1// SPDX-License-Identifier: GPL-2.0 2// 3// mt8192-afe-clk.c -- Mediatek 8192 afe clock ctrl 4// 5// Copyright (c) 2020 MediaTek Inc. 6// Author: Shane Chien <shane.chien@mediatek.com> 7// 8 9#include <linux/arm-smccc.h> 10#include <linux/clk.h> 11#include <linux/mfd/syscon.h> 12#include <linux/regmap.h> 13 14#include "mt8192-afe-clk.h" 15#include "mt8192-afe-common.h" 16 17static const char *aud_clks[CLK_NUM] = { 18 [CLK_AFE] = "aud_afe_clk", 19 [CLK_TML] = "aud_tml_clk", 20 [CLK_APLL22M] = "aud_apll22m_clk", 21 [CLK_APLL24M] = "aud_apll24m_clk", 22 [CLK_APLL1_TUNER] = "aud_apll1_tuner_clk", 23 [CLK_APLL2_TUNER] = "aud_apll2_tuner_clk", 24 [CLK_NLE] = "aud_nle", 25 [CLK_INFRA_SYS_AUDIO] = "aud_infra_clk", 26 [CLK_INFRA_AUDIO_26M] = "aud_infra_26m_clk", 27 [CLK_MUX_AUDIO] = "top_mux_audio", 28 [CLK_MUX_AUDIOINTBUS] = "top_mux_audio_int", 29 [CLK_TOP_MAINPLL_D4_D4] = "top_mainpll_d4_d4", 30 [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1", 31 [CLK_TOP_APLL1_CK] = "top_apll1_ck", 32 [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2", 33 [CLK_TOP_APLL2_CK] = "top_apll2_ck", 34 [CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1", 35 [CLK_TOP_APLL1_D4] = "top_apll1_d4", 36 [CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2", 37 [CLK_TOP_APLL2_D4] = "top_apll2_d4", 38 [CLK_TOP_MUX_AUDIO_H] = "top_mux_audio_h", 39 [CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel", 40 [CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel", 41 [CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel", 42 [CLK_TOP_I2S3_M_SEL] = "top_i2s3_m_sel", 43 [CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel", 44 [CLK_TOP_I2S5_M_SEL] = "top_i2s5_m_sel", 45 [CLK_TOP_I2S6_M_SEL] = "top_i2s6_m_sel", 46 [CLK_TOP_I2S7_M_SEL] = "top_i2s7_m_sel", 47 [CLK_TOP_I2S8_M_SEL] = "top_i2s8_m_sel", 48 [CLK_TOP_I2S9_M_SEL] = "top_i2s9_m_sel", 49 [CLK_TOP_APLL12_DIV0] = "top_apll12_div0", 50 [CLK_TOP_APLL12_DIV1] = "top_apll12_div1", 51 [CLK_TOP_APLL12_DIV2] = "top_apll12_div2", 52 [CLK_TOP_APLL12_DIV3] = "top_apll12_div3", 53 [CLK_TOP_APLL12_DIV4] = "top_apll12_div4", 54 [CLK_TOP_APLL12_DIVB] = "top_apll12_divb", 55 [CLK_TOP_APLL12_DIV5] = "top_apll12_div5", 56 [CLK_TOP_APLL12_DIV6] = "top_apll12_div6", 57 [CLK_TOP_APLL12_DIV7] = "top_apll12_div7", 58 [CLK_TOP_APLL12_DIV8] = "top_apll12_div8", 59 [CLK_TOP_APLL12_DIV9] = "top_apll12_div9", 60 [CLK_CLK26M] = "top_clk26m_clk", 61}; 62 63int mt8192_set_audio_int_bus_parent(struct mtk_base_afe *afe, 64 int clk_id) 65{ 66 struct mt8192_afe_private *afe_priv = afe->platform_priv; 67 int ret; 68 69 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], 70 afe_priv->clk[clk_id]); 71 if (ret) { 72 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 73 __func__, aud_clks[CLK_MUX_AUDIOINTBUS], 74 aud_clks[clk_id], ret); 75 } 76 77 return ret; 78} 79 80static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable) 81{ 82 struct mt8192_afe_private *afe_priv = afe->platform_priv; 83 int ret; 84 85 if (enable) { 86 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]); 87 if (ret) { 88 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 89 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret); 90 goto EXIT; 91 } 92 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], 93 afe_priv->clk[CLK_TOP_APLL1_CK]); 94 if (ret) { 95 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 96 __func__, aud_clks[CLK_TOP_MUX_AUD_1], 97 aud_clks[CLK_TOP_APLL1_CK], ret); 98 goto EXIT; 99 } 100 101 /* 180.6336 / 4 = 45.1584MHz */ 102 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); 103 if (ret) { 104 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 105 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret); 106 goto EXIT; 107 } 108 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], 109 afe_priv->clk[CLK_TOP_APLL1_D4]); 110 if (ret) { 111 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 112 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], 113 aud_clks[CLK_TOP_APLL1_D4], ret); 114 goto EXIT; 115 } 116 } else { 117 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], 118 afe_priv->clk[CLK_CLK26M]); 119 if (ret) { 120 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 121 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], 122 aud_clks[CLK_CLK26M], ret); 123 goto EXIT; 124 } 125 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); 126 127 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], 128 afe_priv->clk[CLK_CLK26M]); 129 if (ret) { 130 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 131 __func__, aud_clks[CLK_TOP_MUX_AUD_1], 132 aud_clks[CLK_CLK26M], ret); 133 goto EXIT; 134 } 135 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); 136 } 137 138EXIT: 139 return ret; 140} 141 142static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable) 143{ 144 struct mt8192_afe_private *afe_priv = afe->platform_priv; 145 int ret; 146 147 if (enable) { 148 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]); 149 if (ret) { 150 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 151 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret); 152 goto EXIT; 153 } 154 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], 155 afe_priv->clk[CLK_TOP_APLL2_CK]); 156 if (ret) { 157 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 158 __func__, aud_clks[CLK_TOP_MUX_AUD_2], 159 aud_clks[CLK_TOP_APLL2_CK], ret); 160 goto EXIT; 161 } 162 163 /* 196.608 / 4 = 49.152MHz */ 164 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]); 165 if (ret) { 166 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 167 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret); 168 goto EXIT; 169 } 170 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], 171 afe_priv->clk[CLK_TOP_APLL2_D4]); 172 if (ret) { 173 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 174 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], 175 aud_clks[CLK_TOP_APLL2_D4], ret); 176 goto EXIT; 177 } 178 } else { 179 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], 180 afe_priv->clk[CLK_CLK26M]); 181 if (ret) { 182 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 183 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], 184 aud_clks[CLK_CLK26M], ret); 185 goto EXIT; 186 } 187 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]); 188 189 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], 190 afe_priv->clk[CLK_CLK26M]); 191 if (ret) { 192 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 193 __func__, aud_clks[CLK_TOP_MUX_AUD_2], 194 aud_clks[CLK_CLK26M], ret); 195 goto EXIT; 196 } 197 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]); 198 } 199 200EXIT: 201 return ret; 202} 203 204int mt8192_afe_enable_clock(struct mtk_base_afe *afe) 205{ 206 struct mt8192_afe_private *afe_priv = afe->platform_priv; 207 int ret; 208 209 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); 210 if (ret) { 211 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 212 __func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret); 213 goto EXIT; 214 } 215 216 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]); 217 if (ret) { 218 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 219 __func__, aud_clks[CLK_INFRA_AUDIO_26M], ret); 220 goto EXIT; 221 } 222 223 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]); 224 if (ret) { 225 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 226 __func__, aud_clks[CLK_MUX_AUDIO], ret); 227 goto EXIT; 228 } 229 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], 230 afe_priv->clk[CLK_CLK26M]); 231 if (ret) { 232 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 233 __func__, aud_clks[CLK_MUX_AUDIO], 234 aud_clks[CLK_CLK26M], ret); 235 goto EXIT; 236 } 237 238 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); 239 if (ret) { 240 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 241 __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret); 242 goto EXIT; 243 } 244 245 ret = mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M); 246 if (ret) { 247 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 248 __func__, aud_clks[CLK_MUX_AUDIOINTBUS], 249 aud_clks[CLK_CLK26M], ret); 250 goto EXIT; 251 } 252 253 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H], 254 afe_priv->clk[CLK_TOP_APLL2_CK]); 255 if (ret) { 256 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 257 __func__, aud_clks[CLK_TOP_MUX_AUDIO_H], 258 aud_clks[CLK_TOP_APLL2_CK], ret); 259 goto EXIT; 260 } 261 262 ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]); 263 if (ret) { 264 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 265 __func__, aud_clks[CLK_AFE], ret); 266 goto EXIT; 267 } 268 269EXIT: 270 return ret; 271} 272 273void mt8192_afe_disable_clock(struct mtk_base_afe *afe) 274{ 275 struct mt8192_afe_private *afe_priv = afe->platform_priv; 276 277 clk_disable_unprepare(afe_priv->clk[CLK_AFE]); 278 mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M); 279 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); 280 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]); 281 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]); 282 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); 283} 284 285int mt8192_apll1_enable(struct mtk_base_afe *afe) 286{ 287 struct mt8192_afe_private *afe_priv = afe->platform_priv; 288 int ret; 289 290 /* setting for APLL */ 291 apll1_mux_setting(afe, true); 292 293 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]); 294 if (ret) { 295 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 296 __func__, aud_clks[CLK_APLL22M], ret); 297 goto EXIT; 298 } 299 300 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]); 301 if (ret) { 302 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 303 __func__, aud_clks[CLK_APLL1_TUNER], ret); 304 goto EXIT; 305 } 306 307 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 308 0x0000FFF7, 0x00000832); 309 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1); 310 311 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, 312 AFE_22M_ON_MASK_SFT, 313 0x1 << AFE_22M_ON_SFT); 314 315EXIT: 316 return ret; 317} 318 319void mt8192_apll1_disable(struct mtk_base_afe *afe) 320{ 321 struct mt8192_afe_private *afe_priv = afe->platform_priv; 322 323 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, 324 AFE_22M_ON_MASK_SFT, 325 0x0 << AFE_22M_ON_SFT); 326 327 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0); 328 329 clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]); 330 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]); 331 332 apll1_mux_setting(afe, false); 333} 334 335int mt8192_apll2_enable(struct mtk_base_afe *afe) 336{ 337 struct mt8192_afe_private *afe_priv = afe->platform_priv; 338 int ret; 339 340 /* setting for APLL */ 341 apll2_mux_setting(afe, true); 342 343 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]); 344 if (ret) { 345 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 346 __func__, aud_clks[CLK_APLL24M], ret); 347 goto EXIT; 348 } 349 350 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]); 351 if (ret) { 352 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 353 __func__, aud_clks[CLK_APLL2_TUNER], ret); 354 goto EXIT; 355 } 356 357 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 358 0x0000FFF7, 0x00000634); 359 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1); 360 361 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, 362 AFE_24M_ON_MASK_SFT, 363 0x1 << AFE_24M_ON_SFT); 364 365EXIT: 366 return ret; 367} 368 369void mt8192_apll2_disable(struct mtk_base_afe *afe) 370{ 371 struct mt8192_afe_private *afe_priv = afe->platform_priv; 372 373 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, 374 AFE_24M_ON_MASK_SFT, 375 0x0 << AFE_24M_ON_SFT); 376 377 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0); 378 379 clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]); 380 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]); 381 382 apll2_mux_setting(afe, false); 383} 384 385int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll) 386{ 387 return (apll == MT8192_APLL1) ? 180633600 : 196608000; 388} 389 390int mt8192_get_apll_by_rate(struct mtk_base_afe *afe, int rate) 391{ 392 return ((rate % 8000) == 0) ? MT8192_APLL2 : MT8192_APLL1; 393} 394 395int mt8192_get_apll_by_name(struct mtk_base_afe *afe, const char *name) 396{ 397 if (strcmp(name, APLL1_W_NAME) == 0) 398 return MT8192_APLL1; 399 else 400 return MT8192_APLL2; 401} 402 403/* mck */ 404struct mt8192_mck_div { 405 int m_sel_id; 406 int div_clk_id; 407 /* below will be deprecated */ 408 int div_pdn_reg; 409 int div_pdn_mask_sft; 410 int div_reg; 411 int div_mask_sft; 412 int div_mask; 413 int div_sft; 414 int div_apll_sel_reg; 415 int div_apll_sel_mask_sft; 416 int div_apll_sel_sft; 417}; 418 419static const struct mt8192_mck_div mck_div[MT8192_MCK_NUM] = { 420 [MT8192_I2S0_MCK] = { 421 .m_sel_id = CLK_TOP_I2S0_M_SEL, 422 .div_clk_id = CLK_TOP_APLL12_DIV0, 423 .div_pdn_reg = CLK_AUDDIV_0, 424 .div_pdn_mask_sft = APLL12_DIV0_PDN_MASK_SFT, 425 .div_reg = CLK_AUDDIV_2, 426 .div_mask_sft = APLL12_CK_DIV0_MASK_SFT, 427 .div_mask = APLL12_CK_DIV0_MASK, 428 .div_sft = APLL12_CK_DIV0_SFT, 429 .div_apll_sel_reg = CLK_AUDDIV_0, 430 .div_apll_sel_mask_sft = APLL_I2S0_MCK_SEL_MASK_SFT, 431 .div_apll_sel_sft = APLL_I2S0_MCK_SEL_SFT, 432 }, 433 [MT8192_I2S1_MCK] = { 434 .m_sel_id = CLK_TOP_I2S1_M_SEL, 435 .div_clk_id = CLK_TOP_APLL12_DIV1, 436 .div_pdn_reg = CLK_AUDDIV_0, 437 .div_pdn_mask_sft = APLL12_DIV1_PDN_MASK_SFT, 438 .div_reg = CLK_AUDDIV_2, 439 .div_mask_sft = APLL12_CK_DIV1_MASK_SFT, 440 .div_mask = APLL12_CK_DIV1_MASK, 441 .div_sft = APLL12_CK_DIV1_SFT, 442 .div_apll_sel_reg = CLK_AUDDIV_0, 443 .div_apll_sel_mask_sft = APLL_I2S1_MCK_SEL_MASK_SFT, 444 .div_apll_sel_sft = APLL_I2S1_MCK_SEL_SFT, 445 }, 446 [MT8192_I2S2_MCK] = { 447 .m_sel_id = CLK_TOP_I2S2_M_SEL, 448 .div_clk_id = CLK_TOP_APLL12_DIV2, 449 .div_pdn_reg = CLK_AUDDIV_0, 450 .div_pdn_mask_sft = APLL12_DIV2_PDN_MASK_SFT, 451 .div_reg = CLK_AUDDIV_2, 452 .div_mask_sft = APLL12_CK_DIV2_MASK_SFT, 453 .div_mask = APLL12_CK_DIV2_MASK, 454 .div_sft = APLL12_CK_DIV2_SFT, 455 .div_apll_sel_reg = CLK_AUDDIV_0, 456 .div_apll_sel_mask_sft = APLL_I2S2_MCK_SEL_MASK_SFT, 457 .div_apll_sel_sft = APLL_I2S2_MCK_SEL_SFT, 458 }, 459 [MT8192_I2S3_MCK] = { 460 .m_sel_id = CLK_TOP_I2S3_M_SEL, 461 .div_clk_id = CLK_TOP_APLL12_DIV3, 462 .div_pdn_reg = CLK_AUDDIV_0, 463 .div_pdn_mask_sft = APLL12_DIV3_PDN_MASK_SFT, 464 .div_reg = CLK_AUDDIV_2, 465 .div_mask_sft = APLL12_CK_DIV3_MASK_SFT, 466 .div_mask = APLL12_CK_DIV3_MASK, 467 .div_sft = APLL12_CK_DIV3_SFT, 468 .div_apll_sel_reg = CLK_AUDDIV_0, 469 .div_apll_sel_mask_sft = APLL_I2S3_MCK_SEL_MASK_SFT, 470 .div_apll_sel_sft = APLL_I2S3_MCK_SEL_SFT, 471 }, 472 [MT8192_I2S4_MCK] = { 473 .m_sel_id = CLK_TOP_I2S4_M_SEL, 474 .div_clk_id = CLK_TOP_APLL12_DIV4, 475 .div_pdn_reg = CLK_AUDDIV_0, 476 .div_pdn_mask_sft = APLL12_DIV4_PDN_MASK_SFT, 477 .div_reg = CLK_AUDDIV_3, 478 .div_mask_sft = APLL12_CK_DIV4_MASK_SFT, 479 .div_mask = APLL12_CK_DIV4_MASK, 480 .div_sft = APLL12_CK_DIV4_SFT, 481 .div_apll_sel_reg = CLK_AUDDIV_0, 482 .div_apll_sel_mask_sft = APLL_I2S4_MCK_SEL_MASK_SFT, 483 .div_apll_sel_sft = APLL_I2S4_MCK_SEL_SFT, 484 }, 485 [MT8192_I2S4_BCK] = { 486 .m_sel_id = -1, 487 .div_clk_id = CLK_TOP_APLL12_DIVB, 488 .div_pdn_reg = CLK_AUDDIV_0, 489 .div_pdn_mask_sft = APLL12_DIVB_PDN_MASK_SFT, 490 .div_reg = CLK_AUDDIV_2, 491 .div_mask_sft = APLL12_CK_DIVB_MASK_SFT, 492 .div_mask = APLL12_CK_DIVB_MASK, 493 .div_sft = APLL12_CK_DIVB_SFT, 494 }, 495 [MT8192_I2S5_MCK] = { 496 .m_sel_id = CLK_TOP_I2S5_M_SEL, 497 .div_clk_id = CLK_TOP_APLL12_DIV5, 498 .div_pdn_reg = CLK_AUDDIV_0, 499 .div_pdn_mask_sft = APLL12_DIV5_PDN_MASK_SFT, 500 .div_reg = CLK_AUDDIV_3, 501 .div_mask_sft = APLL12_CK_DIV5_MASK_SFT, 502 .div_mask = APLL12_CK_DIV5_MASK, 503 .div_sft = APLL12_CK_DIV5_SFT, 504 .div_apll_sel_reg = CLK_AUDDIV_0, 505 .div_apll_sel_mask_sft = APLL_I2S5_MCK_SEL_MASK_SFT, 506 .div_apll_sel_sft = APLL_I2S5_MCK_SEL_SFT, 507 }, 508 [MT8192_I2S6_MCK] = { 509 .m_sel_id = CLK_TOP_I2S6_M_SEL, 510 .div_clk_id = CLK_TOP_APLL12_DIV6, 511 .div_pdn_reg = CLK_AUDDIV_0, 512 .div_pdn_mask_sft = APLL12_DIV6_PDN_MASK_SFT, 513 .div_reg = CLK_AUDDIV_3, 514 .div_mask_sft = APLL12_CK_DIV6_MASK_SFT, 515 .div_mask = APLL12_CK_DIV6_MASK, 516 .div_sft = APLL12_CK_DIV6_SFT, 517 .div_apll_sel_reg = CLK_AUDDIV_0, 518 .div_apll_sel_mask_sft = APLL_I2S6_MCK_SEL_MASK_SFT, 519 .div_apll_sel_sft = APLL_I2S6_MCK_SEL_SFT, 520 }, 521 [MT8192_I2S7_MCK] = { 522 .m_sel_id = CLK_TOP_I2S7_M_SEL, 523 .div_clk_id = CLK_TOP_APLL12_DIV7, 524 .div_pdn_reg = CLK_AUDDIV_0, 525 .div_pdn_mask_sft = APLL12_DIV7_PDN_MASK_SFT, 526 .div_reg = CLK_AUDDIV_4, 527 .div_mask_sft = APLL12_CK_DIV7_MASK_SFT, 528 .div_mask = APLL12_CK_DIV7_MASK, 529 .div_sft = APLL12_CK_DIV7_SFT, 530 .div_apll_sel_reg = CLK_AUDDIV_0, 531 .div_apll_sel_mask_sft = APLL_I2S7_MCK_SEL_MASK_SFT, 532 .div_apll_sel_sft = APLL_I2S7_MCK_SEL_SFT, 533 }, 534 [MT8192_I2S8_MCK] = { 535 .m_sel_id = CLK_TOP_I2S8_M_SEL, 536 .div_clk_id = CLK_TOP_APLL12_DIV8, 537 .div_pdn_reg = CLK_AUDDIV_0, 538 .div_pdn_mask_sft = APLL12_DIV8_PDN_MASK_SFT, 539 .div_reg = CLK_AUDDIV_4, 540 .div_mask_sft = APLL12_CK_DIV8_MASK_SFT, 541 .div_mask = APLL12_CK_DIV8_MASK, 542 .div_sft = APLL12_CK_DIV8_SFT, 543 .div_apll_sel_reg = CLK_AUDDIV_0, 544 .div_apll_sel_mask_sft = APLL_I2S8_MCK_SEL_MASK_SFT, 545 .div_apll_sel_sft = APLL_I2S8_MCK_SEL_SFT, 546 }, 547 [MT8192_I2S9_MCK] = { 548 .m_sel_id = CLK_TOP_I2S9_M_SEL, 549 .div_clk_id = CLK_TOP_APLL12_DIV9, 550 .div_pdn_reg = CLK_AUDDIV_0, 551 .div_pdn_mask_sft = APLL12_DIV9_PDN_MASK_SFT, 552 .div_reg = CLK_AUDDIV_4, 553 .div_mask_sft = APLL12_CK_DIV9_MASK_SFT, 554 .div_mask = APLL12_CK_DIV9_MASK, 555 .div_sft = APLL12_CK_DIV9_SFT, 556 .div_apll_sel_reg = CLK_AUDDIV_0, 557 .div_apll_sel_mask_sft = APLL_I2S9_MCK_SEL_MASK_SFT, 558 .div_apll_sel_sft = APLL_I2S9_MCK_SEL_SFT, 559 }, 560}; 561 562int mt8192_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate) 563{ 564 struct mt8192_afe_private *afe_priv = afe->platform_priv; 565 int apll = mt8192_get_apll_by_rate(afe, rate); 566 int apll_clk_id = apll == MT8192_APLL1 ? 567 CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2; 568 int m_sel_id = mck_div[mck_id].m_sel_id; 569 int div_clk_id = mck_div[mck_id].div_clk_id; 570 int ret; 571 572 /* select apll */ 573 if (m_sel_id >= 0) { 574 ret = clk_prepare_enable(afe_priv->clk[m_sel_id]); 575 if (ret) { 576 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", 577 __func__, aud_clks[m_sel_id], ret); 578 return ret; 579 } 580 ret = clk_set_parent(afe_priv->clk[m_sel_id], 581 afe_priv->clk[apll_clk_id]); 582 if (ret) { 583 dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n", 584 __func__, aud_clks[m_sel_id], 585 aud_clks[apll_clk_id], ret); 586 return ret; 587 } 588 } 589 590 /* enable div, set rate */ 591 ret = clk_prepare_enable(afe_priv->clk[div_clk_id]); 592 if (ret) { 593 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", 594 __func__, aud_clks[div_clk_id], ret); 595 return ret; 596 } 597 ret = clk_set_rate(afe_priv->clk[div_clk_id], rate); 598 if (ret) { 599 dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n", 600 __func__, aud_clks[div_clk_id], 601 rate, ret); 602 return ret; 603 } 604 605 return 0; 606} 607 608void mt8192_mck_disable(struct mtk_base_afe *afe, int mck_id) 609{ 610 struct mt8192_afe_private *afe_priv = afe->platform_priv; 611 int m_sel_id = mck_div[mck_id].m_sel_id; 612 int div_clk_id = mck_div[mck_id].div_clk_id; 613 614 clk_disable_unprepare(afe_priv->clk[div_clk_id]); 615 if (m_sel_id >= 0) 616 clk_disable_unprepare(afe_priv->clk[m_sel_id]); 617} 618 619int mt8192_init_clock(struct mtk_base_afe *afe) 620{ 621 struct mt8192_afe_private *afe_priv = afe->platform_priv; 622 struct device_node *of_node = afe->dev->of_node; 623 int i = 0; 624 625 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk), 626 GFP_KERNEL); 627 if (!afe_priv->clk) 628 return -ENOMEM; 629 630 for (i = 0; i < CLK_NUM; i++) { 631 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); 632 if (IS_ERR(afe_priv->clk[i])) { 633 dev_warn(afe->dev, "%s devm_clk_get %s fail, ret %ld\n", 634 __func__, 635 aud_clks[i], PTR_ERR(afe_priv->clk[i])); 636 afe_priv->clk[i] = NULL; 637 } 638 } 639 640 afe_priv->apmixedsys = syscon_regmap_lookup_by_phandle(of_node, 641 "mediatek,apmixedsys"); 642 if (IS_ERR(afe_priv->apmixedsys)) { 643 dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n", 644 __func__, PTR_ERR(afe_priv->apmixedsys)); 645 return PTR_ERR(afe_priv->apmixedsys); 646 } 647 648 afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node, 649 "mediatek,topckgen"); 650 if (IS_ERR(afe_priv->topckgen)) { 651 dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n", 652 __func__, PTR_ERR(afe_priv->topckgen)); 653 return PTR_ERR(afe_priv->topckgen); 654 } 655 656 afe_priv->infracfg = syscon_regmap_lookup_by_phandle(of_node, 657 "mediatek,infracfg"); 658 if (IS_ERR(afe_priv->infracfg)) { 659 dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n", 660 __func__, PTR_ERR(afe_priv->infracfg)); 661 return PTR_ERR(afe_priv->infracfg); 662 } 663 664 return 0; 665} 666