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9c92ab61 |
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29-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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759fa961 |
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01-Jun-2016 |
Stephen Boyd <stephen.boyd@linaro.org> |
clk: vt8500: Migrate to clk_hw based registration APIs Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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c03d795b |
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07-Jun-2016 |
Roman Volkov <rvolkov@v1ros.org> |
clk: vt8500: rework wm8650_find_pll_bits() PLL clock on WM8650 is calculated in the following way: M * parent [O1] => / P [O2] => / D [O3] Where O2 is 600MHz >= (M * parent) / P >= 300MHz. Current algorithm does not met this requirement, so that the function may return rates which are not supported by the hardware. This patch fixes the algorithm and simplifies the code, reducing the calculation time by ~10000 times (according to usermode app) by removing the nested loops. Signed-off-by: Roman Volkov <rvolkov@v1ros.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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27a0becc |
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07-Jun-2016 |
Arnd Bergmann <arnd@arndb.de> |
clk: vt8500: fix gcc-4.9 warnings This fixes some false positive warnings we get with older compiler versions: clk-vt8500.c: In function ‘wm8650_find_pll_bits’: clk-vt8500.c:430:12: ‘best_div2’ may be used uninitialized in this function clk-vt8500.c:429:12: ‘best_div1’ may be used uninitialized in this function clk-vt8500.c:428:14: ‘best_mul’ may be used uninitialized in this function clk-vt8500.c: In function ‘wm8750_find_pll_bits’: clk-vt8500.c:509:12: ‘best_div2’ may be used uninitialized in this function clk-vt8500.c:508:12: ‘best_div1’ may be used uninitialized in this function clk-vt8500.c:507:14: ‘best_mul’ may be used uninitialized in this function clk-vt8500.c: In function ‘wm8850_find_pll_bits’: clk-vt8500.c:560:12: ‘best_div2’ may be used uninitialized in this function clk-vt8500.c:559:12: ‘best_div1’ may be used uninitialized in this function clk-vt8500.c:558:14: ‘best_mul’ may be used uninitialized in this function As the local variables are only use for temporaries, we can just as well assign the final values directly, which also makes the code slightly shorter. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Roman Volkov <rvolkov@v1ros.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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7001ec56 |
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01-Feb-2016 |
Arnd Bergmann <arnd@arndb.de> |
clk: vt8500: don't return possibly uninitialized data The clk-vt8500.c driver would previously enter an endless loop when invalid settings got requested, this was now fixed. However, the driver will now return uninitialized data for a subset of those cases instead, as the gcc correctly warns: clk/clk-vt8500.c: In function 'wm8650_find_pll_bits': clk/clk-vt8500.c:423:12: error: 'best_div2' may be used uninitialized in this function [-Werror=maybe-uninitialized] *divisor2 = best_div2; ^ clk/clk-vt8500.c:422:12: error: 'best_div1' may be used uninitialized in this function [-Werror=maybe-uninitialized] *divisor1 = best_div1; ^ clk/clk-vt8500.c:421:14: error: 'best_mul' may be used uninitialized in this function [-Werror=maybe-uninitialized] *multiplier = best_mul; This reworks the error handling in the driver so we now return -EINVAL from clk_round_rate() and clk_set_rate() when we get impossible inputs. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 090341b0a95d ("clk: vt8500: fix sign of possible PLL values") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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090341b0 |
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01-Oct-2015 |
Andrzej Hajda <a.hajda@samsung.com> |
clk: vt8500: fix sign of possible PLL values With unsigned values underflow in loops can occur resulting in theoretically infinite loops. The problem has been detected using proposed semantic patch scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2038576 Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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7acc3bca |
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08-Oct-2013 |
Sachin Kamat <sachin.kamat@linaro.org> |
clk: vt8500: Staticize vtwm_pll_ops 'vtwm_pll_ops' is local to this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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f44089a7 |
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04-Sep-2013 |
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
ARM: vt8500: prepare for arch-wide .init_time callback Current vt8500 board init calls of_clk_init() from vtwm_clk_init. To allow consolidation of DT driven .time_init, move of_clock_init() to a temporary .time_init callback that will be removed when arch-wide callback is available. With previous pmc_base parsing helper for vt8500 clock providers, we can also safely remove the call to vtwm_clk_init() and get rid of some includes. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Tony Prisk <linux@prisktech.co.nz> Acked-by: Mike Turquette <mturquette@linaro.org>
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f9e4a18d |
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04-Sep-2013 |
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
clk: vt8500: parse pmc_base from clock driver Currently, clock providers for vt8500 depend on machine_init providing pmc_base address before calling of_clk_init. With upcoming arch-wide .time_init calling of_clk_init, we should make clock providers independent of mach code. This adds a pmc_base parsing helper to current clock provider that gets called if there is no pmc_base set, yet. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Tony Prisk <linux@prisktech.co.nz> Acked-by: Mike Turquette <mturquette@linaro.org>
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419e321d |
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17-May-2013 |
Tony Prisk <linux@prisktech.co.nz> |
clk: vt8500: Fix unbalanced spinlock in vt8500_dclk_set_rate() With the addition of a DVO clock, a bug is now evident in the vt8500 clock code: [ 0.290000] WARNING: at init/main.c:698 do_one_initcall+0x158/0x18c() [ 0.300000] initcall wm8505fb_driver_init+0x0/0xc returned with disabled int This is caused by an unbalanced spinlock in vt8500_dclk_set_rate(). Replace the second call to spin_lock_irqsave() with spin_unlock_irqrestore(). Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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65f2c58f |
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13-May-2013 |
Tony Prisk <linux@prisktech.co.nz> |
clk: vt8500: Remove unnecessary divisor adjustment in vtwm_dclk_set_rate() The divisor adjustment code to ensure that a divisor is not rounded down, thereby giving a rate higher than requested, is unnecessary and in some instances results in the actual rate being much lower than requested due to rounding errors. The test is already performed in vtwm_dclk_round_rate(), which is always called when clk_set_rate is called. Due to rounding errors in the line: divisor = parent_rate / rate (clk-vt8500.c:160) we will sometimes end up adjusting the divisor twice - first in round_rate and then again in set_rate. This patch removes the test/adjustment in vtwm_dclk_set_rate. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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518d4709 |
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13-May-2013 |
Tony Prisk <linux@prisktech.co.nz> |
clk: vt8500: Add support for clocks on the WM8850 SoCs The WM8850 has a different PLL clock to the previous versions. This patch adds support for the WM8850-style PLL clocks. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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bdca21ec |
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13-Apr-2013 |
Tony Prisk <linux@prisktech.co.nz> |
clk: vt8500: Missing breaks in vtwm_pll_round_rate/_set_rate. The case of PLL_TYPE_WM8750 in both these functions is missing a break statement causing a fall-through to the default: case. Insert the missing break statements. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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d6d1053a |
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01-Mar-2013 |
Arnd Bergmann <arnd@arndb.de> |
clk: vt8500: Fix "fix device clock divisor calculations" Patch 72480014b8 "Fix device clock divisor calculations" was apparently rebased incorrectly before it got upstream, causing a build error. Replacing the "prate" pointer with the local parent_rate is most likely the correct solution. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Tony Prisk <linux@prisktech.co.nz> Cc: Mike Turquette <mturquette@linaro.org>
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5b6e0adb |
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03-Jan-2013 |
Prashant Gaikwad <pgaikwad@nvidia.com> |
clk: vt8500: Use common of_clk_init() function Use common of_clk_init() function for clock initialization. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: added entry for wm8750-pll-clock] Signed-off-by: Mike Turquette <mturquette@linaro.org>
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abb165a8 |
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27-Dec-2012 |
Tony Prisk <linux@prisktech.co.nz> |
clk: vt8500: Add support for WM8750/WM8850 PLL clocks This patch adds support for the new PLL module found in WM8750 and WM8850 SoCs. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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58eb5a67 |
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26-Dec-2012 |
Tony Prisk <linux@prisktech.co.nz> |
clk: vt8500: Fix division-by-0 when requested rate=0 A request to vt8500_dclk_(round_rate/set_rate) with rate=0 results in a division-by-0 in the kernel. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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72480014 |
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26-Dec-2012 |
Tony Prisk <linux@prisktech.co.nz> |
clk: vt8500: Fix device clock divisor calculations When calculating device clock divisor values in set_rate and round_rate, we do a simple integer divide. If parent_rate / rate has a fraction, this is dropped which results in the device clock being set too high. This patch corrects the problem by adding 1 to the calculated divisor if the division would have had a decimal result. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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35a5db55 |
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26-Dec-2012 |
Tony Prisk <linux@prisktech.co.nz> |
clk: vt8500: Fix error in PLL calculations on non-exact match. When a PLL frequency calculation is performed and a non-exact match is found the wrong multiplier and divisors are returned. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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973e1d1d |
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18-Oct-2012 |
Tony Prisk <linux@prisktech.co.nz> |
CLK: vt8500: Fix SDMMC clk special cases This patch adds some additional handling for the SDMMC special case in round_rate and set_rate which results in invalid divisor messages at boot time. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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85814d69 |
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21-Aug-2012 |
Tony Prisk <linux@prisktech.co.nz> |
arm: vt8500: clk: Add Common Clock Framework support This patch adds common clock framework support for arch-vt8500. Support for PLL and device clocks on VT8500, WM8505 and WM8650 are included. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Acked-by: Mike Turquette <mturquette@linaro.org>
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