1// SPDX-License-Identifier: GPL-2.0 2// 3// ALSA SoC IMX MQS driver 4// 5// Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 6// Copyright 2019 NXP 7 8#include <linux/clk.h> 9#include <linux/module.h> 10#include <linux/moduleparam.h> 11#include <linux/mfd/syscon.h> 12#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 13#include <linux/pm_runtime.h> 14#include <linux/pm.h> 15#include <linux/slab.h> 16#include <sound/soc.h> 17#include <sound/pcm.h> 18#include <sound/initval.h> 19 20#define REG_MQS_CTRL 0x00 21 22#define MQS_EN_MASK (0x1 << 28) 23#define MQS_EN_SHIFT (28) 24#define MQS_SW_RST_MASK (0x1 << 24) 25#define MQS_SW_RST_SHIFT (24) 26#define MQS_OVERSAMPLE_MASK (0x1 << 20) 27#define MQS_OVERSAMPLE_SHIFT (20) 28#define MQS_CLK_DIV_MASK (0xFF << 0) 29#define MQS_CLK_DIV_SHIFT (0) 30 31/** 32 * struct fsl_mqs_soc_data - soc specific data 33 * 34 * @use_gpr: control register is in General Purpose Register group 35 * @ctrl_off: control register offset 36 * @en_mask: enable bit mask 37 * @en_shift: enable bit shift 38 * @rst_mask: reset bit mask 39 * @rst_shift: reset bit shift 40 * @osr_mask: oversample bit mask 41 * @osr_shift: oversample bit shift 42 * @div_mask: clock divider mask 43 * @div_shift: clock divider bit shift 44 */ 45struct fsl_mqs_soc_data { 46 bool use_gpr; 47 int ctrl_off; 48 int en_mask; 49 int en_shift; 50 int rst_mask; 51 int rst_shift; 52 int osr_mask; 53 int osr_shift; 54 int div_mask; 55 int div_shift; 56}; 57 58/* codec private data */ 59struct fsl_mqs { 60 struct regmap *regmap; 61 struct clk *mclk; 62 struct clk *ipg; 63 const struct fsl_mqs_soc_data *soc; 64 65 unsigned int reg_mqs_ctrl; 66}; 67 68#define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 69#define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE 70 71static int fsl_mqs_hw_params(struct snd_pcm_substream *substream, 72 struct snd_pcm_hw_params *params, 73 struct snd_soc_dai *dai) 74{ 75 struct snd_soc_component *component = dai->component; 76 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 77 unsigned long mclk_rate; 78 int div, res; 79 int lrclk; 80 81 mclk_rate = clk_get_rate(mqs_priv->mclk); 82 lrclk = params_rate(params); 83 84 /* 85 * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate; 86 * if repeat_rate is 8, mqs can achieve better quality. 87 * oversample rate is fix to 32 currently. 88 */ 89 div = mclk_rate / (32 * lrclk * 2 * 8); 90 res = mclk_rate % (32 * lrclk * 2 * 8); 91 92 if (res == 0 && div > 0 && div <= 256) { 93 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 94 mqs_priv->soc->div_mask, 95 (div - 1) << mqs_priv->soc->div_shift); 96 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 97 mqs_priv->soc->osr_mask, 0); 98 } else { 99 dev_err(component->dev, "can't get proper divider\n"); 100 } 101 102 return 0; 103} 104 105static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 106{ 107 /* Only LEFT_J & SLAVE mode is supported. */ 108 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 109 case SND_SOC_DAIFMT_LEFT_J: 110 break; 111 default: 112 return -EINVAL; 113 } 114 115 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 116 case SND_SOC_DAIFMT_NB_NF: 117 break; 118 default: 119 return -EINVAL; 120 } 121 122 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 123 case SND_SOC_DAIFMT_CBC_CFC: 124 break; 125 default: 126 return -EINVAL; 127 } 128 129 return 0; 130} 131 132static int fsl_mqs_startup(struct snd_pcm_substream *substream, 133 struct snd_soc_dai *dai) 134{ 135 struct snd_soc_component *component = dai->component; 136 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 137 138 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 139 mqs_priv->soc->en_mask, 140 1 << mqs_priv->soc->en_shift); 141 return 0; 142} 143 144static void fsl_mqs_shutdown(struct snd_pcm_substream *substream, 145 struct snd_soc_dai *dai) 146{ 147 struct snd_soc_component *component = dai->component; 148 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 149 150 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 151 mqs_priv->soc->en_mask, 0); 152} 153 154static const struct snd_soc_component_driver soc_codec_fsl_mqs = { 155 .idle_bias_on = 1, 156}; 157 158static const struct snd_soc_dai_ops fsl_mqs_dai_ops = { 159 .startup = fsl_mqs_startup, 160 .shutdown = fsl_mqs_shutdown, 161 .hw_params = fsl_mqs_hw_params, 162 .set_fmt = fsl_mqs_set_dai_fmt, 163}; 164 165static struct snd_soc_dai_driver fsl_mqs_dai = { 166 .name = "fsl-mqs-dai", 167 .playback = { 168 .stream_name = "Playback", 169 .channels_min = 2, 170 .channels_max = 2, 171 .rates = FSL_MQS_RATES, 172 .formats = FSL_MQS_FORMATS, 173 }, 174 .ops = &fsl_mqs_dai_ops, 175}; 176 177static const struct regmap_config fsl_mqs_regmap_config = { 178 .reg_bits = 32, 179 .reg_stride = 4, 180 .val_bits = 32, 181 .max_register = REG_MQS_CTRL, 182 .cache_type = REGCACHE_NONE, 183}; 184 185static int fsl_mqs_probe(struct platform_device *pdev) 186{ 187 struct device_node *np = pdev->dev.of_node; 188 struct device_node *gpr_np = NULL; 189 struct fsl_mqs *mqs_priv; 190 void __iomem *regs; 191 int ret; 192 193 mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL); 194 if (!mqs_priv) 195 return -ENOMEM; 196 197 /* On i.MX6sx the MQS control register is in GPR domain 198 * But in i.MX8QM/i.MX8QXP the control register is moved 199 * to its own domain. 200 */ 201 mqs_priv->soc = of_device_get_match_data(&pdev->dev); 202 203 if (mqs_priv->soc->use_gpr) { 204 gpr_np = of_parse_phandle(np, "gpr", 0); 205 if (!gpr_np) { 206 dev_err(&pdev->dev, "failed to get gpr node by phandle\n"); 207 return -EINVAL; 208 } 209 210 mqs_priv->regmap = syscon_node_to_regmap(gpr_np); 211 of_node_put(gpr_np); 212 if (IS_ERR(mqs_priv->regmap)) { 213 dev_err(&pdev->dev, "failed to get gpr regmap\n"); 214 return PTR_ERR(mqs_priv->regmap); 215 } 216 } else { 217 regs = devm_platform_ioremap_resource(pdev, 0); 218 if (IS_ERR(regs)) 219 return PTR_ERR(regs); 220 221 mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 222 "core", 223 regs, 224 &fsl_mqs_regmap_config); 225 if (IS_ERR(mqs_priv->regmap)) { 226 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 227 PTR_ERR(mqs_priv->regmap)); 228 return PTR_ERR(mqs_priv->regmap); 229 } 230 231 mqs_priv->ipg = devm_clk_get(&pdev->dev, "core"); 232 if (IS_ERR(mqs_priv->ipg)) { 233 dev_err(&pdev->dev, "failed to get the clock: %ld\n", 234 PTR_ERR(mqs_priv->ipg)); 235 return PTR_ERR(mqs_priv->ipg); 236 } 237 } 238 239 mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk"); 240 if (IS_ERR(mqs_priv->mclk)) { 241 dev_err(&pdev->dev, "failed to get the clock: %ld\n", 242 PTR_ERR(mqs_priv->mclk)); 243 return PTR_ERR(mqs_priv->mclk); 244 } 245 246 dev_set_drvdata(&pdev->dev, mqs_priv); 247 pm_runtime_enable(&pdev->dev); 248 249 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs, 250 &fsl_mqs_dai, 1); 251 if (ret) 252 return ret; 253 254 return 0; 255} 256 257static void fsl_mqs_remove(struct platform_device *pdev) 258{ 259 pm_runtime_disable(&pdev->dev); 260} 261 262#ifdef CONFIG_PM 263static int fsl_mqs_runtime_resume(struct device *dev) 264{ 265 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 266 int ret; 267 268 ret = clk_prepare_enable(mqs_priv->ipg); 269 if (ret) { 270 dev_err(dev, "failed to enable ipg clock\n"); 271 return ret; 272 } 273 274 ret = clk_prepare_enable(mqs_priv->mclk); 275 if (ret) { 276 dev_err(dev, "failed to enable mclk clock\n"); 277 clk_disable_unprepare(mqs_priv->ipg); 278 return ret; 279 } 280 281 regmap_write(mqs_priv->regmap, mqs_priv->soc->ctrl_off, mqs_priv->reg_mqs_ctrl); 282 return 0; 283} 284 285static int fsl_mqs_runtime_suspend(struct device *dev) 286{ 287 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 288 289 regmap_read(mqs_priv->regmap, mqs_priv->soc->ctrl_off, &mqs_priv->reg_mqs_ctrl); 290 291 clk_disable_unprepare(mqs_priv->mclk); 292 clk_disable_unprepare(mqs_priv->ipg); 293 294 return 0; 295} 296#endif 297 298static const struct dev_pm_ops fsl_mqs_pm_ops = { 299 SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend, 300 fsl_mqs_runtime_resume, 301 NULL) 302 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 303 pm_runtime_force_resume) 304}; 305 306static const struct fsl_mqs_soc_data fsl_mqs_imx8qm_data = { 307 .use_gpr = false, 308 .ctrl_off = REG_MQS_CTRL, 309 .en_mask = MQS_EN_MASK, 310 .en_shift = MQS_EN_SHIFT, 311 .rst_mask = MQS_SW_RST_MASK, 312 .rst_shift = MQS_SW_RST_SHIFT, 313 .osr_mask = MQS_OVERSAMPLE_MASK, 314 .osr_shift = MQS_OVERSAMPLE_SHIFT, 315 .div_mask = MQS_CLK_DIV_MASK, 316 .div_shift = MQS_CLK_DIV_SHIFT, 317}; 318 319static const struct fsl_mqs_soc_data fsl_mqs_imx6sx_data = { 320 .use_gpr = true, 321 .ctrl_off = IOMUXC_GPR2, 322 .en_mask = IMX6SX_GPR2_MQS_EN_MASK, 323 .en_shift = IMX6SX_GPR2_MQS_EN_SHIFT, 324 .rst_mask = IMX6SX_GPR2_MQS_SW_RST_MASK, 325 .rst_shift = IMX6SX_GPR2_MQS_SW_RST_SHIFT, 326 .osr_mask = IMX6SX_GPR2_MQS_OVERSAMPLE_MASK, 327 .osr_shift = IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT, 328 .div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK, 329 .div_shift = IMX6SX_GPR2_MQS_CLK_DIV_SHIFT, 330}; 331 332static const struct fsl_mqs_soc_data fsl_mqs_imx93_data = { 333 .use_gpr = true, 334 .ctrl_off = 0x20, 335 .en_mask = BIT(1), 336 .en_shift = 1, 337 .rst_mask = BIT(2), 338 .rst_shift = 2, 339 .osr_mask = BIT(3), 340 .osr_shift = 3, 341 .div_mask = GENMASK(15, 8), 342 .div_shift = 8, 343}; 344 345static const struct of_device_id fsl_mqs_dt_ids[] = { 346 { .compatible = "fsl,imx8qm-mqs", .data = &fsl_mqs_imx8qm_data }, 347 { .compatible = "fsl,imx6sx-mqs", .data = &fsl_mqs_imx6sx_data }, 348 { .compatible = "fsl,imx93-mqs", .data = &fsl_mqs_imx93_data }, 349 {} 350}; 351MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids); 352 353static struct platform_driver fsl_mqs_driver = { 354 .probe = fsl_mqs_probe, 355 .remove_new = fsl_mqs_remove, 356 .driver = { 357 .name = "fsl-mqs", 358 .of_match_table = fsl_mqs_dt_ids, 359 .pm = &fsl_mqs_pm_ops, 360 }, 361}; 362 363module_platform_driver(fsl_mqs_driver); 364 365MODULE_AUTHOR("Shengjiu Wang <Shengjiu.Wang@nxp.com>"); 366MODULE_DESCRIPTION("MQS codec driver"); 367MODULE_LICENSE("GPL v2"); 368MODULE_ALIAS("platform:fsl-mqs"); 369