Searched refs:CVMX_ADD_IO_SEG (Results 1 - 25 of 57) sorted by relevance

123

/freebsd-9.3-release/sys/contrib/octeon-sdk/
H A Dcvmx-pexp-defs.h59 return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16;
62 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
70 return CVMX_ADD_IO_SEG(0x00011F0000008580ull);
73 #define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
81 return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
84 #define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
92 return CVMX_ADD_IO_SEG(0x00011F0000008250ull);
95 #define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
103 return CVMX_ADD_IO_SEG(0x00011F0000008260ull);
106 #define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(
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H A Dcvmx-spx0-defs.h61 return CVMX_ADD_IO_SEG(0x0001180090000388ull);
64 #define CVMX_SPX0_PLL_BW_CTL (CVMX_ADD_IO_SEG(0x0001180090000388ull))
72 return CVMX_ADD_IO_SEG(0x0001180090000380ull);
75 #define CVMX_SPX0_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180090000380ull))
H A Dcvmx-pcmx-defs.h63 return CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384;
66 #define CVMX_PCMX_DMA_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384)
76 return CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384;
79 #define CVMX_PCMX_INT_ENA(offset) (CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384)
89 return CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384;
92 #define CVMX_PCMX_INT_SUM(offset) (CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384)
102 return CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384;
105 #define CVMX_PCMX_RXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384)
115 return CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384;
118 #define CVMX_PCMX_RXCNT(offset) (CVMX_ADD_IO_SEG(
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H A Dcvmx-uahcx-defs.h61 return CVMX_ADD_IO_SEG(0x00016F0000000028ull);
64 #define CVMX_UAHCX_EHCI_ASYNCLISTADDR(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000028ull))
72 return CVMX_ADD_IO_SEG(0x00016F0000000050ull);
75 #define CVMX_UAHCX_EHCI_CONFIGFLAG(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000050ull))
83 return CVMX_ADD_IO_SEG(0x00016F0000000020ull);
86 #define CVMX_UAHCX_EHCI_CTRLDSSEGMENT(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000020ull))
94 return CVMX_ADD_IO_SEG(0x00016F000000001Cull);
97 #define CVMX_UAHCX_EHCI_FRINDEX(block_id) (CVMX_ADD_IO_SEG(0x00016F000000001Cull))
105 return CVMX_ADD_IO_SEG(0x00016F0000000000ull);
108 #define CVMX_UAHCX_EHCI_HCCAPBASE(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-led-defs.h61 return CVMX_ADD_IO_SEG(0x0001180000001A48ull);
64 #define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
72 return CVMX_ADD_IO_SEG(0x0001180000001A08ull);
75 #define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
83 return CVMX_ADD_IO_SEG(0x0001180000001AF8ull);
86 #define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
94 return CVMX_ADD_IO_SEG(0x0001180000001A18ull);
97 #define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
105 return CVMX_ADD_IO_SEG(0x0001180000001A00ull);
108 #define CVMX_LED_EN (CVMX_ADD_IO_SEG(
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H A Dcvmx-dpi-defs.h61 return CVMX_ADD_IO_SEG(0x0001DF0000000000ull);
64 #define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
72 return CVMX_ADD_IO_SEG(0x0001DF0000000040ull);
75 #define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
83 return CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8;
86 #define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
94 return CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8;
97 #define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
105 return CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8;
108 #define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(
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H A Dcvmx-smi-defs.h61 return CVMX_ADD_IO_SEG(0x0001180000001828ull);
64 #define CVMX_SMI_DRV_CTL (CVMX_ADD_IO_SEG(0x0001180000001828ull))
H A Dcvmx-stxx-defs.h62 return CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull;
65 #define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
74 return CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull;
77 #define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
86 return CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull;
89 #define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
98 return CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull;
101 #define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
110 return CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull;
113 #define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-rad-defs.h61 return CVMX_ADD_IO_SEG(0x0001180070001000ull);
64 #define CVMX_RAD_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070001000ull))
72 return CVMX_ADD_IO_SEG(0x0001180070001008ull);
75 #define CVMX_RAD_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070001008ull))
83 return CVMX_ADD_IO_SEG(0x0001180070001010ull);
86 #define CVMX_RAD_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070001010ull))
94 return CVMX_ADD_IO_SEG(0x0001180070000080ull);
97 #define CVMX_RAD_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180070000080ull))
105 return CVMX_ADD_IO_SEG(0x0001180070000008ull);
108 #define CVMX_RAD_REG_CMD_BUF (CVMX_ADD_IO_SEG(
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H A Dcvmx-asx0-defs.h61 return CVMX_ADD_IO_SEG(0x00011800B0000208ull);
64 #define CVMX_ASX0_DBG_DATA_DRV (CVMX_ADD_IO_SEG(0x00011800B0000208ull))
72 return CVMX_ADD_IO_SEG(0x00011800B0000200ull);
75 #define CVMX_ASX0_DBG_DATA_ENABLE (CVMX_ADD_IO_SEG(0x00011800B0000200ull))
H A Dcvmx-ndf-defs.h61 return CVMX_ADD_IO_SEG(0x0001070001000018ull);
64 #define CVMX_NDF_BT_PG_INFO (CVMX_ADD_IO_SEG(0x0001070001000018ull))
72 return CVMX_ADD_IO_SEG(0x0001070001000000ull);
75 #define CVMX_NDF_CMD (CVMX_ADD_IO_SEG(0x0001070001000000ull))
83 return CVMX_ADD_IO_SEG(0x0001070001000030ull);
86 #define CVMX_NDF_DRBELL (CVMX_ADD_IO_SEG(0x0001070001000030ull))
94 return CVMX_ADD_IO_SEG(0x0001070001000010ull);
97 #define CVMX_NDF_ECC_CNT (CVMX_ADD_IO_SEG(0x0001070001000010ull))
105 return CVMX_ADD_IO_SEG(0x0001070001000020ull);
108 #define CVMX_NDF_INT (CVMX_ADD_IO_SEG(
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H A Dcvmx-zip-defs.h61 return CVMX_ADD_IO_SEG(0x0001180038000080ull);
64 #define CVMX_ZIP_CMD_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180038000080ull))
72 return CVMX_ADD_IO_SEG(0x0001180038000008ull);
75 #define CVMX_ZIP_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180038000008ull))
83 return CVMX_ADD_IO_SEG(0x0001180038000000ull);
86 #define CVMX_ZIP_CMD_CTL (CVMX_ADD_IO_SEG(0x0001180038000000ull))
94 return CVMX_ADD_IO_SEG(0x00011800380000A0ull);
97 #define CVMX_ZIP_CONSTANTS (CVMX_ADD_IO_SEG(0x00011800380000A0ull))
105 return CVMX_ADD_IO_SEG(0x0001180038000098ull);
108 #define CVMX_ZIP_DEBUG0 (CVMX_ADD_IO_SEG(
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H A Dcvmx-uctlx-defs.h61 return CVMX_ADD_IO_SEG(0x000118006F0000A0ull);
64 #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
72 return CVMX_ADD_IO_SEG(0x000118006F000000ull);
75 #define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
83 return CVMX_ADD_IO_SEG(0x000118006F000080ull);
86 #define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
94 return CVMX_ADD_IO_SEG(0x000118006F0000A8ull);
97 #define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
105 return CVMX_ADD_IO_SEG(0x000118006F000090ull);
108 #define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-agl-defs.h61 return CVMX_ADD_IO_SEG(0x00011800E0000518ull);
64 #define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
72 return CVMX_ADD_IO_SEG(0x00011800E0000400ull);
75 #define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
83 return CVMX_ADD_IO_SEG(0x00011800E00007F0ull);
86 #define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
94 return CVMX_ADD_IO_SEG(0x00011800E00007F8ull);
97 #define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
107 return CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048;
110 #define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(
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H A Dcvmx-dfa-defs.h61 return CVMX_ADD_IO_SEG(0x00011800370007F0ull);
64 #define CVMX_DFA_BIST0 (CVMX_ADD_IO_SEG(0x00011800370007F0ull))
72 return CVMX_ADD_IO_SEG(0x00011800370007F8ull);
75 #define CVMX_DFA_BIST1 (CVMX_ADD_IO_SEG(0x00011800370007F8ull))
83 return CVMX_ADD_IO_SEG(0x00011800300007F0ull);
86 #define CVMX_DFA_BST0 (CVMX_ADD_IO_SEG(0x00011800300007F0ull))
94 return CVMX_ADD_IO_SEG(0x00011800300007F8ull);
97 #define CVMX_DFA_BST1 (CVMX_ADD_IO_SEG(0x00011800300007F8ull))
105 return CVMX_ADD_IO_SEG(0x0001180030000000ull);
108 #define CVMX_DFA_CFG (CVMX_ADD_IO_SEG(
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H A Dcvmx-l2c-defs.h61 return CVMX_ADD_IO_SEG(0x0001180080800030ull);
64 #define CVMX_L2C_BIG_CTL (CVMX_ADD_IO_SEG(0x0001180080800030ull))
72 return CVMX_ADD_IO_SEG(0x00011800808007F8ull);
75 #define CVMX_L2C_BST (CVMX_ADD_IO_SEG(0x00011800808007F8ull))
83 return CVMX_ADD_IO_SEG(0x00011800800007F8ull);
86 #define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull))
94 return CVMX_ADD_IO_SEG(0x00011800800007F0ull);
97 #define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull))
105 return CVMX_ADD_IO_SEG(0x00011800800007E8ull);
108 #define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(
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H A Dcvmx-pcm-defs.h63 return CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384;
66 #define CVMX_PCM_CLKX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384)
76 return CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384;
79 #define CVMX_PCM_CLKX_DBG(offset) (CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384)
89 return CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384;
92 #define CVMX_PCM_CLKX_GEN(offset) (CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384)
H A Dcvmx-asxx-defs.h63 return CVMX_ADD_IO_SEG(0x00011800B0000180ull);
66 #define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
76 return CVMX_ADD_IO_SEG(0x00011800B0000188ull);
79 #define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
91 return CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull;
94 #define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
106 return CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull;
109 #define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
118 return CVMX_ADD_IO_SEG(0x00011800B0000190ull);
121 #define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-sriox-defs.h61 return CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 1) * 0x1000000ull;
64 #define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 1) * 0x1000000ull)
72 return CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 1) * 0x1000000ull;
75 #define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 1) * 0x1000000ull)
83 return CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 1) * 0x1000000ull;
86 #define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 1) * 0x1000000ull)
94 return CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 1) * 0x1000000ull;
97 #define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 1) * 0x1000000ull)
105 return CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 1) * 0x1000000ull;
108 #define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-dfm-defs.h61 return CVMX_ADD_IO_SEG(0x00011800D4000220ull);
64 #define CVMX_DFM_CHAR_CTL (CVMX_ADD_IO_SEG(0x00011800D4000220ull))
72 return CVMX_ADD_IO_SEG(0x00011800D4000228ull);
75 #define CVMX_DFM_CHAR_MASK0 (CVMX_ADD_IO_SEG(0x00011800D4000228ull))
83 return CVMX_ADD_IO_SEG(0x00011800D4000238ull);
86 #define CVMX_DFM_CHAR_MASK2 (CVMX_ADD_IO_SEG(0x00011800D4000238ull))
94 return CVMX_ADD_IO_SEG(0x00011800D4000318ull);
97 #define CVMX_DFM_CHAR_MASK4 (CVMX_ADD_IO_SEG(0x00011800D4000318ull))
105 return CVMX_ADD_IO_SEG(0x00011800D40001B8ull);
108 #define CVMX_DFM_COMP_CTL2 (CVMX_ADD_IO_SEG(
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H A Dcvmx-key-defs.h61 return CVMX_ADD_IO_SEG(0x0001180020000018ull);
64 #define CVMX_KEY_BIST_REG (CVMX_ADD_IO_SEG(0x0001180020000018ull))
72 return CVMX_ADD_IO_SEG(0x0001180020000010ull);
75 #define CVMX_KEY_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180020000010ull))
83 return CVMX_ADD_IO_SEG(0x0001180020000008ull);
86 #define CVMX_KEY_INT_ENB (CVMX_ADD_IO_SEG(0x0001180020000008ull))
94 return CVMX_ADD_IO_SEG(0x0001180020000000ull);
97 #define CVMX_KEY_INT_SUM (CVMX_ADD_IO_SEG(0x0001180020000000ull))
H A Dcvmx-mpi-defs.h61 return CVMX_ADD_IO_SEG(0x0001070000001000ull);
64 #define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
74 return CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8;
77 #define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
85 return CVMX_ADD_IO_SEG(0x0001070000001008ull);
88 #define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
96 return CVMX_ADD_IO_SEG(0x0001070000001010ull);
99 #define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
H A Dcvmx-rnm-defs.h55 #define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
56 #define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
63 return CVMX_ADD_IO_SEG(0x0001180040000018ull);
66 #define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
74 return CVMX_ADD_IO_SEG(0x0001180040000010ull);
77 #define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull))
85 return CVMX_ADD_IO_SEG(0x0001180040000020ull);
88 #define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull))
H A Dcvmx-spxx-defs.h62 return CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull;
65 #define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
74 return CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull;
77 #define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
86 return CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull;
89 #define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
98 return CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull;
101 #define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
110 return CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull;
113 #define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-mio-defs.h55 #define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
62 return CVMX_ADD_IO_SEG(0x00011800000000B8ull);
65 #define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
75 return CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8;
78 #define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
88 return CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8;
91 #define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
101 return CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8;
104 #define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
114 return CVMX_ADD_IO_SEG(
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