1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-pexp-defs.h 43 * 44 * Configuration and status register (CSR) definitions for 45 * OCTEON PEXP. 46 * 47 * <hr>$Revision$<hr> 48 */ 49#ifndef __CVMX_PEXP_DEFS_H__ 50#define __CVMX_PEXP_DEFS_H__ 51 52#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 53static inline uint64_t CVMX_PEXP_NPEI_BAR1_INDEXX(unsigned long offset) 54{ 55 if (!( 56 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 57 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 58 cvmx_warn("CVMX_PEXP_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset); 59 return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16; 60} 61#else 62#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16) 63#endif 64#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 65#define CVMX_PEXP_NPEI_BIST_STATUS CVMX_PEXP_NPEI_BIST_STATUS_FUNC() 66static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS_FUNC(void) 67{ 68 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 69 cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS not supported on this chip\n"); 70 return CVMX_ADD_IO_SEG(0x00011F0000008580ull); 71} 72#else 73#define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull)) 74#endif 75#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 76#define CVMX_PEXP_NPEI_BIST_STATUS2 CVMX_PEXP_NPEI_BIST_STATUS2_FUNC() 77static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS2_FUNC(void) 78{ 79 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 80 cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS2 not supported on this chip\n"); 81 return CVMX_ADD_IO_SEG(0x00011F0000008680ull); 82} 83#else 84#define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull)) 85#endif 86#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 87#define CVMX_PEXP_NPEI_CTL_PORT0 CVMX_PEXP_NPEI_CTL_PORT0_FUNC() 88static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT0_FUNC(void) 89{ 90 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 91 cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT0 not supported on this chip\n"); 92 return CVMX_ADD_IO_SEG(0x00011F0000008250ull); 93} 94#else 95#define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull)) 96#endif 97#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 98#define CVMX_PEXP_NPEI_CTL_PORT1 CVMX_PEXP_NPEI_CTL_PORT1_FUNC() 99static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT1_FUNC(void) 100{ 101 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 102 cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT1 not supported on this chip\n"); 103 return CVMX_ADD_IO_SEG(0x00011F0000008260ull); 104} 105#else 106#define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull)) 107#endif 108#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 109#define CVMX_PEXP_NPEI_CTL_STATUS CVMX_PEXP_NPEI_CTL_STATUS_FUNC() 110static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS_FUNC(void) 111{ 112 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 113 cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS not supported on this chip\n"); 114 return CVMX_ADD_IO_SEG(0x00011F0000008570ull); 115} 116#else 117#define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull)) 118#endif 119#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 120#define CVMX_PEXP_NPEI_CTL_STATUS2 CVMX_PEXP_NPEI_CTL_STATUS2_FUNC() 121static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS2_FUNC(void) 122{ 123 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 124 cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS2 not supported on this chip\n"); 125 return CVMX_ADD_IO_SEG(0x00011F000000BC00ull); 126} 127#else 128#define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull)) 129#endif 130#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 131#define CVMX_PEXP_NPEI_DATA_OUT_CNT CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC() 132static inline uint64_t CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC(void) 133{ 134 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 135 cvmx_warn("CVMX_PEXP_NPEI_DATA_OUT_CNT not supported on this chip\n"); 136 return CVMX_ADD_IO_SEG(0x00011F00000085F0ull); 137} 138#else 139#define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull)) 140#endif 141#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 142#define CVMX_PEXP_NPEI_DBG_DATA CVMX_PEXP_NPEI_DBG_DATA_FUNC() 143static inline uint64_t CVMX_PEXP_NPEI_DBG_DATA_FUNC(void) 144{ 145 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 146 cvmx_warn("CVMX_PEXP_NPEI_DBG_DATA not supported on this chip\n"); 147 return CVMX_ADD_IO_SEG(0x00011F0000008510ull); 148} 149#else 150#define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull)) 151#endif 152#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 153#define CVMX_PEXP_NPEI_DBG_SELECT CVMX_PEXP_NPEI_DBG_SELECT_FUNC() 154static inline uint64_t CVMX_PEXP_NPEI_DBG_SELECT_FUNC(void) 155{ 156 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 157 cvmx_warn("CVMX_PEXP_NPEI_DBG_SELECT not supported on this chip\n"); 158 return CVMX_ADD_IO_SEG(0x00011F0000008500ull); 159} 160#else 161#define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull)) 162#endif 163#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 164#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC() 165static inline uint64_t CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC(void) 166{ 167 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 168 cvmx_warn("CVMX_PEXP_NPEI_DMA0_INT_LEVEL not supported on this chip\n"); 169 return CVMX_ADD_IO_SEG(0x00011F00000085C0ull); 170} 171#else 172#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull)) 173#endif 174#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 175#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC() 176static inline uint64_t CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC(void) 177{ 178 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 179 cvmx_warn("CVMX_PEXP_NPEI_DMA1_INT_LEVEL not supported on this chip\n"); 180 return CVMX_ADD_IO_SEG(0x00011F00000085D0ull); 181} 182#else 183#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull)) 184#endif 185#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 186static inline uint64_t CVMX_PEXP_NPEI_DMAX_COUNTS(unsigned long offset) 187{ 188 if (!( 189 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 190 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 191 cvmx_warn("CVMX_PEXP_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset); 192 return CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16; 193} 194#else 195#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16) 196#endif 197#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 198static inline uint64_t CVMX_PEXP_NPEI_DMAX_DBELL(unsigned long offset) 199{ 200 if (!( 201 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 202 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 203 cvmx_warn("CVMX_PEXP_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset); 204 return CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16; 205} 206#else 207#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210static inline uint64_t CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(unsigned long offset) 211{ 212 if (!( 213 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 214 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 215 cvmx_warn("CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset); 216 return CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16; 217} 218#else 219#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16) 220#endif 221#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 222static inline uint64_t CVMX_PEXP_NPEI_DMAX_NADDR(unsigned long offset) 223{ 224 if (!( 225 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 226 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 227 cvmx_warn("CVMX_PEXP_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset); 228 return CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16; 229} 230#else 231#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16) 232#endif 233#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 234#define CVMX_PEXP_NPEI_DMA_CNTS CVMX_PEXP_NPEI_DMA_CNTS_FUNC() 235static inline uint64_t CVMX_PEXP_NPEI_DMA_CNTS_FUNC(void) 236{ 237 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 238 cvmx_warn("CVMX_PEXP_NPEI_DMA_CNTS not supported on this chip\n"); 239 return CVMX_ADD_IO_SEG(0x00011F00000085E0ull); 240} 241#else 242#define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull)) 243#endif 244#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 245#define CVMX_PEXP_NPEI_DMA_CONTROL CVMX_PEXP_NPEI_DMA_CONTROL_FUNC() 246static inline uint64_t CVMX_PEXP_NPEI_DMA_CONTROL_FUNC(void) 247{ 248 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 249 cvmx_warn("CVMX_PEXP_NPEI_DMA_CONTROL not supported on this chip\n"); 250 return CVMX_ADD_IO_SEG(0x00011F00000083A0ull); 251} 252#else 253#define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull)) 254#endif 255#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 256#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC() 257static inline uint64_t CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC(void) 258{ 259 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 260 cvmx_warn("CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n"); 261 return CVMX_ADD_IO_SEG(0x00011F00000085B0ull); 262} 263#else 264#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull)) 265#endif 266#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 267#define CVMX_PEXP_NPEI_DMA_STATE1 CVMX_PEXP_NPEI_DMA_STATE1_FUNC() 268static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE1_FUNC(void) 269{ 270 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 271 cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE1 not supported on this chip\n"); 272 return CVMX_ADD_IO_SEG(0x00011F00000086C0ull); 273} 274#else 275#define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull)) 276#endif 277#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull)) 278#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 279#define CVMX_PEXP_NPEI_DMA_STATE2 CVMX_PEXP_NPEI_DMA_STATE2_FUNC() 280static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE2_FUNC(void) 281{ 282 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 283 cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE2 not supported on this chip\n"); 284 return CVMX_ADD_IO_SEG(0x00011F00000086D0ull); 285} 286#else 287#define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull)) 288#endif 289#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull)) 290#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull)) 291#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull)) 292#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull)) 293#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 294#define CVMX_PEXP_NPEI_INT_A_ENB CVMX_PEXP_NPEI_INT_A_ENB_FUNC() 295static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB_FUNC(void) 296{ 297 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 298 cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB not supported on this chip\n"); 299 return CVMX_ADD_IO_SEG(0x00011F0000008560ull); 300} 301#else 302#define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull)) 303#endif 304#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 305#define CVMX_PEXP_NPEI_INT_A_ENB2 CVMX_PEXP_NPEI_INT_A_ENB2_FUNC() 306static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB2_FUNC(void) 307{ 308 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 309 cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB2 not supported on this chip\n"); 310 return CVMX_ADD_IO_SEG(0x00011F000000BCE0ull); 311} 312#else 313#define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull)) 314#endif 315#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 316#define CVMX_PEXP_NPEI_INT_A_SUM CVMX_PEXP_NPEI_INT_A_SUM_FUNC() 317static inline uint64_t CVMX_PEXP_NPEI_INT_A_SUM_FUNC(void) 318{ 319 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 320 cvmx_warn("CVMX_PEXP_NPEI_INT_A_SUM not supported on this chip\n"); 321 return CVMX_ADD_IO_SEG(0x00011F0000008550ull); 322} 323#else 324#define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull)) 325#endif 326#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 327#define CVMX_PEXP_NPEI_INT_ENB CVMX_PEXP_NPEI_INT_ENB_FUNC() 328static inline uint64_t CVMX_PEXP_NPEI_INT_ENB_FUNC(void) 329{ 330 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 331 cvmx_warn("CVMX_PEXP_NPEI_INT_ENB not supported on this chip\n"); 332 return CVMX_ADD_IO_SEG(0x00011F0000008540ull); 333} 334#else 335#define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull)) 336#endif 337#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 338#define CVMX_PEXP_NPEI_INT_ENB2 CVMX_PEXP_NPEI_INT_ENB2_FUNC() 339static inline uint64_t CVMX_PEXP_NPEI_INT_ENB2_FUNC(void) 340{ 341 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 342 cvmx_warn("CVMX_PEXP_NPEI_INT_ENB2 not supported on this chip\n"); 343 return CVMX_ADD_IO_SEG(0x00011F000000BCD0ull); 344} 345#else 346#define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull)) 347#endif 348#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 349#define CVMX_PEXP_NPEI_INT_INFO CVMX_PEXP_NPEI_INT_INFO_FUNC() 350static inline uint64_t CVMX_PEXP_NPEI_INT_INFO_FUNC(void) 351{ 352 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 353 cvmx_warn("CVMX_PEXP_NPEI_INT_INFO not supported on this chip\n"); 354 return CVMX_ADD_IO_SEG(0x00011F0000008590ull); 355} 356#else 357#define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull)) 358#endif 359#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 360#define CVMX_PEXP_NPEI_INT_SUM CVMX_PEXP_NPEI_INT_SUM_FUNC() 361static inline uint64_t CVMX_PEXP_NPEI_INT_SUM_FUNC(void) 362{ 363 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 364 cvmx_warn("CVMX_PEXP_NPEI_INT_SUM not supported on this chip\n"); 365 return CVMX_ADD_IO_SEG(0x00011F0000008530ull); 366} 367#else 368#define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull)) 369#endif 370#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 371#define CVMX_PEXP_NPEI_INT_SUM2 CVMX_PEXP_NPEI_INT_SUM2_FUNC() 372static inline uint64_t CVMX_PEXP_NPEI_INT_SUM2_FUNC(void) 373{ 374 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 375 cvmx_warn("CVMX_PEXP_NPEI_INT_SUM2 not supported on this chip\n"); 376 return CVMX_ADD_IO_SEG(0x00011F000000BCC0ull); 377} 378#else 379#define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull)) 380#endif 381#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 382#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC() 383static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC(void) 384{ 385 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 386 cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA0 not supported on this chip\n"); 387 return CVMX_ADD_IO_SEG(0x00011F0000008600ull); 388} 389#else 390#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull)) 391#endif 392#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 393#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC() 394static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC(void) 395{ 396 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 397 cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA1 not supported on this chip\n"); 398 return CVMX_ADD_IO_SEG(0x00011F0000008610ull); 399} 400#else 401#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull)) 402#endif 403#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 404#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC() 405static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC(void) 406{ 407 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 408 cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_CTL not supported on this chip\n"); 409 return CVMX_ADD_IO_SEG(0x00011F00000084F0ull); 410} 411#else 412#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull)) 413#endif 414#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 415static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset) 416{ 417 if (!( 418 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27)))) || 419 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27)))))) 420 cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset); 421 return CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12; 422} 423#else 424#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12) 425#endif 426#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 427#define CVMX_PEXP_NPEI_MSI_ENB0 CVMX_PEXP_NPEI_MSI_ENB0_FUNC() 428static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB0_FUNC(void) 429{ 430 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 431 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB0 not supported on this chip\n"); 432 return CVMX_ADD_IO_SEG(0x00011F000000BC50ull); 433} 434#else 435#define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull)) 436#endif 437#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 438#define CVMX_PEXP_NPEI_MSI_ENB1 CVMX_PEXP_NPEI_MSI_ENB1_FUNC() 439static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB1_FUNC(void) 440{ 441 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 442 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB1 not supported on this chip\n"); 443 return CVMX_ADD_IO_SEG(0x00011F000000BC60ull); 444} 445#else 446#define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull)) 447#endif 448#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 449#define CVMX_PEXP_NPEI_MSI_ENB2 CVMX_PEXP_NPEI_MSI_ENB2_FUNC() 450static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB2_FUNC(void) 451{ 452 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 453 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB2 not supported on this chip\n"); 454 return CVMX_ADD_IO_SEG(0x00011F000000BC70ull); 455} 456#else 457#define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull)) 458#endif 459#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 460#define CVMX_PEXP_NPEI_MSI_ENB3 CVMX_PEXP_NPEI_MSI_ENB3_FUNC() 461static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB3_FUNC(void) 462{ 463 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 464 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB3 not supported on this chip\n"); 465 return CVMX_ADD_IO_SEG(0x00011F000000BC80ull); 466} 467#else 468#define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull)) 469#endif 470#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 471#define CVMX_PEXP_NPEI_MSI_RCV0 CVMX_PEXP_NPEI_MSI_RCV0_FUNC() 472static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV0_FUNC(void) 473{ 474 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 475 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV0 not supported on this chip\n"); 476 return CVMX_ADD_IO_SEG(0x00011F000000BC10ull); 477} 478#else 479#define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull)) 480#endif 481#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 482#define CVMX_PEXP_NPEI_MSI_RCV1 CVMX_PEXP_NPEI_MSI_RCV1_FUNC() 483static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV1_FUNC(void) 484{ 485 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 486 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV1 not supported on this chip\n"); 487 return CVMX_ADD_IO_SEG(0x00011F000000BC20ull); 488} 489#else 490#define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull)) 491#endif 492#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 493#define CVMX_PEXP_NPEI_MSI_RCV2 CVMX_PEXP_NPEI_MSI_RCV2_FUNC() 494static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV2_FUNC(void) 495{ 496 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 497 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV2 not supported on this chip\n"); 498 return CVMX_ADD_IO_SEG(0x00011F000000BC30ull); 499} 500#else 501#define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull)) 502#endif 503#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 504#define CVMX_PEXP_NPEI_MSI_RCV3 CVMX_PEXP_NPEI_MSI_RCV3_FUNC() 505static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV3_FUNC(void) 506{ 507 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 508 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV3 not supported on this chip\n"); 509 return CVMX_ADD_IO_SEG(0x00011F000000BC40ull); 510} 511#else 512#define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull)) 513#endif 514#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 515#define CVMX_PEXP_NPEI_MSI_RD_MAP CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC() 516static inline uint64_t CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC(void) 517{ 518 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 519 cvmx_warn("CVMX_PEXP_NPEI_MSI_RD_MAP not supported on this chip\n"); 520 return CVMX_ADD_IO_SEG(0x00011F000000BCA0ull); 521} 522#else 523#define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull)) 524#endif 525#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 526#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC() 527static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC(void) 528{ 529 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 530 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB0 not supported on this chip\n"); 531 return CVMX_ADD_IO_SEG(0x00011F000000BCF0ull); 532} 533#else 534#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull)) 535#endif 536#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 537#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC() 538static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC(void) 539{ 540 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 541 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB1 not supported on this chip\n"); 542 return CVMX_ADD_IO_SEG(0x00011F000000BD00ull); 543} 544#else 545#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull)) 546#endif 547#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 548#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC() 549static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC(void) 550{ 551 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 552 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB2 not supported on this chip\n"); 553 return CVMX_ADD_IO_SEG(0x00011F000000BD10ull); 554} 555#else 556#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull)) 557#endif 558#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 559#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC() 560static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC(void) 561{ 562 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 563 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB3 not supported on this chip\n"); 564 return CVMX_ADD_IO_SEG(0x00011F000000BD20ull); 565} 566#else 567#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull)) 568#endif 569#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 570#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC() 571static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC(void) 572{ 573 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 574 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB0 not supported on this chip\n"); 575 return CVMX_ADD_IO_SEG(0x00011F000000BD30ull); 576} 577#else 578#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull)) 579#endif 580#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 581#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC() 582static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC(void) 583{ 584 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 585 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB1 not supported on this chip\n"); 586 return CVMX_ADD_IO_SEG(0x00011F000000BD40ull); 587} 588#else 589#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull)) 590#endif 591#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 592#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC() 593static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC(void) 594{ 595 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 596 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB2 not supported on this chip\n"); 597 return CVMX_ADD_IO_SEG(0x00011F000000BD50ull); 598} 599#else 600#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull)) 601#endif 602#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 603#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC() 604static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC(void) 605{ 606 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 607 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB3 not supported on this chip\n"); 608 return CVMX_ADD_IO_SEG(0x00011F000000BD60ull); 609} 610#else 611#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull)) 612#endif 613#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 614#define CVMX_PEXP_NPEI_MSI_WR_MAP CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC() 615static inline uint64_t CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC(void) 616{ 617 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 618 cvmx_warn("CVMX_PEXP_NPEI_MSI_WR_MAP not supported on this chip\n"); 619 return CVMX_ADD_IO_SEG(0x00011F000000BC90ull); 620} 621#else 622#define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull)) 623#endif 624#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 625#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC() 626static inline uint64_t CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC(void) 627{ 628 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 629 cvmx_warn("CVMX_PEXP_NPEI_PCIE_CREDIT_CNT not supported on this chip\n"); 630 return CVMX_ADD_IO_SEG(0x00011F000000BD70ull); 631} 632#else 633#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull)) 634#endif 635#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 636#define CVMX_PEXP_NPEI_PCIE_MSI_RCV CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC() 637static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC(void) 638{ 639 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 640 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV not supported on this chip\n"); 641 return CVMX_ADD_IO_SEG(0x00011F000000BCB0ull); 642} 643#else 644#define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull)) 645#endif 646#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 647#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC() 648static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC(void) 649{ 650 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 651 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n"); 652 return CVMX_ADD_IO_SEG(0x00011F0000008650ull); 653} 654#else 655#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull)) 656#endif 657#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 658#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC() 659static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC(void) 660{ 661 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 662 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n"); 663 return CVMX_ADD_IO_SEG(0x00011F0000008660ull); 664} 665#else 666#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull)) 667#endif 668#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 669#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC() 670static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC(void) 671{ 672 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 673 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n"); 674 return CVMX_ADD_IO_SEG(0x00011F0000008670ull); 675} 676#else 677#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull)) 678#endif 679#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 680static inline uint64_t CVMX_PEXP_NPEI_PKTX_CNTS(unsigned long offset) 681{ 682 if (!( 683 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 684 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 685 cvmx_warn("CVMX_PEXP_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset); 686 return CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16; 687} 688#else 689#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16) 690#endif 691#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 692static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(unsigned long offset) 693{ 694 if (!( 695 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 696 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 697 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset); 698 return CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16; 699} 700#else 701#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16) 702#endif 703#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 704static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset) 705{ 706 if (!( 707 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 708 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 709 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 710 return CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16; 711} 712#else 713#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16) 714#endif 715#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset) 717{ 718 if (!( 719 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 720 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 721 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 722 return CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16; 723} 724#else 725#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16) 726#endif 727#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 728static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(unsigned long offset) 729{ 730 if (!( 731 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 732 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 733 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset); 734 return CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16; 735} 736#else 737#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16) 738#endif 739#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 740static inline uint64_t CVMX_PEXP_NPEI_PKTX_IN_BP(unsigned long offset) 741{ 742 if (!( 743 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 744 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 745 cvmx_warn("CVMX_PEXP_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset); 746 return CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16; 747} 748#else 749#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16) 750#endif 751#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 752static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(unsigned long offset) 753{ 754 if (!( 755 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 756 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 757 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset); 758 return CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16; 759} 760#else 761#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16) 762#endif 763#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 764static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset) 765{ 766 if (!( 767 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 768 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 769 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 770 return CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16; 771} 772#else 773#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16) 774#endif 775#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 776static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset) 777{ 778 if (!( 779 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 780 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 781 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 782 return CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16; 783} 784#else 785#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16) 786#endif 787#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 788#define CVMX_PEXP_NPEI_PKT_CNT_INT CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC() 789static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC(void) 790{ 791 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 792 cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT not supported on this chip\n"); 793 return CVMX_ADD_IO_SEG(0x00011F0000009110ull); 794} 795#else 796#define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull)) 797#endif 798#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 799#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC() 800static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC(void) 801{ 802 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 803 cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT_ENB not supported on this chip\n"); 804 return CVMX_ADD_IO_SEG(0x00011F0000009130ull); 805} 806#else 807#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull)) 808#endif 809#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 810#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC() 811static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC(void) 812{ 813 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 814 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ES not supported on this chip\n"); 815 return CVMX_ADD_IO_SEG(0x00011F00000090B0ull); 816} 817#else 818#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull)) 819#endif 820#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 821#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC() 822static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC(void) 823{ 824 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 825 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_NS not supported on this chip\n"); 826 return CVMX_ADD_IO_SEG(0x00011F00000090A0ull); 827} 828#else 829#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull)) 830#endif 831#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 832#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC() 833static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC(void) 834{ 835 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 836 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n"); 837 return CVMX_ADD_IO_SEG(0x00011F0000009090ull); 838} 839#else 840#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull)) 841#endif 842#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 843#define CVMX_PEXP_NPEI_PKT_DPADDR CVMX_PEXP_NPEI_PKT_DPADDR_FUNC() 844static inline uint64_t CVMX_PEXP_NPEI_PKT_DPADDR_FUNC(void) 845{ 846 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 847 cvmx_warn("CVMX_PEXP_NPEI_PKT_DPADDR not supported on this chip\n"); 848 return CVMX_ADD_IO_SEG(0x00011F0000009080ull); 849} 850#else 851#define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull)) 852#endif 853#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 854#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC() 855static inline uint64_t CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC(void) 856{ 857 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 858 cvmx_warn("CVMX_PEXP_NPEI_PKT_INPUT_CONTROL not supported on this chip\n"); 859 return CVMX_ADD_IO_SEG(0x00011F0000009150ull); 860} 861#else 862#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull)) 863#endif 864#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 865#define CVMX_PEXP_NPEI_PKT_INSTR_ENB CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC() 866static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC(void) 867{ 868 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 869 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_ENB not supported on this chip\n"); 870 return CVMX_ADD_IO_SEG(0x00011F0000009000ull); 871} 872#else 873#define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull)) 874#endif 875#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 876#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC() 877static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC(void) 878{ 879 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 880 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n"); 881 return CVMX_ADD_IO_SEG(0x00011F0000009190ull); 882} 883#else 884#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull)) 885#endif 886#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 887#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC() 888static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC(void) 889{ 890 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 891 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_SIZE not supported on this chip\n"); 892 return CVMX_ADD_IO_SEG(0x00011F0000009020ull); 893} 894#else 895#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull)) 896#endif 897#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 898#define CVMX_PEXP_NPEI_PKT_INT_LEVELS CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC() 899static inline uint64_t CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC(void) 900{ 901 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 902 cvmx_warn("CVMX_PEXP_NPEI_PKT_INT_LEVELS not supported on this chip\n"); 903 return CVMX_ADD_IO_SEG(0x00011F0000009100ull); 904} 905#else 906#define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull)) 907#endif 908#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 909#define CVMX_PEXP_NPEI_PKT_IN_BP CVMX_PEXP_NPEI_PKT_IN_BP_FUNC() 910static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_BP_FUNC(void) 911{ 912 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 913 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_BP not supported on this chip\n"); 914 return CVMX_ADD_IO_SEG(0x00011F00000086B0ull); 915} 916#else 917#define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull)) 918#endif 919#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 920static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset) 921{ 922 if (!( 923 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 924 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 925 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset); 926 return CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16; 927} 928#else 929#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16) 930#endif 931#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 932#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC() 933static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void) 934{ 935 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 936 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n"); 937 return CVMX_ADD_IO_SEG(0x00011F00000086A0ull); 938} 939#else 940#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull)) 941#endif 942#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 943#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC() 944static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC(void) 945{ 946 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 947 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n"); 948 return CVMX_ADD_IO_SEG(0x00011F00000091A0ull); 949} 950#else 951#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull)) 952#endif 953#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 954#define CVMX_PEXP_NPEI_PKT_IPTR CVMX_PEXP_NPEI_PKT_IPTR_FUNC() 955static inline uint64_t CVMX_PEXP_NPEI_PKT_IPTR_FUNC(void) 956{ 957 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 958 cvmx_warn("CVMX_PEXP_NPEI_PKT_IPTR not supported on this chip\n"); 959 return CVMX_ADD_IO_SEG(0x00011F0000009070ull); 960} 961#else 962#define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull)) 963#endif 964#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 965#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC() 966static inline uint64_t CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC(void) 967{ 968 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 969 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n"); 970 return CVMX_ADD_IO_SEG(0x00011F0000009160ull); 971} 972#else 973#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull)) 974#endif 975#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 976#define CVMX_PEXP_NPEI_PKT_OUT_BMODE CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC() 977static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC(void) 978{ 979 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 980 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_BMODE not supported on this chip\n"); 981 return CVMX_ADD_IO_SEG(0x00011F00000090D0ull); 982} 983#else 984#define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull)) 985#endif 986#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 987#define CVMX_PEXP_NPEI_PKT_OUT_ENB CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC() 988static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC(void) 989{ 990 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 991 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_ENB not supported on this chip\n"); 992 return CVMX_ADD_IO_SEG(0x00011F0000009010ull); 993} 994#else 995#define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull)) 996#endif 997#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 998#define CVMX_PEXP_NPEI_PKT_PCIE_PORT CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC() 999static inline uint64_t CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC(void) 1000{ 1001 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1002 cvmx_warn("CVMX_PEXP_NPEI_PKT_PCIE_PORT not supported on this chip\n"); 1003 return CVMX_ADD_IO_SEG(0x00011F00000090E0ull); 1004} 1005#else 1006#define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull)) 1007#endif 1008#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1009#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC() 1010static inline uint64_t CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC(void) 1011{ 1012 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1013 cvmx_warn("CVMX_PEXP_NPEI_PKT_PORT_IN_RST not supported on this chip\n"); 1014 return CVMX_ADD_IO_SEG(0x00011F0000008690ull); 1015} 1016#else 1017#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull)) 1018#endif 1019#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1020#define CVMX_PEXP_NPEI_PKT_SLIST_ES CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC() 1021static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC(void) 1022{ 1023 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1024 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ES not supported on this chip\n"); 1025 return CVMX_ADD_IO_SEG(0x00011F0000009050ull); 1026} 1027#else 1028#define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull)) 1029#endif 1030#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1031#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC() 1032static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC(void) 1033{ 1034 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1035 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n"); 1036 return CVMX_ADD_IO_SEG(0x00011F0000009180ull); 1037} 1038#else 1039#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull)) 1040#endif 1041#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1042#define CVMX_PEXP_NPEI_PKT_SLIST_NS CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC() 1043static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC(void) 1044{ 1045 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1046 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_NS not supported on this chip\n"); 1047 return CVMX_ADD_IO_SEG(0x00011F0000009040ull); 1048} 1049#else 1050#define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull)) 1051#endif 1052#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1053#define CVMX_PEXP_NPEI_PKT_SLIST_ROR CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC() 1054static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC(void) 1055{ 1056 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1057 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ROR not supported on this chip\n"); 1058 return CVMX_ADD_IO_SEG(0x00011F0000009030ull); 1059} 1060#else 1061#define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull)) 1062#endif 1063#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1064#define CVMX_PEXP_NPEI_PKT_TIME_INT CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC() 1065static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC(void) 1066{ 1067 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1068 cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT not supported on this chip\n"); 1069 return CVMX_ADD_IO_SEG(0x00011F0000009120ull); 1070} 1071#else 1072#define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull)) 1073#endif 1074#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1075#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC() 1076static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC(void) 1077{ 1078 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1079 cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT_ENB not supported on this chip\n"); 1080 return CVMX_ADD_IO_SEG(0x00011F0000009140ull); 1081} 1082#else 1083#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull)) 1084#endif 1085#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1086#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC() 1087static inline uint64_t CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC(void) 1088{ 1089 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1090 cvmx_warn("CVMX_PEXP_NPEI_RSL_INT_BLOCKS not supported on this chip\n"); 1091 return CVMX_ADD_IO_SEG(0x00011F0000008520ull); 1092} 1093#else 1094#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull)) 1095#endif 1096#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1097#define CVMX_PEXP_NPEI_SCRATCH_1 CVMX_PEXP_NPEI_SCRATCH_1_FUNC() 1098static inline uint64_t CVMX_PEXP_NPEI_SCRATCH_1_FUNC(void) 1099{ 1100 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1101 cvmx_warn("CVMX_PEXP_NPEI_SCRATCH_1 not supported on this chip\n"); 1102 return CVMX_ADD_IO_SEG(0x00011F0000008270ull); 1103} 1104#else 1105#define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull)) 1106#endif 1107#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1108#define CVMX_PEXP_NPEI_STATE1 CVMX_PEXP_NPEI_STATE1_FUNC() 1109static inline uint64_t CVMX_PEXP_NPEI_STATE1_FUNC(void) 1110{ 1111 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1112 cvmx_warn("CVMX_PEXP_NPEI_STATE1 not supported on this chip\n"); 1113 return CVMX_ADD_IO_SEG(0x00011F0000008620ull); 1114} 1115#else 1116#define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull)) 1117#endif 1118#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1119#define CVMX_PEXP_NPEI_STATE2 CVMX_PEXP_NPEI_STATE2_FUNC() 1120static inline uint64_t CVMX_PEXP_NPEI_STATE2_FUNC(void) 1121{ 1122 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1123 cvmx_warn("CVMX_PEXP_NPEI_STATE2 not supported on this chip\n"); 1124 return CVMX_ADD_IO_SEG(0x00011F0000008630ull); 1125} 1126#else 1127#define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull)) 1128#endif 1129#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1130#define CVMX_PEXP_NPEI_STATE3 CVMX_PEXP_NPEI_STATE3_FUNC() 1131static inline uint64_t CVMX_PEXP_NPEI_STATE3_FUNC(void) 1132{ 1133 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1134 cvmx_warn("CVMX_PEXP_NPEI_STATE3 not supported on this chip\n"); 1135 return CVMX_ADD_IO_SEG(0x00011F0000008640ull); 1136} 1137#else 1138#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull)) 1139#endif 1140#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1141#define CVMX_PEXP_NPEI_WINDOW_CTL CVMX_PEXP_NPEI_WINDOW_CTL_FUNC() 1142static inline uint64_t CVMX_PEXP_NPEI_WINDOW_CTL_FUNC(void) 1143{ 1144 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1145 cvmx_warn("CVMX_PEXP_NPEI_WINDOW_CTL not supported on this chip\n"); 1146 return CVMX_ADD_IO_SEG(0x00011F0000008380ull); 1147} 1148#else 1149#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull)) 1150#endif 1151#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1152#define CVMX_PEXP_SLI_BIST_STATUS CVMX_PEXP_SLI_BIST_STATUS_FUNC() 1153static inline uint64_t CVMX_PEXP_SLI_BIST_STATUS_FUNC(void) 1154{ 1155 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1156 cvmx_warn("CVMX_PEXP_SLI_BIST_STATUS not supported on this chip\n"); 1157 return CVMX_ADD_IO_SEG(0x00011F0000010580ull); 1158} 1159#else 1160#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull)) 1161#endif 1162#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1163static inline uint64_t CVMX_PEXP_SLI_CTL_PORTX(unsigned long offset) 1164{ 1165 if (!( 1166 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 1167 cvmx_warn("CVMX_PEXP_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset); 1168 return CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16; 1169} 1170#else 1171#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16) 1172#endif 1173#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1174#define CVMX_PEXP_SLI_CTL_STATUS CVMX_PEXP_SLI_CTL_STATUS_FUNC() 1175static inline uint64_t CVMX_PEXP_SLI_CTL_STATUS_FUNC(void) 1176{ 1177 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1178 cvmx_warn("CVMX_PEXP_SLI_CTL_STATUS not supported on this chip\n"); 1179 return CVMX_ADD_IO_SEG(0x00011F0000010570ull); 1180} 1181#else 1182#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull)) 1183#endif 1184#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1185#define CVMX_PEXP_SLI_DATA_OUT_CNT CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC() 1186static inline uint64_t CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC(void) 1187{ 1188 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1189 cvmx_warn("CVMX_PEXP_SLI_DATA_OUT_CNT not supported on this chip\n"); 1190 return CVMX_ADD_IO_SEG(0x00011F00000105F0ull); 1191} 1192#else 1193#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull)) 1194#endif 1195#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1196#define CVMX_PEXP_SLI_DBG_DATA CVMX_PEXP_SLI_DBG_DATA_FUNC() 1197static inline uint64_t CVMX_PEXP_SLI_DBG_DATA_FUNC(void) 1198{ 1199 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1200 cvmx_warn("CVMX_PEXP_SLI_DBG_DATA not supported on this chip\n"); 1201 return CVMX_ADD_IO_SEG(0x00011F0000010310ull); 1202} 1203#else 1204#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull)) 1205#endif 1206#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1207#define CVMX_PEXP_SLI_DBG_SELECT CVMX_PEXP_SLI_DBG_SELECT_FUNC() 1208static inline uint64_t CVMX_PEXP_SLI_DBG_SELECT_FUNC(void) 1209{ 1210 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1211 cvmx_warn("CVMX_PEXP_SLI_DBG_SELECT not supported on this chip\n"); 1212 return CVMX_ADD_IO_SEG(0x00011F0000010300ull); 1213} 1214#else 1215#define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull)) 1216#endif 1217#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1218static inline uint64_t CVMX_PEXP_SLI_DMAX_CNT(unsigned long offset) 1219{ 1220 if (!( 1221 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 1222 cvmx_warn("CVMX_PEXP_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset); 1223 return CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16; 1224} 1225#else 1226#define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16) 1227#endif 1228#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1229static inline uint64_t CVMX_PEXP_SLI_DMAX_INT_LEVEL(unsigned long offset) 1230{ 1231 if (!( 1232 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 1233 cvmx_warn("CVMX_PEXP_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset); 1234 return CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16; 1235} 1236#else 1237#define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16) 1238#endif 1239#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1240static inline uint64_t CVMX_PEXP_SLI_DMAX_TIM(unsigned long offset) 1241{ 1242 if (!( 1243 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 1244 cvmx_warn("CVMX_PEXP_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset); 1245 return CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16; 1246} 1247#else 1248#define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16) 1249#endif 1250#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1251#define CVMX_PEXP_SLI_INT_ENB_CIU CVMX_PEXP_SLI_INT_ENB_CIU_FUNC() 1252static inline uint64_t CVMX_PEXP_SLI_INT_ENB_CIU_FUNC(void) 1253{ 1254 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1255 cvmx_warn("CVMX_PEXP_SLI_INT_ENB_CIU not supported on this chip\n"); 1256 return CVMX_ADD_IO_SEG(0x00011F0000013CD0ull); 1257} 1258#else 1259#define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull)) 1260#endif 1261#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1262static inline uint64_t CVMX_PEXP_SLI_INT_ENB_PORTX(unsigned long offset) 1263{ 1264 if (!( 1265 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 1266 cvmx_warn("CVMX_PEXP_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset); 1267 return CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16; 1268} 1269#else 1270#define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16) 1271#endif 1272#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1273#define CVMX_PEXP_SLI_INT_SUM CVMX_PEXP_SLI_INT_SUM_FUNC() 1274static inline uint64_t CVMX_PEXP_SLI_INT_SUM_FUNC(void) 1275{ 1276 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1277 cvmx_warn("CVMX_PEXP_SLI_INT_SUM not supported on this chip\n"); 1278 return CVMX_ADD_IO_SEG(0x00011F0000010330ull); 1279} 1280#else 1281#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull)) 1282#endif 1283#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1284#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC() 1285static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC(void) 1286{ 1287 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1288 cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA0 not supported on this chip\n"); 1289 return CVMX_ADD_IO_SEG(0x00011F0000010600ull); 1290} 1291#else 1292#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull)) 1293#endif 1294#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1295#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC() 1296static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC(void) 1297{ 1298 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1299 cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA1 not supported on this chip\n"); 1300 return CVMX_ADD_IO_SEG(0x00011F0000010610ull); 1301} 1302#else 1303#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull)) 1304#endif 1305#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1306#define CVMX_PEXP_SLI_MAC_CREDIT_CNT CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC() 1307static inline uint64_t CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC(void) 1308{ 1309 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1310 cvmx_warn("CVMX_PEXP_SLI_MAC_CREDIT_CNT not supported on this chip\n"); 1311 return CVMX_ADD_IO_SEG(0x00011F0000013D70ull); 1312} 1313#else 1314#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull)) 1315#endif 1316#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1317#define CVMX_PEXP_SLI_MEM_ACCESS_CTL CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC() 1318static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC(void) 1319{ 1320 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1321 cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_CTL not supported on this chip\n"); 1322 return CVMX_ADD_IO_SEG(0x00011F00000102F0ull); 1323} 1324#else 1325#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull)) 1326#endif 1327#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1328static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(unsigned long offset) 1329{ 1330 if (!( 1331 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27)))))) 1332 cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset); 1333 return CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12; 1334} 1335#else 1336#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12) 1337#endif 1338#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1339#define CVMX_PEXP_SLI_MSI_ENB0 CVMX_PEXP_SLI_MSI_ENB0_FUNC() 1340static inline uint64_t CVMX_PEXP_SLI_MSI_ENB0_FUNC(void) 1341{ 1342 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1343 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB0 not supported on this chip\n"); 1344 return CVMX_ADD_IO_SEG(0x00011F0000013C50ull); 1345} 1346#else 1347#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull)) 1348#endif 1349#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1350#define CVMX_PEXP_SLI_MSI_ENB1 CVMX_PEXP_SLI_MSI_ENB1_FUNC() 1351static inline uint64_t CVMX_PEXP_SLI_MSI_ENB1_FUNC(void) 1352{ 1353 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1354 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB1 not supported on this chip\n"); 1355 return CVMX_ADD_IO_SEG(0x00011F0000013C60ull); 1356} 1357#else 1358#define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull)) 1359#endif 1360#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1361#define CVMX_PEXP_SLI_MSI_ENB2 CVMX_PEXP_SLI_MSI_ENB2_FUNC() 1362static inline uint64_t CVMX_PEXP_SLI_MSI_ENB2_FUNC(void) 1363{ 1364 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1365 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB2 not supported on this chip\n"); 1366 return CVMX_ADD_IO_SEG(0x00011F0000013C70ull); 1367} 1368#else 1369#define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull)) 1370#endif 1371#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1372#define CVMX_PEXP_SLI_MSI_ENB3 CVMX_PEXP_SLI_MSI_ENB3_FUNC() 1373static inline uint64_t CVMX_PEXP_SLI_MSI_ENB3_FUNC(void) 1374{ 1375 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1376 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB3 not supported on this chip\n"); 1377 return CVMX_ADD_IO_SEG(0x00011F0000013C80ull); 1378} 1379#else 1380#define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull)) 1381#endif 1382#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1383#define CVMX_PEXP_SLI_MSI_RCV0 CVMX_PEXP_SLI_MSI_RCV0_FUNC() 1384static inline uint64_t CVMX_PEXP_SLI_MSI_RCV0_FUNC(void) 1385{ 1386 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1387 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV0 not supported on this chip\n"); 1388 return CVMX_ADD_IO_SEG(0x00011F0000013C10ull); 1389} 1390#else 1391#define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull)) 1392#endif 1393#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1394#define CVMX_PEXP_SLI_MSI_RCV1 CVMX_PEXP_SLI_MSI_RCV1_FUNC() 1395static inline uint64_t CVMX_PEXP_SLI_MSI_RCV1_FUNC(void) 1396{ 1397 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1398 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV1 not supported on this chip\n"); 1399 return CVMX_ADD_IO_SEG(0x00011F0000013C20ull); 1400} 1401#else 1402#define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull)) 1403#endif 1404#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1405#define CVMX_PEXP_SLI_MSI_RCV2 CVMX_PEXP_SLI_MSI_RCV2_FUNC() 1406static inline uint64_t CVMX_PEXP_SLI_MSI_RCV2_FUNC(void) 1407{ 1408 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1409 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV2 not supported on this chip\n"); 1410 return CVMX_ADD_IO_SEG(0x00011F0000013C30ull); 1411} 1412#else 1413#define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull)) 1414#endif 1415#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1416#define CVMX_PEXP_SLI_MSI_RCV3 CVMX_PEXP_SLI_MSI_RCV3_FUNC() 1417static inline uint64_t CVMX_PEXP_SLI_MSI_RCV3_FUNC(void) 1418{ 1419 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1420 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV3 not supported on this chip\n"); 1421 return CVMX_ADD_IO_SEG(0x00011F0000013C40ull); 1422} 1423#else 1424#define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull)) 1425#endif 1426#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1427#define CVMX_PEXP_SLI_MSI_RD_MAP CVMX_PEXP_SLI_MSI_RD_MAP_FUNC() 1428static inline uint64_t CVMX_PEXP_SLI_MSI_RD_MAP_FUNC(void) 1429{ 1430 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1431 cvmx_warn("CVMX_PEXP_SLI_MSI_RD_MAP not supported on this chip\n"); 1432 return CVMX_ADD_IO_SEG(0x00011F0000013CA0ull); 1433} 1434#else 1435#define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull)) 1436#endif 1437#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1438#define CVMX_PEXP_SLI_MSI_W1C_ENB0 CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC() 1439static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC(void) 1440{ 1441 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1442 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB0 not supported on this chip\n"); 1443 return CVMX_ADD_IO_SEG(0x00011F0000013CF0ull); 1444} 1445#else 1446#define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull)) 1447#endif 1448#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1449#define CVMX_PEXP_SLI_MSI_W1C_ENB1 CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC() 1450static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC(void) 1451{ 1452 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1453 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB1 not supported on this chip\n"); 1454 return CVMX_ADD_IO_SEG(0x00011F0000013D00ull); 1455} 1456#else 1457#define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull)) 1458#endif 1459#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1460#define CVMX_PEXP_SLI_MSI_W1C_ENB2 CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC() 1461static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC(void) 1462{ 1463 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1464 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB2 not supported on this chip\n"); 1465 return CVMX_ADD_IO_SEG(0x00011F0000013D10ull); 1466} 1467#else 1468#define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull)) 1469#endif 1470#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1471#define CVMX_PEXP_SLI_MSI_W1C_ENB3 CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC() 1472static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC(void) 1473{ 1474 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1475 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB3 not supported on this chip\n"); 1476 return CVMX_ADD_IO_SEG(0x00011F0000013D20ull); 1477} 1478#else 1479#define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull)) 1480#endif 1481#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1482#define CVMX_PEXP_SLI_MSI_W1S_ENB0 CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC() 1483static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC(void) 1484{ 1485 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1486 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB0 not supported on this chip\n"); 1487 return CVMX_ADD_IO_SEG(0x00011F0000013D30ull); 1488} 1489#else 1490#define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull)) 1491#endif 1492#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1493#define CVMX_PEXP_SLI_MSI_W1S_ENB1 CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC() 1494static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC(void) 1495{ 1496 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1497 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB1 not supported on this chip\n"); 1498 return CVMX_ADD_IO_SEG(0x00011F0000013D40ull); 1499} 1500#else 1501#define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull)) 1502#endif 1503#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1504#define CVMX_PEXP_SLI_MSI_W1S_ENB2 CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC() 1505static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC(void) 1506{ 1507 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1508 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB2 not supported on this chip\n"); 1509 return CVMX_ADD_IO_SEG(0x00011F0000013D50ull); 1510} 1511#else 1512#define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull)) 1513#endif 1514#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1515#define CVMX_PEXP_SLI_MSI_W1S_ENB3 CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC() 1516static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC(void) 1517{ 1518 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1519 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB3 not supported on this chip\n"); 1520 return CVMX_ADD_IO_SEG(0x00011F0000013D60ull); 1521} 1522#else 1523#define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull)) 1524#endif 1525#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1526#define CVMX_PEXP_SLI_MSI_WR_MAP CVMX_PEXP_SLI_MSI_WR_MAP_FUNC() 1527static inline uint64_t CVMX_PEXP_SLI_MSI_WR_MAP_FUNC(void) 1528{ 1529 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1530 cvmx_warn("CVMX_PEXP_SLI_MSI_WR_MAP not supported on this chip\n"); 1531 return CVMX_ADD_IO_SEG(0x00011F0000013C90ull); 1532} 1533#else 1534#define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull)) 1535#endif 1536#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1537#define CVMX_PEXP_SLI_PCIE_MSI_RCV CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC() 1538static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC(void) 1539{ 1540 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1541 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV not supported on this chip\n"); 1542 return CVMX_ADD_IO_SEG(0x00011F0000013CB0ull); 1543} 1544#else 1545#define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull)) 1546#endif 1547#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1548#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC() 1549static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC(void) 1550{ 1551 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1552 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n"); 1553 return CVMX_ADD_IO_SEG(0x00011F0000010650ull); 1554} 1555#else 1556#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull)) 1557#endif 1558#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1559#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC() 1560static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC(void) 1561{ 1562 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1563 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n"); 1564 return CVMX_ADD_IO_SEG(0x00011F0000010660ull); 1565} 1566#else 1567#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull)) 1568#endif 1569#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1570#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC() 1571static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC(void) 1572{ 1573 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1574 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n"); 1575 return CVMX_ADD_IO_SEG(0x00011F0000010670ull); 1576} 1577#else 1578#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull)) 1579#endif 1580#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1581static inline uint64_t CVMX_PEXP_SLI_PKTX_CNTS(unsigned long offset) 1582{ 1583 if (!( 1584 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 1585 cvmx_warn("CVMX_PEXP_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset); 1586 return CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16; 1587} 1588#else 1589#define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16) 1590#endif 1591#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1592static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BADDR(unsigned long offset) 1593{ 1594 if (!( 1595 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 1596 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset); 1597 return CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16; 1598} 1599#else 1600#define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16) 1601#endif 1602#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1603static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset) 1604{ 1605 if (!( 1606 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 1607 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 1608 return CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16; 1609} 1610#else 1611#define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16) 1612#endif 1613#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1614static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset) 1615{ 1616 if (!( 1617 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 1618 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 1619 return CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16; 1620} 1621#else 1622#define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16) 1623#endif 1624#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1625static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_HEADER(unsigned long offset) 1626{ 1627 if (!( 1628 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 1629 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset); 1630 return CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16; 1631} 1632#else 1633#define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16) 1634#endif 1635#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1636static inline uint64_t CVMX_PEXP_SLI_PKTX_IN_BP(unsigned long offset) 1637{ 1638 if (!( 1639 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 1640 cvmx_warn("CVMX_PEXP_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset); 1641 return CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16; 1642} 1643#else 1644#define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16) 1645#endif 1646#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1647static inline uint64_t CVMX_PEXP_SLI_PKTX_OUT_SIZE(unsigned long offset) 1648{ 1649 if (!( 1650 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 1651 cvmx_warn("CVMX_PEXP_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset); 1652 return CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16; 1653} 1654#else 1655#define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16) 1656#endif 1657#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1658static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BADDR(unsigned long offset) 1659{ 1660 if (!( 1661 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 1662 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset); 1663 return CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16; 1664} 1665#else 1666#define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16) 1667#endif 1668#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1669static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset) 1670{ 1671 if (!( 1672 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 1673 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 1674 return CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16; 1675} 1676#else 1677#define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16) 1678#endif 1679#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1680static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset) 1681{ 1682 if (!( 1683 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 1684 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 1685 return CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16; 1686} 1687#else 1688#define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16) 1689#endif 1690#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1691#define CVMX_PEXP_SLI_PKT_CNT_INT CVMX_PEXP_SLI_PKT_CNT_INT_FUNC() 1692static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_FUNC(void) 1693{ 1694 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1695 cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT not supported on this chip\n"); 1696 return CVMX_ADD_IO_SEG(0x00011F0000011130ull); 1697} 1698#else 1699#define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull)) 1700#endif 1701#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1702#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC() 1703static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC(void) 1704{ 1705 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1706 cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT_ENB not supported on this chip\n"); 1707 return CVMX_ADD_IO_SEG(0x00011F0000011150ull); 1708} 1709#else 1710#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull)) 1711#endif 1712#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1713#define CVMX_PEXP_SLI_PKT_CTL CVMX_PEXP_SLI_PKT_CTL_FUNC() 1714static inline uint64_t CVMX_PEXP_SLI_PKT_CTL_FUNC(void) 1715{ 1716 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1717 cvmx_warn("CVMX_PEXP_SLI_PKT_CTL not supported on this chip\n"); 1718 return CVMX_ADD_IO_SEG(0x00011F0000011220ull); 1719} 1720#else 1721#define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull)) 1722#endif 1723#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1724#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC() 1725static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC(void) 1726{ 1727 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1728 cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ES not supported on this chip\n"); 1729 return CVMX_ADD_IO_SEG(0x00011F00000110B0ull); 1730} 1731#else 1732#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull)) 1733#endif 1734#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1735#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC() 1736static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC(void) 1737{ 1738 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1739 cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_NS not supported on this chip\n"); 1740 return CVMX_ADD_IO_SEG(0x00011F00000110A0ull); 1741} 1742#else 1743#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull)) 1744#endif 1745#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1746#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC() 1747static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC(void) 1748{ 1749 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1750 cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ROR not supported on this chip\n"); 1751 return CVMX_ADD_IO_SEG(0x00011F0000011090ull); 1752} 1753#else 1754#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull)) 1755#endif 1756#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1757#define CVMX_PEXP_SLI_PKT_DPADDR CVMX_PEXP_SLI_PKT_DPADDR_FUNC() 1758static inline uint64_t CVMX_PEXP_SLI_PKT_DPADDR_FUNC(void) 1759{ 1760 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1761 cvmx_warn("CVMX_PEXP_SLI_PKT_DPADDR not supported on this chip\n"); 1762 return CVMX_ADD_IO_SEG(0x00011F0000011080ull); 1763} 1764#else 1765#define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull)) 1766#endif 1767#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1768#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC() 1769static inline uint64_t CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC(void) 1770{ 1771 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1772 cvmx_warn("CVMX_PEXP_SLI_PKT_INPUT_CONTROL not supported on this chip\n"); 1773 return CVMX_ADD_IO_SEG(0x00011F0000011170ull); 1774} 1775#else 1776#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull)) 1777#endif 1778#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1779#define CVMX_PEXP_SLI_PKT_INSTR_ENB CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC() 1780static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC(void) 1781{ 1782 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1783 cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_ENB not supported on this chip\n"); 1784 return CVMX_ADD_IO_SEG(0x00011F0000011000ull); 1785} 1786#else 1787#define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull)) 1788#endif 1789#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1790#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC() 1791static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC(void) 1792{ 1793 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1794 cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n"); 1795 return CVMX_ADD_IO_SEG(0x00011F00000111A0ull); 1796} 1797#else 1798#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull)) 1799#endif 1800#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1801#define CVMX_PEXP_SLI_PKT_INSTR_SIZE CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC() 1802static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC(void) 1803{ 1804 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1805 cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_SIZE not supported on this chip\n"); 1806 return CVMX_ADD_IO_SEG(0x00011F0000011020ull); 1807} 1808#else 1809#define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull)) 1810#endif 1811#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1812#define CVMX_PEXP_SLI_PKT_INT_LEVELS CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC() 1813static inline uint64_t CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC(void) 1814{ 1815 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1816 cvmx_warn("CVMX_PEXP_SLI_PKT_INT_LEVELS not supported on this chip\n"); 1817 return CVMX_ADD_IO_SEG(0x00011F0000011120ull); 1818} 1819#else 1820#define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull)) 1821#endif 1822#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1823#define CVMX_PEXP_SLI_PKT_IN_BP CVMX_PEXP_SLI_PKT_IN_BP_FUNC() 1824static inline uint64_t CVMX_PEXP_SLI_PKT_IN_BP_FUNC(void) 1825{ 1826 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1827 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_BP not supported on this chip\n"); 1828 return CVMX_ADD_IO_SEG(0x00011F0000011210ull); 1829} 1830#else 1831#define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull)) 1832#endif 1833#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1834static inline uint64_t CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(unsigned long offset) 1835{ 1836 if (!( 1837 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 1838 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset); 1839 return CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16; 1840} 1841#else 1842#define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16) 1843#endif 1844#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1845#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC() 1846static inline uint64_t CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC(void) 1847{ 1848 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1849 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n"); 1850 return CVMX_ADD_IO_SEG(0x00011F0000011200ull); 1851} 1852#else 1853#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull)) 1854#endif 1855#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1856#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC() 1857static inline uint64_t CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC(void) 1858{ 1859 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1860 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_PCIE_PORT not supported on this chip\n"); 1861 return CVMX_ADD_IO_SEG(0x00011F00000111B0ull); 1862} 1863#else 1864#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull)) 1865#endif 1866#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1867#define CVMX_PEXP_SLI_PKT_IPTR CVMX_PEXP_SLI_PKT_IPTR_FUNC() 1868static inline uint64_t CVMX_PEXP_SLI_PKT_IPTR_FUNC(void) 1869{ 1870 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1871 cvmx_warn("CVMX_PEXP_SLI_PKT_IPTR not supported on this chip\n"); 1872 return CVMX_ADD_IO_SEG(0x00011F0000011070ull); 1873} 1874#else 1875#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull)) 1876#endif 1877#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1878#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC() 1879static inline uint64_t CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC(void) 1880{ 1881 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1882 cvmx_warn("CVMX_PEXP_SLI_PKT_OUTPUT_WMARK not supported on this chip\n"); 1883 return CVMX_ADD_IO_SEG(0x00011F0000011180ull); 1884} 1885#else 1886#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull)) 1887#endif 1888#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1889#define CVMX_PEXP_SLI_PKT_OUT_BMODE CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC() 1890static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC(void) 1891{ 1892 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1893 cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_BMODE not supported on this chip\n"); 1894 return CVMX_ADD_IO_SEG(0x00011F00000110D0ull); 1895} 1896#else 1897#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull)) 1898#endif 1899#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1900#define CVMX_PEXP_SLI_PKT_OUT_ENB CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC() 1901static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC(void) 1902{ 1903 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1904 cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_ENB not supported on this chip\n"); 1905 return CVMX_ADD_IO_SEG(0x00011F0000011010ull); 1906} 1907#else 1908#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull)) 1909#endif 1910#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1911#define CVMX_PEXP_SLI_PKT_PCIE_PORT CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC() 1912static inline uint64_t CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC(void) 1913{ 1914 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1915 cvmx_warn("CVMX_PEXP_SLI_PKT_PCIE_PORT not supported on this chip\n"); 1916 return CVMX_ADD_IO_SEG(0x00011F00000110E0ull); 1917} 1918#else 1919#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull)) 1920#endif 1921#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1922#define CVMX_PEXP_SLI_PKT_PORT_IN_RST CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC() 1923static inline uint64_t CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC(void) 1924{ 1925 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1926 cvmx_warn("CVMX_PEXP_SLI_PKT_PORT_IN_RST not supported on this chip\n"); 1927 return CVMX_ADD_IO_SEG(0x00011F00000111F0ull); 1928} 1929#else 1930#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull)) 1931#endif 1932#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1933#define CVMX_PEXP_SLI_PKT_SLIST_ES CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC() 1934static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC(void) 1935{ 1936 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1937 cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ES not supported on this chip\n"); 1938 return CVMX_ADD_IO_SEG(0x00011F0000011050ull); 1939} 1940#else 1941#define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull)) 1942#endif 1943#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1944#define CVMX_PEXP_SLI_PKT_SLIST_NS CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC() 1945static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC(void) 1946{ 1947 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1948 cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_NS not supported on this chip\n"); 1949 return CVMX_ADD_IO_SEG(0x00011F0000011040ull); 1950} 1951#else 1952#define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull)) 1953#endif 1954#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1955#define CVMX_PEXP_SLI_PKT_SLIST_ROR CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC() 1956static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC(void) 1957{ 1958 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1959 cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ROR not supported on this chip\n"); 1960 return CVMX_ADD_IO_SEG(0x00011F0000011030ull); 1961} 1962#else 1963#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull)) 1964#endif 1965#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1966#define CVMX_PEXP_SLI_PKT_TIME_INT CVMX_PEXP_SLI_PKT_TIME_INT_FUNC() 1967static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_FUNC(void) 1968{ 1969 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1970 cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT not supported on this chip\n"); 1971 return CVMX_ADD_IO_SEG(0x00011F0000011140ull); 1972} 1973#else 1974#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull)) 1975#endif 1976#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1977#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC() 1978static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC(void) 1979{ 1980 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1981 cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT_ENB not supported on this chip\n"); 1982 return CVMX_ADD_IO_SEG(0x00011F0000011160ull); 1983} 1984#else 1985#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull)) 1986#endif 1987#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1988static inline uint64_t CVMX_PEXP_SLI_S2M_PORTX_CTL(unsigned long offset) 1989{ 1990 if (!( 1991 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 1992 cvmx_warn("CVMX_PEXP_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset); 1993 return CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16; 1994} 1995#else 1996#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16) 1997#endif 1998#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1999#define CVMX_PEXP_SLI_SCRATCH_1 CVMX_PEXP_SLI_SCRATCH_1_FUNC() 2000static inline uint64_t CVMX_PEXP_SLI_SCRATCH_1_FUNC(void) 2001{ 2002 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 2003 cvmx_warn("CVMX_PEXP_SLI_SCRATCH_1 not supported on this chip\n"); 2004 return CVMX_ADD_IO_SEG(0x00011F00000103C0ull); 2005} 2006#else 2007#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull)) 2008#endif 2009#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2010#define CVMX_PEXP_SLI_SCRATCH_2 CVMX_PEXP_SLI_SCRATCH_2_FUNC() 2011static inline uint64_t CVMX_PEXP_SLI_SCRATCH_2_FUNC(void) 2012{ 2013 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 2014 cvmx_warn("CVMX_PEXP_SLI_SCRATCH_2 not supported on this chip\n"); 2015 return CVMX_ADD_IO_SEG(0x00011F00000103D0ull); 2016} 2017#else 2018#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull)) 2019#endif 2020#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2021#define CVMX_PEXP_SLI_STATE1 CVMX_PEXP_SLI_STATE1_FUNC() 2022static inline uint64_t CVMX_PEXP_SLI_STATE1_FUNC(void) 2023{ 2024 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 2025 cvmx_warn("CVMX_PEXP_SLI_STATE1 not supported on this chip\n"); 2026 return CVMX_ADD_IO_SEG(0x00011F0000010620ull); 2027} 2028#else 2029#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull)) 2030#endif 2031#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2032#define CVMX_PEXP_SLI_STATE2 CVMX_PEXP_SLI_STATE2_FUNC() 2033static inline uint64_t CVMX_PEXP_SLI_STATE2_FUNC(void) 2034{ 2035 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 2036 cvmx_warn("CVMX_PEXP_SLI_STATE2 not supported on this chip\n"); 2037 return CVMX_ADD_IO_SEG(0x00011F0000010630ull); 2038} 2039#else 2040#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull)) 2041#endif 2042#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2043#define CVMX_PEXP_SLI_STATE3 CVMX_PEXP_SLI_STATE3_FUNC() 2044static inline uint64_t CVMX_PEXP_SLI_STATE3_FUNC(void) 2045{ 2046 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 2047 cvmx_warn("CVMX_PEXP_SLI_STATE3 not supported on this chip\n"); 2048 return CVMX_ADD_IO_SEG(0x00011F0000010640ull); 2049} 2050#else 2051#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull)) 2052#endif 2053#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2054#define CVMX_PEXP_SLI_WINDOW_CTL CVMX_PEXP_SLI_WINDOW_CTL_FUNC() 2055static inline uint64_t CVMX_PEXP_SLI_WINDOW_CTL_FUNC(void) 2056{ 2057 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 2058 cvmx_warn("CVMX_PEXP_SLI_WINDOW_CTL not supported on this chip\n"); 2059 return CVMX_ADD_IO_SEG(0x00011F00000102E0ull); 2060} 2061#else 2062#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull)) 2063#endif 2064 2065#endif 2066