1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-dpi-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon dpi. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_DPI_TYPEDEFS_H__ 53#define __CVMX_DPI_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_DPI_BIST_STATUS CVMX_DPI_BIST_STATUS_FUNC() 57static inline uint64_t CVMX_DPI_BIST_STATUS_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 60 cvmx_warn("CVMX_DPI_BIST_STATUS not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x0001DF0000000000ull); 62} 63#else 64#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_DPI_CTL CVMX_DPI_CTL_FUNC() 68static inline uint64_t CVMX_DPI_CTL_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 71 cvmx_warn("CVMX_DPI_CTL not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x0001DF0000000040ull); 73} 74#else 75#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78static inline uint64_t CVMX_DPI_DMAX_COUNTS(unsigned long offset) 79{ 80 if (!( 81 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 82 cvmx_warn("CVMX_DPI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset); 83 return CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8; 84} 85#else 86#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89static inline uint64_t CVMX_DPI_DMAX_DBELL(unsigned long offset) 90{ 91 if (!( 92 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 93 cvmx_warn("CVMX_DPI_DMAX_DBELL(%lu) is invalid on this chip\n", offset); 94 return CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8; 95} 96#else 97#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100static inline uint64_t CVMX_DPI_DMAX_IBUFF_SADDR(unsigned long offset) 101{ 102 if (!( 103 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 104 cvmx_warn("CVMX_DPI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset); 105 return CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8; 106} 107#else 108#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111static inline uint64_t CVMX_DPI_DMAX_NADDR(unsigned long offset) 112{ 113 if (!( 114 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 115 cvmx_warn("CVMX_DPI_DMAX_NADDR(%lu) is invalid on this chip\n", offset); 116 return CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8; 117} 118#else 119#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122static inline uint64_t CVMX_DPI_DMAX_REQBNK0(unsigned long offset) 123{ 124 if (!( 125 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 126 cvmx_warn("CVMX_DPI_DMAX_REQBNK0(%lu) is invalid on this chip\n", offset); 127 return CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8; 128} 129#else 130#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133static inline uint64_t CVMX_DPI_DMAX_REQBNK1(unsigned long offset) 134{ 135 if (!( 136 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 137 cvmx_warn("CVMX_DPI_DMAX_REQBNK1(%lu) is invalid on this chip\n", offset); 138 return CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8; 139} 140#else 141#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144#define CVMX_DPI_DMA_CONTROL CVMX_DPI_DMA_CONTROL_FUNC() 145static inline uint64_t CVMX_DPI_DMA_CONTROL_FUNC(void) 146{ 147 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 148 cvmx_warn("CVMX_DPI_DMA_CONTROL not supported on this chip\n"); 149 return CVMX_ADD_IO_SEG(0x0001DF0000000048ull); 150} 151#else 152#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull)) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155static inline uint64_t CVMX_DPI_DMA_ENGX_EN(unsigned long offset) 156{ 157 if (!( 158 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 159 cvmx_warn("CVMX_DPI_DMA_ENGX_EN(%lu) is invalid on this chip\n", offset); 160 return CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8; 161} 162#else 163#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166static inline uint64_t CVMX_DPI_ENGX_BUF(unsigned long offset) 167{ 168 if (!( 169 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 170 cvmx_warn("CVMX_DPI_ENGX_BUF(%lu) is invalid on this chip\n", offset); 171 return CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8; 172} 173#else 174#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177#define CVMX_DPI_INFO_REG CVMX_DPI_INFO_REG_FUNC() 178static inline uint64_t CVMX_DPI_INFO_REG_FUNC(void) 179{ 180 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 181 cvmx_warn("CVMX_DPI_INFO_REG not supported on this chip\n"); 182 return CVMX_ADD_IO_SEG(0x0001DF0000000980ull); 183} 184#else 185#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull)) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188#define CVMX_DPI_INT_EN CVMX_DPI_INT_EN_FUNC() 189static inline uint64_t CVMX_DPI_INT_EN_FUNC(void) 190{ 191 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 192 cvmx_warn("CVMX_DPI_INT_EN not supported on this chip\n"); 193 return CVMX_ADD_IO_SEG(0x0001DF0000000010ull); 194} 195#else 196#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull)) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199#define CVMX_DPI_INT_REG CVMX_DPI_INT_REG_FUNC() 200static inline uint64_t CVMX_DPI_INT_REG_FUNC(void) 201{ 202 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 203 cvmx_warn("CVMX_DPI_INT_REG not supported on this chip\n"); 204 return CVMX_ADD_IO_SEG(0x0001DF0000000008ull); 205} 206#else 207#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull)) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210#define CVMX_DPI_PINT_INFO CVMX_DPI_PINT_INFO_FUNC() 211static inline uint64_t CVMX_DPI_PINT_INFO_FUNC(void) 212{ 213 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 214 cvmx_warn("CVMX_DPI_PINT_INFO not supported on this chip\n"); 215 return CVMX_ADD_IO_SEG(0x0001DF0000000830ull); 216} 217#else 218#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull)) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221#define CVMX_DPI_PKT_ERR_RSP CVMX_DPI_PKT_ERR_RSP_FUNC() 222static inline uint64_t CVMX_DPI_PKT_ERR_RSP_FUNC(void) 223{ 224 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 225 cvmx_warn("CVMX_DPI_PKT_ERR_RSP not supported on this chip\n"); 226 return CVMX_ADD_IO_SEG(0x0001DF0000000078ull); 227} 228#else 229#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull)) 230#endif 231#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232#define CVMX_DPI_REQ_ERR_RSP CVMX_DPI_REQ_ERR_RSP_FUNC() 233static inline uint64_t CVMX_DPI_REQ_ERR_RSP_FUNC(void) 234{ 235 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 236 cvmx_warn("CVMX_DPI_REQ_ERR_RSP not supported on this chip\n"); 237 return CVMX_ADD_IO_SEG(0x0001DF0000000058ull); 238} 239#else 240#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull)) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243#define CVMX_DPI_REQ_ERR_RSP_EN CVMX_DPI_REQ_ERR_RSP_EN_FUNC() 244static inline uint64_t CVMX_DPI_REQ_ERR_RSP_EN_FUNC(void) 245{ 246 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 247 cvmx_warn("CVMX_DPI_REQ_ERR_RSP_EN not supported on this chip\n"); 248 return CVMX_ADD_IO_SEG(0x0001DF0000000068ull); 249} 250#else 251#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull)) 252#endif 253#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254#define CVMX_DPI_REQ_ERR_RST CVMX_DPI_REQ_ERR_RST_FUNC() 255static inline uint64_t CVMX_DPI_REQ_ERR_RST_FUNC(void) 256{ 257 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 258 cvmx_warn("CVMX_DPI_REQ_ERR_RST not supported on this chip\n"); 259 return CVMX_ADD_IO_SEG(0x0001DF0000000060ull); 260} 261#else 262#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull)) 263#endif 264#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265#define CVMX_DPI_REQ_ERR_RST_EN CVMX_DPI_REQ_ERR_RST_EN_FUNC() 266static inline uint64_t CVMX_DPI_REQ_ERR_RST_EN_FUNC(void) 267{ 268 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 269 cvmx_warn("CVMX_DPI_REQ_ERR_RST_EN not supported on this chip\n"); 270 return CVMX_ADD_IO_SEG(0x0001DF0000000070ull); 271} 272#else 273#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull)) 274#endif 275#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276#define CVMX_DPI_REQ_GBL_EN CVMX_DPI_REQ_GBL_EN_FUNC() 277static inline uint64_t CVMX_DPI_REQ_GBL_EN_FUNC(void) 278{ 279 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 280 cvmx_warn("CVMX_DPI_REQ_GBL_EN not supported on this chip\n"); 281 return CVMX_ADD_IO_SEG(0x0001DF0000000050ull); 282} 283#else 284#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull)) 285#endif 286#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287static inline uint64_t CVMX_DPI_SLI_PRTX_CFG(unsigned long offset) 288{ 289 if (!( 290 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 291 cvmx_warn("CVMX_DPI_SLI_PRTX_CFG(%lu) is invalid on this chip\n", offset); 292 return CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 1) * 8; 293} 294#else 295#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 1) * 8) 296#endif 297#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset) 299{ 300 if (!( 301 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 302 cvmx_warn("CVMX_DPI_SLI_PRTX_ERR(%lu) is invalid on this chip\n", offset); 303 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8; 304} 305#else 306#define CVMX_DPI_SLI_PRTX_ERR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8) 307#endif 308#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309static inline uint64_t CVMX_DPI_SLI_PRTX_ERR_INFO(unsigned long offset) 310{ 311 if (!( 312 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 313 cvmx_warn("CVMX_DPI_SLI_PRTX_ERR_INFO(%lu) is invalid on this chip\n", offset); 314 return CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 1) * 8; 315} 316#else 317#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 1) * 8) 318#endif 319 320/** 321 * cvmx_dpi_bist_status 322 */ 323union cvmx_dpi_bist_status 324{ 325 uint64_t u64; 326 struct cvmx_dpi_bist_status_s 327 { 328#if __BYTE_ORDER == __BIG_ENDIAN 329 uint64_t reserved_37_63 : 27; 330 uint64_t bist : 37; /**< BIST Results. 331 HW sets a bit in BIST for for memory that fails 332 BIST. */ 333#else 334 uint64_t bist : 37; 335 uint64_t reserved_37_63 : 27; 336#endif 337 } s; 338 struct cvmx_dpi_bist_status_s cn63xx; 339 struct cvmx_dpi_bist_status_s cn63xxp1; 340}; 341typedef union cvmx_dpi_bist_status cvmx_dpi_bist_status_t; 342 343/** 344 * cvmx_dpi_ctl 345 */ 346union cvmx_dpi_ctl 347{ 348 uint64_t u64; 349 struct cvmx_dpi_ctl_s 350 { 351#if __BYTE_ORDER == __BIG_ENDIAN 352 uint64_t reserved_2_63 : 62; 353 uint64_t clk : 1; /**< Status bit that indicates that the clks are running */ 354 uint64_t en : 1; /**< Turns on the DMA and Packet state machines */ 355#else 356 uint64_t en : 1; 357 uint64_t clk : 1; 358 uint64_t reserved_2_63 : 62; 359#endif 360 } s; 361 struct cvmx_dpi_ctl_s cn63xx; 362 struct cvmx_dpi_ctl_s cn63xxp1; 363}; 364typedef union cvmx_dpi_ctl cvmx_dpi_ctl_t; 365 366/** 367 * cvmx_dpi_dma#_counts 368 * 369 * DPI_DMA[0..7]_COUNTS = DMA Instruction Counts 370 * 371 * Values for determing the number of instructions for DMA[0..7] in the DPI. 372 */ 373union cvmx_dpi_dmax_counts 374{ 375 uint64_t u64; 376 struct cvmx_dpi_dmax_counts_s 377 { 378#if __BYTE_ORDER == __BIG_ENDIAN 379 uint64_t reserved_39_63 : 25; 380 uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO locally 381 cached within DPI. */ 382 uint64_t dbell : 32; /**< Number of available words of Instructions to read. */ 383#else 384 uint64_t dbell : 32; 385 uint64_t fcnt : 7; 386 uint64_t reserved_39_63 : 25; 387#endif 388 } s; 389 struct cvmx_dpi_dmax_counts_s cn63xx; 390 struct cvmx_dpi_dmax_counts_s cn63xxp1; 391}; 392typedef union cvmx_dpi_dmax_counts cvmx_dpi_dmax_counts_t; 393 394/** 395 * cvmx_dpi_dma#_dbell 396 * 397 * DPI_DMA_DBELL[0..7] = DMA Door Bell 398 * 399 * The door bell register for DMA[0..7] queue. 400 */ 401union cvmx_dpi_dmax_dbell 402{ 403 uint64_t u64; 404 struct cvmx_dpi_dmax_dbell_s 405 { 406#if __BYTE_ORDER == __BIG_ENDIAN 407 uint64_t reserved_16_63 : 48; 408 uint64_t dbell : 16; /**< The value written to this register is added to the 409 number of 8byte words to be read and processes for 410 the low priority dma queue. */ 411#else 412 uint64_t dbell : 16; 413 uint64_t reserved_16_63 : 48; 414#endif 415 } s; 416 struct cvmx_dpi_dmax_dbell_s cn63xx; 417 struct cvmx_dpi_dmax_dbell_s cn63xxp1; 418}; 419typedef union cvmx_dpi_dmax_dbell cvmx_dpi_dmax_dbell_t; 420 421/** 422 * cvmx_dpi_dma#_ibuff_saddr 423 * 424 * DPI_DMA[0..7]_IBUFF_SADDR = DMA Instruction Buffer Starting Address 425 * 426 * The address to start reading Instructions from for DMA[0..7]. 427 */ 428union cvmx_dpi_dmax_ibuff_saddr 429{ 430 uint64_t u64; 431 struct cvmx_dpi_dmax_ibuff_saddr_s 432 { 433#if __BYTE_ORDER == __BIG_ENDIAN 434 uint64_t reserved_62_63 : 2; 435 uint64_t csize : 14; /**< The size in 8B words of the DMA Instruction Chunk. 436 This value should only be written at known times 437 in order to prevent corruption of the instruction 438 queue. The minimum CSIZE is 16 (one cacheblock). */ 439 uint64_t reserved_41_47 : 7; 440 uint64_t idle : 1; /**< DMA Request Queue is IDLE */ 441 uint64_t reserved_36_39 : 4; 442 uint64_t saddr : 29; /**< The 128 byte aligned starting or chunk address. 443 SADDR is address bit 35:7 of the starting 444 instructions address. When new chunks are fetched 445 by the HW, SADDR will be updated to reflect the 446 address of the current chunk. 447 A write to SADDR resets both the queue's doorbell 448 (DPI_DMAx_COUNTS[DBELL) and its tail pointer 449 (DPI_DMAx_NADDR[ADDR]). */ 450 uint64_t reserved_0_6 : 7; 451#else 452 uint64_t reserved_0_6 : 7; 453 uint64_t saddr : 29; 454 uint64_t reserved_36_39 : 4; 455 uint64_t idle : 1; 456 uint64_t reserved_41_47 : 7; 457 uint64_t csize : 14; 458 uint64_t reserved_62_63 : 2; 459#endif 460 } s; 461 struct cvmx_dpi_dmax_ibuff_saddr_s cn63xx; 462 struct cvmx_dpi_dmax_ibuff_saddr_s cn63xxp1; 463}; 464typedef union cvmx_dpi_dmax_ibuff_saddr cvmx_dpi_dmax_ibuff_saddr_t; 465 466/** 467 * cvmx_dpi_dma#_naddr 468 * 469 * DPI_DMA[0..7]_NADDR = DMA Next Ichunk Address 470 * 471 * Place DPI will read the next Ichunk data from. 472 */ 473union cvmx_dpi_dmax_naddr 474{ 475 uint64_t u64; 476 struct cvmx_dpi_dmax_naddr_s 477 { 478#if __BYTE_ORDER == __BIG_ENDIAN 479 uint64_t reserved_36_63 : 28; 480 uint64_t addr : 36; /**< The next L2C address to read DMA# instructions 481 from. */ 482#else 483 uint64_t addr : 36; 484 uint64_t reserved_36_63 : 28; 485#endif 486 } s; 487 struct cvmx_dpi_dmax_naddr_s cn63xx; 488 struct cvmx_dpi_dmax_naddr_s cn63xxp1; 489}; 490typedef union cvmx_dpi_dmax_naddr cvmx_dpi_dmax_naddr_t; 491 492/** 493 * cvmx_dpi_dma#_reqbnk0 494 * 495 * DPI_DMA[0..7]_REQBNK0 = DMA Request State Bank0 496 * 497 * Current contents of the request state machine - bank0 498 */ 499union cvmx_dpi_dmax_reqbnk0 500{ 501 uint64_t u64; 502 struct cvmx_dpi_dmax_reqbnk0_s 503 { 504#if __BYTE_ORDER == __BIG_ENDIAN 505 uint64_t state : 64; /**< State */ 506#else 507 uint64_t state : 64; 508#endif 509 } s; 510 struct cvmx_dpi_dmax_reqbnk0_s cn63xx; 511 struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1; 512}; 513typedef union cvmx_dpi_dmax_reqbnk0 cvmx_dpi_dmax_reqbnk0_t; 514 515/** 516 * cvmx_dpi_dma#_reqbnk1 517 * 518 * DPI_DMA[0..7]_REQBNK1 = DMA Request State Bank1 519 * 520 * Current contents of the request state machine - bank1 521 */ 522union cvmx_dpi_dmax_reqbnk1 523{ 524 uint64_t u64; 525 struct cvmx_dpi_dmax_reqbnk1_s 526 { 527#if __BYTE_ORDER == __BIG_ENDIAN 528 uint64_t state : 64; /**< State */ 529#else 530 uint64_t state : 64; 531#endif 532 } s; 533 struct cvmx_dpi_dmax_reqbnk1_s cn63xx; 534 struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1; 535}; 536typedef union cvmx_dpi_dmax_reqbnk1 cvmx_dpi_dmax_reqbnk1_t; 537 538/** 539 * cvmx_dpi_dma_control 540 * 541 * DPI_DMA_CONTROL = DMA Control Register 542 * 543 * Controls operation of the DMA IN/OUT. 544 */ 545union cvmx_dpi_dma_control 546{ 547 uint64_t u64; 548 struct cvmx_dpi_dma_control_s 549 { 550#if __BYTE_ORDER == __BIG_ENDIAN 551 uint64_t reserved_61_63 : 3; 552 uint64_t pkt_en1 : 1; /**< Enables the 2nd packet interface. 553 When the packet interface is enabled, engine 4 554 is used for packets and is not available for DMA. 555 The packet interfaces must be enabled in order. 556 When PKT_EN1=1, then PKT_EN=1. 557 When PKT_EN1=1, then DMA_ENB<4>=0. */ 558 uint64_t ffp_dis : 1; /**< Force forward progress disable 559 The DMA engines will compete for shared resources. 560 If the HW detects that particular engines are not 561 able to make requests to an interface, the HW 562 will periodically trade-off throughput for 563 fairness. */ 564 uint64_t commit_mode : 1; /**< DMA Engine Commit Mode 565 566 When COMMIT_MODE=0, DPI considers an instruction 567 complete when the HW internally generates the 568 final write for the current instruction. 569 570 When COMMIT_MODE=1, DPI additionally waits for 571 the final write to reach the interface coherency 572 point to declare the instructions complete. 573 574 Please note: when COMMIT_MODE == 0, DPI may not 575 follow the HRM ordering rules. 576 577 DPI hardware performance may be better with 578 COMMIT_MODE == 0 than with COMMIT_MODE == 1 due 579 to the relaxed ordering rules. 580 581 If the HRM ordering rules are required, set 582 COMMIT_MODE == 1. */ 583 uint64_t pkt_hp : 1; /**< High-Priority Mode for Packet Interface. 584 Engine 5 will be serviced more frequently to 585 deliver more bandwidth to packet interface. 586 When PKT_EN=0, then PKT_HP=0. */ 587 uint64_t pkt_en : 1; /**< Enables the packet interface. 588 When the packet interface is enabled, engine 5 589 is used for packets and is not available for DMA. 590 When PKT_EN=1, then DMA_ENB<5>=0. 591 When PKT_EN=0, then PKT_HP=0. */ 592 uint64_t reserved_54_55 : 2; 593 uint64_t dma_enb : 6; /**< DMA engine enable. Enables the operation of the 594 DMA engine. After being enabled an engine should 595 not be disabled while processing instructions. 596 When PKT_EN=1, then DMA_ENB<5>=0. */ 597 uint64_t reserved_34_47 : 14; 598 uint64_t b0_lend : 1; /**< When set '1' and the DPI is in the mode to write 599 0 to L2C memory when a DMA is done, the address 600 to be written to will be treated as a Little 601 Endian address. */ 602 uint64_t dwb_denb : 1; /**< When set '1', DPI will send a value in the DWB 603 field for a free page operation for the memory 604 that contained the data. */ 605 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are 606 freed this value is used for the DWB field of the 607 operation. */ 608 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 609 be returned to when used. */ 610 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 611 if '0' then the number of bytes in the dma 612 transfer will be added to the count register. */ 613 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 614 uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 615 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 616 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 617 0=DPTR format 1 is used 618 use register values for address and pointer 619 values for ES, NS, RO 620 1=DPTR format 0 is used 621 use pointer values for address and register 622 values for ES, NS, RO */ 623 uint64_t reserved_0_13 : 14; 624#else 625 uint64_t reserved_0_13 : 14; 626 uint64_t o_mode : 1; 627 uint64_t o_es : 2; 628 uint64_t o_ns : 1; 629 uint64_t o_ro : 1; 630 uint64_t o_add1 : 1; 631 uint64_t fpa_que : 3; 632 uint64_t dwb_ichk : 9; 633 uint64_t dwb_denb : 1; 634 uint64_t b0_lend : 1; 635 uint64_t reserved_34_47 : 14; 636 uint64_t dma_enb : 6; 637 uint64_t reserved_54_55 : 2; 638 uint64_t pkt_en : 1; 639 uint64_t pkt_hp : 1; 640 uint64_t commit_mode : 1; 641 uint64_t ffp_dis : 1; 642 uint64_t pkt_en1 : 1; 643 uint64_t reserved_61_63 : 3; 644#endif 645 } s; 646 struct cvmx_dpi_dma_control_s cn63xx; 647 struct cvmx_dpi_dma_control_cn63xxp1 648 { 649#if __BYTE_ORDER == __BIG_ENDIAN 650 uint64_t reserved_59_63 : 5; 651 uint64_t commit_mode : 1; /**< DMA Engine Commit Mode 652 653 When COMMIT_MODE=0, DPI considers an instruction 654 complete when the HW internally generates the 655 final write for the current instruction. 656 657 When COMMIT_MODE=1, DPI additionally waits for 658 the final write to reach the interface coherency 659 point to declare the instructions complete. 660 661 Please note: when COMMIT_MODE == 0, DPI may not 662 follow the HRM ordering rules. 663 664 DPI hardware performance may be better with 665 COMMIT_MODE == 0 than with COMMIT_MODE == 1 due 666 to the relaxed ordering rules. 667 668 If the HRM ordering rules are required, set 669 COMMIT_MODE == 1. */ 670 uint64_t pkt_hp : 1; /**< High-Priority Mode for Packet Interface. 671 Engine 5 will be serviced more frequently to 672 deliver more bandwidth to packet interface. 673 When PKT_EN=0, then PKT_HP=0. */ 674 uint64_t pkt_en : 1; /**< Enables the packet interface. 675 When the packet interface is enabled, engine 5 676 is used for packets and is not available for DMA. 677 When PKT_EN=1, then DMA_ENB<5>=0. 678 When PKT_EN=0, then PKT_HP=0. */ 679 uint64_t reserved_54_55 : 2; 680 uint64_t dma_enb : 6; /**< DMA engine enable. Enables the operation of the 681 DMA engine. After being enabled an engine should 682 not be disabled while processing instructions. 683 When PKT_EN=1, then DMA_ENB<5>=0. */ 684 uint64_t reserved_34_47 : 14; 685 uint64_t b0_lend : 1; /**< When set '1' and the DPI is in the mode to write 686 0 to L2C memory when a DMA is done, the address 687 to be written to will be treated as a Little 688 Endian address. */ 689 uint64_t dwb_denb : 1; /**< When set '1', DPI will send a value in the DWB 690 field for a free page operation for the memory 691 that contained the data. */ 692 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are 693 freed this value is used for the DWB field of the 694 operation. */ 695 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 696 be returned to when used. */ 697 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 698 if '0' then the number of bytes in the dma 699 transfer will be added to the count register. */ 700 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 701 uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 702 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 703 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 704 0=DPTR format 1 is used 705 use register values for address and pointer 706 values for ES, NS, RO 707 1=DPTR format 0 is used 708 use pointer values for address and register 709 values for ES, NS, RO */ 710 uint64_t reserved_0_13 : 14; 711#else 712 uint64_t reserved_0_13 : 14; 713 uint64_t o_mode : 1; 714 uint64_t o_es : 2; 715 uint64_t o_ns : 1; 716 uint64_t o_ro : 1; 717 uint64_t o_add1 : 1; 718 uint64_t fpa_que : 3; 719 uint64_t dwb_ichk : 9; 720 uint64_t dwb_denb : 1; 721 uint64_t b0_lend : 1; 722 uint64_t reserved_34_47 : 14; 723 uint64_t dma_enb : 6; 724 uint64_t reserved_54_55 : 2; 725 uint64_t pkt_en : 1; 726 uint64_t pkt_hp : 1; 727 uint64_t commit_mode : 1; 728 uint64_t reserved_59_63 : 5; 729#endif 730 } cn63xxp1; 731}; 732typedef union cvmx_dpi_dma_control cvmx_dpi_dma_control_t; 733 734/** 735 * cvmx_dpi_dma_eng#_en 736 */ 737union cvmx_dpi_dma_engx_en 738{ 739 uint64_t u64; 740 struct cvmx_dpi_dma_engx_en_s 741 { 742#if __BYTE_ORDER == __BIG_ENDIAN 743 uint64_t reserved_8_63 : 56; 744 uint64_t qen : 8; /**< Controls which logical instruction queues can be 745 serviced by the DMA engine. Setting QEN==0 746 effectively disables the engine. 747 When DPI_DMA_CONTROL[PKT_EN] = 1, then 748 DPI_DMA_ENG5_EN[QEN] must be zero. */ 749#else 750 uint64_t qen : 8; 751 uint64_t reserved_8_63 : 56; 752#endif 753 } s; 754 struct cvmx_dpi_dma_engx_en_s cn63xx; 755 struct cvmx_dpi_dma_engx_en_s cn63xxp1; 756}; 757typedef union cvmx_dpi_dma_engx_en cvmx_dpi_dma_engx_en_t; 758 759/** 760 * cvmx_dpi_eng#_buf 761 * 762 * Notes: 763 * The total amount of storage allocated to the 6 DPI DMA engines (via DPI_ENG*_BUF[BLKS]) must not exceed 8KB. 764 * 765 */ 766union cvmx_dpi_engx_buf 767{ 768 uint64_t u64; 769 struct cvmx_dpi_engx_buf_s 770 { 771#if __BYTE_ORDER == __BIG_ENDIAN 772 uint64_t reserved_8_63 : 56; 773 uint64_t base : 4; /**< The base address in 512B blocks of the engine fifo */ 774 uint64_t blks : 4; /**< The size in 512B blocks of the engine fifo 775 Legal values are 0-8. 776 0 = Engine is disabled 777 1 = 0.5KB buffer 778 2 = 1.0KB buffer 779 3 = 1.5KB buffer 780 4 = 2.0KB buffer 781 5 = 2.5KB buffer 782 6 = 3.0KB buffer 783 7 = 3.5KB buffer 784 8 = 4.0KB buffer */ 785#else 786 uint64_t blks : 4; 787 uint64_t base : 4; 788 uint64_t reserved_8_63 : 56; 789#endif 790 } s; 791 struct cvmx_dpi_engx_buf_s cn63xx; 792 struct cvmx_dpi_engx_buf_s cn63xxp1; 793}; 794typedef union cvmx_dpi_engx_buf cvmx_dpi_engx_buf_t; 795 796/** 797 * cvmx_dpi_info_reg 798 */ 799union cvmx_dpi_info_reg 800{ 801 uint64_t u64; 802 struct cvmx_dpi_info_reg_s 803 { 804#if __BYTE_ORDER == __BIG_ENDIAN 805 uint64_t reserved_8_63 : 56; 806 uint64_t ffp : 4; /**< Force Forward Progress Indicator */ 807 uint64_t reserved_2_3 : 2; 808 uint64_t ncb : 1; /**< NCB Register Access 809 This interrupt will fire in normal operation 810 when SW reads a DPI register through the NCB 811 interface. */ 812 uint64_t rsl : 1; /**< RSL Register Access 813 This interrupt will fire in normal operation 814 when SW reads a DPI register through the RSL 815 interface. */ 816#else 817 uint64_t rsl : 1; 818 uint64_t ncb : 1; 819 uint64_t reserved_2_3 : 2; 820 uint64_t ffp : 4; 821 uint64_t reserved_8_63 : 56; 822#endif 823 } s; 824 struct cvmx_dpi_info_reg_s cn63xx; 825 struct cvmx_dpi_info_reg_cn63xxp1 826 { 827#if __BYTE_ORDER == __BIG_ENDIAN 828 uint64_t reserved_2_63 : 62; 829 uint64_t ncb : 1; /**< NCB Register Access 830 This interrupt will fire in normal operation 831 when SW reads a DPI register through the NCB 832 interface. */ 833 uint64_t rsl : 1; /**< RSL Register Access 834 This interrupt will fire in normal operation 835 when SW reads a DPI register through the RSL 836 interface. */ 837#else 838 uint64_t rsl : 1; 839 uint64_t ncb : 1; 840 uint64_t reserved_2_63 : 62; 841#endif 842 } cn63xxp1; 843}; 844typedef union cvmx_dpi_info_reg cvmx_dpi_info_reg_t; 845 846/** 847 * cvmx_dpi_int_en 848 */ 849union cvmx_dpi_int_en 850{ 851 uint64_t u64; 852 struct cvmx_dpi_int_en_s 853 { 854#if __BYTE_ORDER == __BIG_ENDIAN 855 uint64_t reserved_26_63 : 38; 856 uint64_t sprt1_rst : 1; /**< DMA instruction was dropped because the source or 857 destination port was in reset. 858 this bit is set. */ 859 uint64_t sprt0_rst : 1; /**< DMA instruction was dropped because the source or 860 destination port was in reset. 861 this bit is set. */ 862 uint64_t reserved_23_23 : 1; 863 uint64_t req_badfil : 1; /**< DMA instruction unexpected fill */ 864 uint64_t req_inull : 1; /**< DMA instruction filled with NULL pointer */ 865 uint64_t req_anull : 1; /**< DMA instruction filled with bad instruction */ 866 uint64_t req_undflw : 1; /**< DMA instruction FIFO underflow */ 867 uint64_t req_ovrflw : 1; /**< DMA instruction FIFO overflow */ 868 uint64_t req_badlen : 1; /**< DMA instruction fetch with length */ 869 uint64_t req_badadr : 1; /**< DMA instruction fetch with bad pointer */ 870 uint64_t dmadbo : 8; /**< DMAx doorbell overflow. */ 871 uint64_t reserved_2_7 : 6; 872 uint64_t nfovr : 1; /**< CSR Fifo Overflow */ 873 uint64_t nderr : 1; /**< NCB Decode Error */ 874#else 875 uint64_t nderr : 1; 876 uint64_t nfovr : 1; 877 uint64_t reserved_2_7 : 6; 878 uint64_t dmadbo : 8; 879 uint64_t req_badadr : 1; 880 uint64_t req_badlen : 1; 881 uint64_t req_ovrflw : 1; 882 uint64_t req_undflw : 1; 883 uint64_t req_anull : 1; 884 uint64_t req_inull : 1; 885 uint64_t req_badfil : 1; 886 uint64_t reserved_23_23 : 1; 887 uint64_t sprt0_rst : 1; 888 uint64_t sprt1_rst : 1; 889 uint64_t reserved_26_63 : 38; 890#endif 891 } s; 892 struct cvmx_dpi_int_en_s cn63xx; 893 struct cvmx_dpi_int_en_s cn63xxp1; 894}; 895typedef union cvmx_dpi_int_en cvmx_dpi_int_en_t; 896 897/** 898 * cvmx_dpi_int_reg 899 */ 900union cvmx_dpi_int_reg 901{ 902 uint64_t u64; 903 struct cvmx_dpi_int_reg_s 904 { 905#if __BYTE_ORDER == __BIG_ENDIAN 906 uint64_t reserved_26_63 : 38; 907 uint64_t sprt1_rst : 1; /**< DMA instruction was dropped because the source or 908 destination port was in reset. 909 this bit is set. */ 910 uint64_t sprt0_rst : 1; /**< DMA instruction was dropped because the source or 911 destination port was in reset. 912 this bit is set. */ 913 uint64_t reserved_23_23 : 1; 914 uint64_t req_badfil : 1; /**< DMA instruction unexpected fill 915 Instruction fill when none outstanding. */ 916 uint64_t req_inull : 1; /**< DMA instruction filled with NULL pointer 917 Next pointer was NULL. */ 918 uint64_t req_anull : 1; /**< DMA instruction filled with bad instruction 919 Fetched instruction word was 0. */ 920 uint64_t req_undflw : 1; /**< DMA instruction FIFO underflow 921 DPI tracks outstanding instructions fetches. 922 Interrupt will fire when FIFO underflows. */ 923 uint64_t req_ovrflw : 1; /**< DMA instruction FIFO overflow 924 DPI tracks outstanding instructions fetches. 925 Interrupt will fire when FIFO overflows. */ 926 uint64_t req_badlen : 1; /**< DMA instruction fetch with length 927 Interrupt will fire if DPI forms an instruction 928 fetch with length of zero. */ 929 uint64_t req_badadr : 1; /**< DMA instruction fetch with bad pointer 930 Interrupt will fire if DPI forms an instruction 931 fetch to the NULL pointer. */ 932 uint64_t dmadbo : 8; /**< DMAx doorbell overflow. 933 DPI has a 32-bit counter for each request's queue 934 outstanding doorbell counts. Interrupt will fire 935 if the count overflows. */ 936 uint64_t reserved_2_7 : 6; 937 uint64_t nfovr : 1; /**< CSR Fifo Overflow 938 DPI can store upto 16 CSR request. The FIFO will 939 overflow if that number is exceeded. */ 940 uint64_t nderr : 1; /**< NCB Decode Error 941 DPI received a NCB transaction on the outbound 942 bus to the DPI deviceID, but the command was not 943 recognized. */ 944#else 945 uint64_t nderr : 1; 946 uint64_t nfovr : 1; 947 uint64_t reserved_2_7 : 6; 948 uint64_t dmadbo : 8; 949 uint64_t req_badadr : 1; 950 uint64_t req_badlen : 1; 951 uint64_t req_ovrflw : 1; 952 uint64_t req_undflw : 1; 953 uint64_t req_anull : 1; 954 uint64_t req_inull : 1; 955 uint64_t req_badfil : 1; 956 uint64_t reserved_23_23 : 1; 957 uint64_t sprt0_rst : 1; 958 uint64_t sprt1_rst : 1; 959 uint64_t reserved_26_63 : 38; 960#endif 961 } s; 962 struct cvmx_dpi_int_reg_s cn63xx; 963 struct cvmx_dpi_int_reg_s cn63xxp1; 964}; 965typedef union cvmx_dpi_int_reg cvmx_dpi_int_reg_t; 966 967/** 968 * cvmx_dpi_pint_info 969 * 970 * DPI_PINT_INFO = DPI Packet Interrupt Info 971 * 972 * DPI Packet Interrupt Info. 973 */ 974union cvmx_dpi_pint_info 975{ 976 uint64_t u64; 977 struct cvmx_dpi_pint_info_s 978 { 979#if __BYTE_ORDER == __BIG_ENDIAN 980 uint64_t reserved_14_63 : 50; 981 uint64_t iinfo : 6; /**< Packet Instruction Doorbell count overflow info */ 982 uint64_t reserved_6_7 : 2; 983 uint64_t sinfo : 6; /**< Packet Scatterlist Doorbell count overflow info */ 984#else 985 uint64_t sinfo : 6; 986 uint64_t reserved_6_7 : 2; 987 uint64_t iinfo : 6; 988 uint64_t reserved_14_63 : 50; 989#endif 990 } s; 991 struct cvmx_dpi_pint_info_s cn63xx; 992 struct cvmx_dpi_pint_info_s cn63xxp1; 993}; 994typedef union cvmx_dpi_pint_info cvmx_dpi_pint_info_t; 995 996/** 997 * cvmx_dpi_pkt_err_rsp 998 */ 999union cvmx_dpi_pkt_err_rsp 1000{ 1001 uint64_t u64; 1002 struct cvmx_dpi_pkt_err_rsp_s 1003 { 1004#if __BYTE_ORDER == __BIG_ENDIAN 1005 uint64_t reserved_1_63 : 63; 1006 uint64_t pkterr : 1; /**< Indicates that an ErrorResponse was received from 1007 the I/O subsystem. */ 1008#else 1009 uint64_t pkterr : 1; 1010 uint64_t reserved_1_63 : 63; 1011#endif 1012 } s; 1013 struct cvmx_dpi_pkt_err_rsp_s cn63xx; 1014 struct cvmx_dpi_pkt_err_rsp_s cn63xxp1; 1015}; 1016typedef union cvmx_dpi_pkt_err_rsp cvmx_dpi_pkt_err_rsp_t; 1017 1018/** 1019 * cvmx_dpi_req_err_rsp 1020 */ 1021union cvmx_dpi_req_err_rsp 1022{ 1023 uint64_t u64; 1024 struct cvmx_dpi_req_err_rsp_s 1025 { 1026#if __BYTE_ORDER == __BIG_ENDIAN 1027 uint64_t reserved_8_63 : 56; 1028 uint64_t qerr : 8; /**< Indicates which instruction queue received an 1029 ErrorResponse from the I/O subsystem. 1030 SW must clear the bit before the the cooresponding 1031 instruction queue will continue processing 1032 instructions if DPI_REQ_ERR_RSP_EN[EN] is set. */ 1033#else 1034 uint64_t qerr : 8; 1035 uint64_t reserved_8_63 : 56; 1036#endif 1037 } s; 1038 struct cvmx_dpi_req_err_rsp_s cn63xx; 1039 struct cvmx_dpi_req_err_rsp_s cn63xxp1; 1040}; 1041typedef union cvmx_dpi_req_err_rsp cvmx_dpi_req_err_rsp_t; 1042 1043/** 1044 * cvmx_dpi_req_err_rsp_en 1045 */ 1046union cvmx_dpi_req_err_rsp_en 1047{ 1048 uint64_t u64; 1049 struct cvmx_dpi_req_err_rsp_en_s 1050 { 1051#if __BYTE_ORDER == __BIG_ENDIAN 1052 uint64_t reserved_8_63 : 56; 1053 uint64_t en : 8; /**< Indicates which instruction queues should stop 1054 dispatching instructions when an ErrorResponse 1055 is received from the I/O subsystem. */ 1056#else 1057 uint64_t en : 8; 1058 uint64_t reserved_8_63 : 56; 1059#endif 1060 } s; 1061 struct cvmx_dpi_req_err_rsp_en_s cn63xx; 1062 struct cvmx_dpi_req_err_rsp_en_s cn63xxp1; 1063}; 1064typedef union cvmx_dpi_req_err_rsp_en cvmx_dpi_req_err_rsp_en_t; 1065 1066/** 1067 * cvmx_dpi_req_err_rst 1068 */ 1069union cvmx_dpi_req_err_rst 1070{ 1071 uint64_t u64; 1072 struct cvmx_dpi_req_err_rst_s 1073 { 1074#if __BYTE_ORDER == __BIG_ENDIAN 1075 uint64_t reserved_8_63 : 56; 1076 uint64_t qerr : 8; /**< Indicates which instruction queue dropped an 1077 instruction because the source or destination 1078 was in reset. 1079 SW must clear the bit before the the cooresponding 1080 instruction queue will continue processing 1081 instructions if DPI_REQ_ERR_RST_EN[EN] is set. */ 1082#else 1083 uint64_t qerr : 8; 1084 uint64_t reserved_8_63 : 56; 1085#endif 1086 } s; 1087 struct cvmx_dpi_req_err_rst_s cn63xx; 1088 struct cvmx_dpi_req_err_rst_s cn63xxp1; 1089}; 1090typedef union cvmx_dpi_req_err_rst cvmx_dpi_req_err_rst_t; 1091 1092/** 1093 * cvmx_dpi_req_err_rst_en 1094 */ 1095union cvmx_dpi_req_err_rst_en 1096{ 1097 uint64_t u64; 1098 struct cvmx_dpi_req_err_rst_en_s 1099 { 1100#if __BYTE_ORDER == __BIG_ENDIAN 1101 uint64_t reserved_8_63 : 56; 1102 uint64_t en : 8; /**< Indicates which instruction queues should stop 1103 dispatching instructions when an instruction 1104 is dropped because the source or destination port 1105 is in reset. */ 1106#else 1107 uint64_t en : 8; 1108 uint64_t reserved_8_63 : 56; 1109#endif 1110 } s; 1111 struct cvmx_dpi_req_err_rst_en_s cn63xx; 1112 struct cvmx_dpi_req_err_rst_en_s cn63xxp1; 1113}; 1114typedef union cvmx_dpi_req_err_rst_en cvmx_dpi_req_err_rst_en_t; 1115 1116/** 1117 * cvmx_dpi_req_gbl_en 1118 */ 1119union cvmx_dpi_req_gbl_en 1120{ 1121 uint64_t u64; 1122 struct cvmx_dpi_req_gbl_en_s 1123 { 1124#if __BYTE_ORDER == __BIG_ENDIAN 1125 uint64_t reserved_8_63 : 56; 1126 uint64_t qen : 8; /**< Indicates which instruction queues are enabled and 1127 can dispatch instructions to a requesting engine. */ 1128#else 1129 uint64_t qen : 8; 1130 uint64_t reserved_8_63 : 56; 1131#endif 1132 } s; 1133 struct cvmx_dpi_req_gbl_en_s cn63xx; 1134 struct cvmx_dpi_req_gbl_en_s cn63xxp1; 1135}; 1136typedef union cvmx_dpi_req_gbl_en cvmx_dpi_req_gbl_en_t; 1137 1138/** 1139 * cvmx_dpi_sli_prt#_cfg 1140 * 1141 * DPI_SLI_PRTx_CFG = DPI SLI Port Configuration 1142 * 1143 * Configures the Max Read Request Size, Max Paylod Size, and Max Number of SLI Tags in use 1144 */ 1145union cvmx_dpi_sli_prtx_cfg 1146{ 1147 uint64_t u64; 1148 struct cvmx_dpi_sli_prtx_cfg_s 1149 { 1150#if __BYTE_ORDER == __BIG_ENDIAN 1151 uint64_t reserved_25_63 : 39; 1152 uint64_t halt : 1; /**< When set, HALT indicates that the MAC has detected 1153 a reset condition. No further instructions that 1154 reference the MAC from any instruction Q will be 1155 issued until the MAC comes out of reset and HALT 1156 is cleared in SLI_CTL_PORTx[DIS_PORT]. */ 1157 uint64_t reserved_21_23 : 3; 1158 uint64_t qlm_cfg : 1; /**< Read only copy of the QLM CFG pin 1159 0= MAC is PCIe 1160 1= MAC is SRIO */ 1161 uint64_t reserved_17_19 : 3; 1162 uint64_t rd_mode : 1; /**< Read Mode 1163 0=Exact Read Mode 1164 If the port is a PCIe port, the HW reads on a 1165 4B granularity. In this mode, the HW may break 1166 a given read into 3 operations to satisify 1167 PCIe rules. 1168 If the port is a SRIO port, the HW follows the 1169 SRIO read rules from the SRIO specification and 1170 only issues 32*n, 16, and 8 byte operations 1171 on the SRIO bus. 1172 1=Block Mode 1173 The HW will read more data than requested in 1174 order to minimize the number of operations 1175 necessary to complete the operation. 1176 The memory region must be memory like. */ 1177 uint64_t reserved_14_15 : 2; 1178 uint64_t molr : 6; /**< Max Outstanding Load Requests 1179 Limits the number of oustanding load requests on 1180 the port by restricting the number of tags 1181 used by the SLI to track load responses. This 1182 value can range from 1 to 32. Setting a value of 1183 0 will halt all read traffic to the port. There 1184 are no restrictions on when this value 1185 can be changed. */ 1186 uint64_t mps_lim : 1; /**< MAC memory space write requests cannot cross the 1187 (naturally-aligned) MPS boundary. 1188 When clear, DPI is allowed to issue a MAC memory 1189 space read that crosses the naturally-aligned 1190 boundary of size defined by MPS. (DPI will still 1191 only cross the boundary when it would eliminate a 1192 write by doing so.) 1193 When set, DPI will never issue a MAC memory space 1194 write that crosses the naturally-aligned boundary 1195 of size defined by MPS. */ 1196 uint64_t reserved_5_6 : 2; 1197 uint64_t mps : 1; /**< Max Payload Size 1198 0 = 128B 1199 1 = 256B 1200 For PCIe MACs, this MPS size must not exceed 1201 the size selected by PCIE*_CFG030[MPS]. 1202 For sRIO MACs, all MPS values are allowed. */ 1203 uint64_t mrrs_lim : 1; /**< MAC memory space read requests cannot cross the 1204 (naturally-aligned) MRRS boundary. 1205 When clear, DPI is allowed to issue a MAC memory 1206 space read that crosses the naturally-aligned 1207 boundary of size defined by MRRS. (DPI will still 1208 only cross the boundary when it would eliminate a 1209 read by doing so.) 1210 When set, DPI will never issue a MAC memory space 1211 read that crosses the naturally-aligned boundary 1212 of size defined by MRRS. */ 1213 uint64_t reserved_2_2 : 1; 1214 uint64_t mrrs : 2; /**< Max Read Request Size 1215 0 = 128B 1216 1 = 256B 1217 2 = 512B 1218 3 = 1024B 1219 For PCIe MACs, this MRRS size must not exceed 1220 the size selected by PCIE*_CFG030[MRRS]. 1221 For sRIO MACs, this MRRS size must be <= 256B. */ 1222#else 1223 uint64_t mrrs : 2; 1224 uint64_t reserved_2_2 : 1; 1225 uint64_t mrrs_lim : 1; 1226 uint64_t mps : 1; 1227 uint64_t reserved_5_6 : 2; 1228 uint64_t mps_lim : 1; 1229 uint64_t molr : 6; 1230 uint64_t reserved_14_15 : 2; 1231 uint64_t rd_mode : 1; 1232 uint64_t reserved_17_19 : 3; 1233 uint64_t qlm_cfg : 1; 1234 uint64_t reserved_21_23 : 3; 1235 uint64_t halt : 1; 1236 uint64_t reserved_25_63 : 39; 1237#endif 1238 } s; 1239 struct cvmx_dpi_sli_prtx_cfg_s cn63xx; 1240 struct cvmx_dpi_sli_prtx_cfg_s cn63xxp1; 1241}; 1242typedef union cvmx_dpi_sli_prtx_cfg cvmx_dpi_sli_prtx_cfg_t; 1243 1244/** 1245 * cvmx_dpi_sli_prt#_err 1246 * 1247 * DPI_SLI_PRTx_ERR = DPI SLI Port Error Info 1248 * 1249 * Logs the Address and Request Queue associated with the reported SLI error response 1250 */ 1251union cvmx_dpi_sli_prtx_err 1252{ 1253 uint64_t u64; 1254 struct cvmx_dpi_sli_prtx_err_s 1255 { 1256#if __BYTE_ORDER == __BIG_ENDIAN 1257 uint64_t addr : 61; /**< Address of the failed load request. */ 1258 uint64_t reserved_0_2 : 3; 1259#else 1260 uint64_t reserved_0_2 : 3; 1261 uint64_t addr : 61; 1262#endif 1263 } s; 1264 struct cvmx_dpi_sli_prtx_err_s cn63xx; 1265 struct cvmx_dpi_sli_prtx_err_s cn63xxp1; 1266}; 1267typedef union cvmx_dpi_sli_prtx_err cvmx_dpi_sli_prtx_err_t; 1268 1269/** 1270 * cvmx_dpi_sli_prt#_err_info 1271 * 1272 * DPI_SLI_PRTx_ERR_INFO = DPI SLI Port Error Info 1273 * 1274 * Logs the Address and Request Queue associated with the reported SLI error response 1275 */ 1276union cvmx_dpi_sli_prtx_err_info 1277{ 1278 uint64_t u64; 1279 struct cvmx_dpi_sli_prtx_err_info_s 1280 { 1281#if __BYTE_ORDER == __BIG_ENDIAN 1282 uint64_t reserved_9_63 : 55; 1283 uint64_t lock : 1; /**< DPI_SLI_PRTx_ERR and DPI_SLI_PRTx_ERR_INFO have 1284 captured and locked contents. */ 1285 uint64_t reserved_5_7 : 3; 1286 uint64_t type : 1; /**< Type of transaction that caused the ErrorResponse. 1287 0=DMA Instruction 1288 1=PKT Instruction */ 1289 uint64_t reserved_3_3 : 1; 1290 uint64_t reqq : 3; /**< Request queue that made the failed load request. */ 1291#else 1292 uint64_t reqq : 3; 1293 uint64_t reserved_3_3 : 1; 1294 uint64_t type : 1; 1295 uint64_t reserved_5_7 : 3; 1296 uint64_t lock : 1; 1297 uint64_t reserved_9_63 : 55; 1298#endif 1299 } s; 1300 struct cvmx_dpi_sli_prtx_err_info_s cn63xx; 1301 struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1; 1302}; 1303typedef union cvmx_dpi_sli_prtx_err_info cvmx_dpi_sli_prtx_err_info_t; 1304 1305#endif 1306