1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-uctlx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon uctlx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_UCTLX_TYPEDEFS_H__ 53#define __CVMX_UCTLX_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_UCTLX_BIST_STATUS(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 60 cvmx_warn("CVMX_UCTLX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 61 return CVMX_ADD_IO_SEG(0x000118006F0000A0ull); 62} 63#else 64#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67static inline uint64_t CVMX_UCTLX_CLK_RST_CTL(unsigned long block_id) 68{ 69 if (!( 70 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 71 cvmx_warn("CVMX_UCTLX_CLK_RST_CTL(%lu) is invalid on this chip\n", block_id); 72 return CVMX_ADD_IO_SEG(0x000118006F000000ull); 73} 74#else 75#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78static inline uint64_t CVMX_UCTLX_EHCI_CTL(unsigned long block_id) 79{ 80 if (!( 81 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 82 cvmx_warn("CVMX_UCTLX_EHCI_CTL(%lu) is invalid on this chip\n", block_id); 83 return CVMX_ADD_IO_SEG(0x000118006F000080ull); 84} 85#else 86#define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull)) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89static inline uint64_t CVMX_UCTLX_EHCI_FLA(unsigned long block_id) 90{ 91 if (!( 92 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 93 cvmx_warn("CVMX_UCTLX_EHCI_FLA(%lu) is invalid on this chip\n", block_id); 94 return CVMX_ADD_IO_SEG(0x000118006F0000A8ull); 95} 96#else 97#define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull)) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100static inline uint64_t CVMX_UCTLX_ERTO_CTL(unsigned long block_id) 101{ 102 if (!( 103 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 104 cvmx_warn("CVMX_UCTLX_ERTO_CTL(%lu) is invalid on this chip\n", block_id); 105 return CVMX_ADD_IO_SEG(0x000118006F000090ull); 106} 107#else 108#define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull)) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111static inline uint64_t CVMX_UCTLX_IF_ENA(unsigned long block_id) 112{ 113 if (!( 114 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 115 cvmx_warn("CVMX_UCTLX_IF_ENA(%lu) is invalid on this chip\n", block_id); 116 return CVMX_ADD_IO_SEG(0x000118006F000030ull); 117} 118#else 119#define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull)) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122static inline uint64_t CVMX_UCTLX_INT_ENA(unsigned long block_id) 123{ 124 if (!( 125 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 126 cvmx_warn("CVMX_UCTLX_INT_ENA(%lu) is invalid on this chip\n", block_id); 127 return CVMX_ADD_IO_SEG(0x000118006F000028ull); 128} 129#else 130#define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull)) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133static inline uint64_t CVMX_UCTLX_INT_REG(unsigned long block_id) 134{ 135 if (!( 136 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 137 cvmx_warn("CVMX_UCTLX_INT_REG(%lu) is invalid on this chip\n", block_id); 138 return CVMX_ADD_IO_SEG(0x000118006F000020ull); 139} 140#else 141#define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull)) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144static inline uint64_t CVMX_UCTLX_OHCI_CTL(unsigned long block_id) 145{ 146 if (!( 147 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 148 cvmx_warn("CVMX_UCTLX_OHCI_CTL(%lu) is invalid on this chip\n", block_id); 149 return CVMX_ADD_IO_SEG(0x000118006F000088ull); 150} 151#else 152#define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull)) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155static inline uint64_t CVMX_UCTLX_ORTO_CTL(unsigned long block_id) 156{ 157 if (!( 158 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 159 cvmx_warn("CVMX_UCTLX_ORTO_CTL(%lu) is invalid on this chip\n", block_id); 160 return CVMX_ADD_IO_SEG(0x000118006F000098ull); 161} 162#else 163#define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull)) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166static inline uint64_t CVMX_UCTLX_PPAF_WM(unsigned long block_id) 167{ 168 if (!( 169 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 170 cvmx_warn("CVMX_UCTLX_PPAF_WM(%lu) is invalid on this chip\n", block_id); 171 return CVMX_ADD_IO_SEG(0x000118006F000038ull); 172} 173#else 174#define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull)) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177static inline uint64_t CVMX_UCTLX_UPHY_CTL_STATUS(unsigned long block_id) 178{ 179 if (!( 180 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 181 cvmx_warn("CVMX_UCTLX_UPHY_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 182 return CVMX_ADD_IO_SEG(0x000118006F000008ull); 183} 184#else 185#define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull)) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188static inline uint64_t CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(unsigned long offset, unsigned long block_id) 189{ 190 if (!( 191 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id == 0)))))) 192 cvmx_warn("CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(%lu,%lu) is invalid on this chip\n", offset, block_id); 193 return CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8; 194} 195#else 196#define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8) 197#endif 198 199/** 200 * cvmx_uctl#_bist_status 201 * 202 * UCTL_BIST_STATUS = UCTL Bist Status 203 * 204 * Results from BIST runs of UCTL's memories. 205 */ 206union cvmx_uctlx_bist_status 207{ 208 uint64_t u64; 209 struct cvmx_uctlx_bist_status_s 210 { 211#if __BYTE_ORDER == __BIG_ENDIAN 212 uint64_t reserved_6_63 : 58; 213 uint64_t data_bis : 1; /**< UAHC EHCI Data Ram Bist Status */ 214 uint64_t desc_bis : 1; /**< UAHC EHCI Descriptor Ram Bist Status */ 215 uint64_t erbm_bis : 1; /**< UCTL EHCI Read Buffer Memory Bist Status */ 216 uint64_t orbm_bis : 1; /**< UCTL OHCI Read Buffer Memory Bist Status */ 217 uint64_t wrbm_bis : 1; /**< UCTL Write Buffer Memory Bist Sta */ 218 uint64_t ppaf_bis : 1; /**< PP Access FIFO Memory Bist Status */ 219#else 220 uint64_t ppaf_bis : 1; 221 uint64_t wrbm_bis : 1; 222 uint64_t orbm_bis : 1; 223 uint64_t erbm_bis : 1; 224 uint64_t desc_bis : 1; 225 uint64_t data_bis : 1; 226 uint64_t reserved_6_63 : 58; 227#endif 228 } s; 229 struct cvmx_uctlx_bist_status_s cn63xx; 230 struct cvmx_uctlx_bist_status_s cn63xxp1; 231}; 232typedef union cvmx_uctlx_bist_status cvmx_uctlx_bist_status_t; 233 234/** 235 * cvmx_uctl#_clk_rst_ctl 236 * 237 * CLK_RST_CTL = Clock and Reset Control Reigster 238 * This register controls the frequceny of hclk and resets for hclk and phy clocks. It also controls Simulation modes and Bists. 239 */ 240union cvmx_uctlx_clk_rst_ctl 241{ 242 uint64_t u64; 243 struct cvmx_uctlx_clk_rst_ctl_s 244 { 245#if __BYTE_ORDER == __BIG_ENDIAN 246 uint64_t reserved_25_63 : 39; 247 uint64_t clear_bist : 1; /**< Clear BIST on the HCLK memories */ 248 uint64_t start_bist : 1; /**< Starts BIST on the HCLK memories during 0-to-1 249 transition. */ 250 uint64_t ehci_sm : 1; /**< Only set it during simulation time. When set to 1, 251 this bit sets the PHY in a non-driving mode so the 252 EHCI can detect device connection. 253 Note: it must not be set to 1, during normal 254 operation. */ 255 uint64_t ohci_clkcktrst : 1; /**< Clear clock reset. Active low. OHCI initial reset 256 signal for the DPLL block. This is only needed by 257 simulation. The duration of the reset in simulation 258 must be the same as HRST. 259 Note: it must be set to 1 during normal operation. */ 260 uint64_t ohci_sm : 1; /**< OHCI Simulation Mode. It selects the counter value 261 for simulation or real time for 1 ms. 262 - 0: counter full 1ms; 1: simulation time. */ 263 uint64_t ohci_susp_lgcy : 1; /**< OHCI Clock Control Signal. Note: This bit must be 264 set to 0 if the OHCI 48/12Mhz clocks must be 265 suspended when the EHCI and OHCI controllers are 266 not active. */ 267 uint64_t app_start_clk : 1; /**< OHCI Clock Control Signal. When the OHCI clocks are 268 suspended, the system has to assert this signal to 269 start the clocks (12 and 48 Mhz). */ 270 uint64_t o_clkdiv_rst : 1; /**< OHCI 12Mhz clock divider reset. Active low. When 271 set to 0, divider is held in reset. 272 The reset to the divider is also asserted when core 273 reset is asserted. */ 274 uint64_t h_clkdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV */ 275 uint64_t h_clkdiv_rst : 1; /**< Host clock divider reset. Active low. When set to 0, 276 divider is held in reset. This must be set to 0 277 before change H_DIV0 and H_DIV1. 278 The reset to the divider is also asserted when core 279 reset is asserted. */ 280 uint64_t h_clkdiv_en : 1; /**< Hclk enable. When set to 1, the hclk is gernerated. */ 281 uint64_t o_clkdiv_en : 1; /**< OHCI 48Mhz/12MHz clock enable. When set to 1, the 282 clocks are gernerated. */ 283 uint64_t h_div : 4; /**< The hclk frequency is sclk frequency divided by 284 H_DIV. The maximum frequency of hclk is 200Mhz. 285 The minimum frequency of hclk is no less than the 286 UTMI clock frequency which is 60Mhz. After writing a 287 value to this field, the software should read the 288 field for the value written. The [H_ENABLE] field of 289 this register should not be set until after this 290 field is set and then read. 291 Only the following values are valid: 292 1, 2, 3, 4, 6, 8, 12. 293 All other values are reserved and will be coded as 294 following: 295 0 -> 1 296 5 -> 4 297 7 -> 6 298 9,10,11 -> 8 299 13,14,15 -> 12 */ 300 uint64_t p_refclk_sel : 2; /**< PHY PLL Reference Clock Select. 301 - 00: uses 12Mhz crystal at USB_XO and USB_XI; 302 - 01: uses 12/24/48Mhz 2.5V clock source at USB_XO. 303 USB_XI should be tied to GND. 304 1x: Reserved. */ 305 uint64_t p_refclk_div : 2; /**< PHY Reference Clock Frequency Select. 306 - 00: 12MHz, 01: 24Mhz, 10: 48Mhz, 11: Reserved. 307 Note: This value must be set during POR is active. 308 If a crystal is used as a reference clock,this field 309 must be set to 12 MHz. Values 01 and 10 are reserved 310 when a crystal is used. */ 311 uint64_t reserved_4_4 : 1; 312 uint64_t p_com_on : 1; /**< PHY Common Block Power-Down Control. 313 - 1: The XO, Bias, and PLL blocks are powered down in 314 Suspend mode. 315 - 0: The XO, Bias, and PLL blocks remain powered in 316 suspend mode. 317 Note: This bit must be set to 0 during POR is active 318 in current design. */ 319 uint64_t p_por : 1; /**< Power on reset for PHY. Resets all the PHY's 320 registers and state machines. */ 321 uint64_t p_prst : 1; /**< PHY Clock Reset. The is the value for phy_rst_n, 322 utmi_rst_n[1] and utmi_rst_n[0]. It is synchronized 323 to each clock domain to generate the corresponding 324 reset signal. This should not be set to 1 until the 325 time it takes for six clock cycles (HCLK and 326 PHY CLK, which ever is slower) has passed. */ 327 uint64_t hrst : 1; /**< Host Clock Reset. This is the value for hreset_n. 328 This should not be set to 1 until 12ms after PHY CLK 329 is stable. */ 330#else 331 uint64_t hrst : 1; 332 uint64_t p_prst : 1; 333 uint64_t p_por : 1; 334 uint64_t p_com_on : 1; 335 uint64_t reserved_4_4 : 1; 336 uint64_t p_refclk_div : 2; 337 uint64_t p_refclk_sel : 2; 338 uint64_t h_div : 4; 339 uint64_t o_clkdiv_en : 1; 340 uint64_t h_clkdiv_en : 1; 341 uint64_t h_clkdiv_rst : 1; 342 uint64_t h_clkdiv_byp : 1; 343 uint64_t o_clkdiv_rst : 1; 344 uint64_t app_start_clk : 1; 345 uint64_t ohci_susp_lgcy : 1; 346 uint64_t ohci_sm : 1; 347 uint64_t ohci_clkcktrst : 1; 348 uint64_t ehci_sm : 1; 349 uint64_t start_bist : 1; 350 uint64_t clear_bist : 1; 351 uint64_t reserved_25_63 : 39; 352#endif 353 } s; 354 struct cvmx_uctlx_clk_rst_ctl_s cn63xx; 355 struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1; 356}; 357typedef union cvmx_uctlx_clk_rst_ctl cvmx_uctlx_clk_rst_ctl_t; 358 359/** 360 * cvmx_uctl#_ehci_ctl 361 * 362 * UCTL_EHCI_CTL = UCTL EHCI Control Register 363 * This register controls the general behavior of UCTL EHCI datapath. 364 */ 365union cvmx_uctlx_ehci_ctl 366{ 367 uint64_t u64; 368 struct cvmx_uctlx_ehci_ctl_s 369 { 370#if __BYTE_ORDER == __BIG_ENDIAN 371 uint64_t reserved_20_63 : 44; 372 uint64_t desc_rbm : 1; /**< Descriptor Read Burst Mode on AHB bus 373 - 1: A read burst can be interruprted after 16 AHB 374 clock cycle 375 - 0: A read burst will not be interrupted until it 376 finishes or no more data available */ 377 uint64_t reg_nb : 1; /**< 1: EHCI register access will not be blocked by EHCI 378 buffer/descriptor access on AHB 379 - 0: Buffer/descriptor and register access will be 380 mutually exclusive */ 381 uint64_t l2c_dc : 1; /**< When set to 1, set the commit bit in the descriptor 382 store commands to L2C. */ 383 uint64_t l2c_bc : 1; /**< When set to 1, set the commit bit in the buffer 384 store commands to L2C. */ 385 uint64_t l2c_0pag : 1; /**< When set to 1, sets the zero-page bit in store 386 command to L2C. */ 387 uint64_t l2c_stt : 1; /**< When set to 1, use STT when store to L2C. */ 388 uint64_t l2c_buff_emod : 2; /**< Endian format for buffer from/to the L2C. 389 IN: A-B-C-D-E-F-G-H 390 OUT0: A-B-C-D-E-F-G-H 391 OUT1: H-G-F-E-D-C-B-A 392 OUT2: D-C-B-A-H-G-F-E 393 OUT3: E-F-G-H-A-B-C-D */ 394 uint64_t l2c_desc_emod : 2; /**< Endian format for descriptor from/to the L2C. 395 IN: A-B-C-D-E-F-G-H 396 OUT0: A-B-C-D-E-F-G-H 397 OUT1: H-G-F-E-D-C-B-A 398 OUT2: D-C-B-A-H-G-F-E 399 OUT3: E-F-G-H-A-B-C-D */ 400 uint64_t inv_reg_a2 : 1; /**< UAHC register address bit<2> invert. When set to 1, 401 for a 32-bit NCB I/O register access, the address 402 offset will be flipped between 0x4 and 0x0. */ 403 uint64_t ehci_64b_addr_en : 1; /**< EHCI AHB Master 64-bit Addressing Enable. 404 - 1: enable ehci 64-bit addressing mode; 405 - 0: disable ehci 64-bit addressing mode. 406 When ehci 64-bit addressing mode is disabled, 407 UCTL_EHCI_CTL[L2C_ADDR_MSB] is used as the address 408 bit[39:32]. */ 409 uint64_t l2c_addr_msb : 8; /**< This is the bit [39:32] of an address sent to L2C 410 for ehci whenUCTL_EHCI_CFG[EHCI_64B_ADDR_EN=0]). */ 411#else 412 uint64_t l2c_addr_msb : 8; 413 uint64_t ehci_64b_addr_en : 1; 414 uint64_t inv_reg_a2 : 1; 415 uint64_t l2c_desc_emod : 2; 416 uint64_t l2c_buff_emod : 2; 417 uint64_t l2c_stt : 1; 418 uint64_t l2c_0pag : 1; 419 uint64_t l2c_bc : 1; 420 uint64_t l2c_dc : 1; 421 uint64_t reg_nb : 1; 422 uint64_t desc_rbm : 1; 423 uint64_t reserved_20_63 : 44; 424#endif 425 } s; 426 struct cvmx_uctlx_ehci_ctl_s cn63xx; 427 struct cvmx_uctlx_ehci_ctl_s cn63xxp1; 428}; 429typedef union cvmx_uctlx_ehci_ctl cvmx_uctlx_ehci_ctl_t; 430 431/** 432 * cvmx_uctl#_ehci_fla 433 * 434 * UCTL_EHCI_FLA = UCTL EHCI Frame Length Adjument Register 435 * This register configures the EHCI Frame Length Adjustment. 436 */ 437union cvmx_uctlx_ehci_fla 438{ 439 uint64_t u64; 440 struct cvmx_uctlx_ehci_fla_s 441 { 442#if __BYTE_ORDER == __BIG_ENDIAN 443 uint64_t reserved_6_63 : 58; 444 uint64_t fla : 6; /**< EHCI Frame Length Adjustment. This feature 445 adjusts any offset from the clock source that drives 446 the uSOF counter. The default value is 32(0x20), 447 which gives an SOF cycle time of 60,0000 (each 448 microframe has 60,000 bit times). 449 Note: keep this value to 0x20 (decimal 32) for no 450 offset. */ 451#else 452 uint64_t fla : 6; 453 uint64_t reserved_6_63 : 58; 454#endif 455 } s; 456 struct cvmx_uctlx_ehci_fla_s cn63xx; 457 struct cvmx_uctlx_ehci_fla_s cn63xxp1; 458}; 459typedef union cvmx_uctlx_ehci_fla cvmx_uctlx_ehci_fla_t; 460 461/** 462 * cvmx_uctl#_erto_ctl 463 * 464 * UCTL_ERTO_CTL = UCTL EHCI Readbuffer TimeOut Control Register 465 * This register controls timeout for EHCI Readbuffer. 466 */ 467union cvmx_uctlx_erto_ctl 468{ 469 uint64_t u64; 470 struct cvmx_uctlx_erto_ctl_s 471 { 472#if __BYTE_ORDER == __BIG_ENDIAN 473 uint64_t reserved_32_63 : 32; 474 uint64_t to_val : 27; /**< Read buffer timeout value 475 (value 0 means timeout disabled) */ 476 uint64_t reserved_0_4 : 5; 477#else 478 uint64_t reserved_0_4 : 5; 479 uint64_t to_val : 27; 480 uint64_t reserved_32_63 : 32; 481#endif 482 } s; 483 struct cvmx_uctlx_erto_ctl_s cn63xx; 484 struct cvmx_uctlx_erto_ctl_s cn63xxp1; 485}; 486typedef union cvmx_uctlx_erto_ctl cvmx_uctlx_erto_ctl_t; 487 488/** 489 * cvmx_uctl#_if_ena 490 * 491 * UCTL_IF_ENA = UCTL Interface Enable Register 492 * 493 * Register to enable the uctl interface clock. 494 */ 495union cvmx_uctlx_if_ena 496{ 497 uint64_t u64; 498 struct cvmx_uctlx_if_ena_s 499 { 500#if __BYTE_ORDER == __BIG_ENDIAN 501 uint64_t reserved_1_63 : 63; 502 uint64_t en : 1; /**< Turns on the USB UCTL interface clock */ 503#else 504 uint64_t en : 1; 505 uint64_t reserved_1_63 : 63; 506#endif 507 } s; 508 struct cvmx_uctlx_if_ena_s cn63xx; 509 struct cvmx_uctlx_if_ena_s cn63xxp1; 510}; 511typedef union cvmx_uctlx_if_ena cvmx_uctlx_if_ena_t; 512 513/** 514 * cvmx_uctl#_int_ena 515 * 516 * UCTL_INT_ENA = UCTL Interrupt Enable Register 517 * 518 * Register to enable individual interrupt source in corresponding to UCTL_INT_REG 519 */ 520union cvmx_uctlx_int_ena 521{ 522 uint64_t u64; 523 struct cvmx_uctlx_int_ena_s 524 { 525#if __BYTE_ORDER == __BIG_ENDIAN 526 uint64_t reserved_8_63 : 56; 527 uint64_t ec_ovf_e : 1; /**< Ehci Commit OVerFlow Error */ 528 uint64_t oc_ovf_e : 1; /**< Ohci Commit OVerFlow Error */ 529 uint64_t wb_pop_e : 1; /**< Write Buffer FIFO Poped When Empty */ 530 uint64_t wb_psh_f : 1; /**< Write Buffer FIFO Pushed When Full */ 531 uint64_t cf_psh_f : 1; /**< Command FIFO Pushed When Full */ 532 uint64_t or_psh_f : 1; /**< OHCI Read Buffer FIFO Pushed When Full */ 533 uint64_t er_psh_f : 1; /**< EHCI Read Buffer FIFO Pushed When Full */ 534 uint64_t pp_psh_f : 1; /**< PP Access FIFO Pushed When Full */ 535#else 536 uint64_t pp_psh_f : 1; 537 uint64_t er_psh_f : 1; 538 uint64_t or_psh_f : 1; 539 uint64_t cf_psh_f : 1; 540 uint64_t wb_psh_f : 1; 541 uint64_t wb_pop_e : 1; 542 uint64_t oc_ovf_e : 1; 543 uint64_t ec_ovf_e : 1; 544 uint64_t reserved_8_63 : 56; 545#endif 546 } s; 547 struct cvmx_uctlx_int_ena_s cn63xx; 548 struct cvmx_uctlx_int_ena_s cn63xxp1; 549}; 550typedef union cvmx_uctlx_int_ena cvmx_uctlx_int_ena_t; 551 552/** 553 * cvmx_uctl#_int_reg 554 * 555 * UCTL_INT_REG = UCTL Interrupt Register 556 * 557 * Summary of different bits of RSL interrupt status. 558 */ 559union cvmx_uctlx_int_reg 560{ 561 uint64_t u64; 562 struct cvmx_uctlx_int_reg_s 563 { 564#if __BYTE_ORDER == __BIG_ENDIAN 565 uint64_t reserved_8_63 : 56; 566 uint64_t ec_ovf_e : 1; /**< Ehci Commit OVerFlow Error 567 When the error happenes, the whole NCB system needs 568 to be reset. */ 569 uint64_t oc_ovf_e : 1; /**< Ohci Commit OVerFlow Error 570 When the error happenes, the whole NCB system needs 571 to be reset. */ 572 uint64_t wb_pop_e : 1; /**< Write Buffer FIFO Poped When Empty */ 573 uint64_t wb_psh_f : 1; /**< Write Buffer FIFO Pushed When Full */ 574 uint64_t cf_psh_f : 1; /**< Command FIFO Pushed When Full */ 575 uint64_t or_psh_f : 1; /**< OHCI Read Buffer FIFO Pushed When Full */ 576 uint64_t er_psh_f : 1; /**< EHCI Read Buffer FIFO Pushed When Full */ 577 uint64_t pp_psh_f : 1; /**< PP Access FIFO Pushed When Full */ 578#else 579 uint64_t pp_psh_f : 1; 580 uint64_t er_psh_f : 1; 581 uint64_t or_psh_f : 1; 582 uint64_t cf_psh_f : 1; 583 uint64_t wb_psh_f : 1; 584 uint64_t wb_pop_e : 1; 585 uint64_t oc_ovf_e : 1; 586 uint64_t ec_ovf_e : 1; 587 uint64_t reserved_8_63 : 56; 588#endif 589 } s; 590 struct cvmx_uctlx_int_reg_s cn63xx; 591 struct cvmx_uctlx_int_reg_s cn63xxp1; 592}; 593typedef union cvmx_uctlx_int_reg cvmx_uctlx_int_reg_t; 594 595/** 596 * cvmx_uctl#_ohci_ctl 597 * 598 * RSL registers starting from 0x10 can be accessed only after hclk is active and hreset is deasserted. 599 * 600 * UCTL_OHCI_CTL = UCTL OHCI Control Register 601 * This register controls the general behavior of UCTL OHCI datapath. 602 */ 603union cvmx_uctlx_ohci_ctl 604{ 605 uint64_t u64; 606 struct cvmx_uctlx_ohci_ctl_s 607 { 608#if __BYTE_ORDER == __BIG_ENDIAN 609 uint64_t reserved_19_63 : 45; 610 uint64_t reg_nb : 1; /**< 1: OHCI register access will not be blocked by EHCI 611 buffer/descriptor access on AHB 612 - 0: Buffer/descriptor and register access will be 613 mutually exclusive */ 614 uint64_t l2c_dc : 1; /**< When set to 1, set the commit bit in the descriptor 615 store commands to L2C. */ 616 uint64_t l2c_bc : 1; /**< When set to 1, set the commit bit in the buffer 617 store commands to L2C. */ 618 uint64_t l2c_0pag : 1; /**< When set to 1, sets the zero-page bit in store 619 command to L2C. */ 620 uint64_t l2c_stt : 1; /**< When set to 1, use STT when store to L2C. */ 621 uint64_t l2c_buff_emod : 2; /**< Endian format for buffer from/to the L2C. 622 IN: A-B-C-D-E-F-G-H 623 OUT0: A-B-C-D-E-F-G-H 624 OUT1: H-G-F-E-D-C-B-A 625 OUT2: D-C-B-A-H-G-F-E 626 OUT3: E-F-G-H-A-B-C-D */ 627 uint64_t l2c_desc_emod : 2; /**< Endian format for descriptor from/to the L2C. 628 IN: A-B-C-D-E-F-G-H 629 OUT0: A-B-C-D-E-F-G-H 630 OUT1: H-G-F-E-D-C-B-A 631 OUT2: D-C-B-A-H-G-F-E 632 OUT3: E-F-G-H-A-B-C-D */ 633 uint64_t inv_reg_a2 : 1; /**< UAHC register address bit<2> invert. When set to 1, 634 for a 32-bit NCB I/O register access, the address 635 offset will be flipped between 0x4 and 0x0. */ 636 uint64_t reserved_8_8 : 1; 637 uint64_t l2c_addr_msb : 8; /**< This is the bit [39:32] of an address sent to L2C 638 for ohci. */ 639#else 640 uint64_t l2c_addr_msb : 8; 641 uint64_t reserved_8_8 : 1; 642 uint64_t inv_reg_a2 : 1; 643 uint64_t l2c_desc_emod : 2; 644 uint64_t l2c_buff_emod : 2; 645 uint64_t l2c_stt : 1; 646 uint64_t l2c_0pag : 1; 647 uint64_t l2c_bc : 1; 648 uint64_t l2c_dc : 1; 649 uint64_t reg_nb : 1; 650 uint64_t reserved_19_63 : 45; 651#endif 652 } s; 653 struct cvmx_uctlx_ohci_ctl_s cn63xx; 654 struct cvmx_uctlx_ohci_ctl_s cn63xxp1; 655}; 656typedef union cvmx_uctlx_ohci_ctl cvmx_uctlx_ohci_ctl_t; 657 658/** 659 * cvmx_uctl#_orto_ctl 660 * 661 * UCTL_ORTO_CTL = UCTL OHCI Readbuffer TimeOut Control Register 662 * This register controls timeout for OHCI Readbuffer. 663 */ 664union cvmx_uctlx_orto_ctl 665{ 666 uint64_t u64; 667 struct cvmx_uctlx_orto_ctl_s 668 { 669#if __BYTE_ORDER == __BIG_ENDIAN 670 uint64_t reserved_32_63 : 32; 671 uint64_t to_val : 24; /**< Read buffer timeout value 672 (value 0 means timeout disabled) */ 673 uint64_t reserved_0_7 : 8; 674#else 675 uint64_t reserved_0_7 : 8; 676 uint64_t to_val : 24; 677 uint64_t reserved_32_63 : 32; 678#endif 679 } s; 680 struct cvmx_uctlx_orto_ctl_s cn63xx; 681 struct cvmx_uctlx_orto_ctl_s cn63xxp1; 682}; 683typedef union cvmx_uctlx_orto_ctl cvmx_uctlx_orto_ctl_t; 684 685/** 686 * cvmx_uctl#_ppaf_wm 687 * 688 * UCTL_PPAF_WM = UCTL PP Access FIFO WaterMark Register 689 * 690 * Register to set PP access FIFO full watermark. 691 */ 692union cvmx_uctlx_ppaf_wm 693{ 694 uint64_t u64; 695 struct cvmx_uctlx_ppaf_wm_s 696 { 697#if __BYTE_ORDER == __BIG_ENDIAN 698 uint64_t reserved_5_63 : 59; 699 uint64_t wm : 5; /**< Number of entries when PP Access FIFO will assert 700 full (back pressure) */ 701#else 702 uint64_t wm : 5; 703 uint64_t reserved_5_63 : 59; 704#endif 705 } s; 706 struct cvmx_uctlx_ppaf_wm_s cn63xx; 707 struct cvmx_uctlx_ppaf_wm_s cn63xxp1; 708}; 709typedef union cvmx_uctlx_ppaf_wm cvmx_uctlx_ppaf_wm_t; 710 711/** 712 * cvmx_uctl#_uphy_ctl_status 713 * 714 * UPHY_CTL_STATUS = USB PHY Control and Status Reigster 715 * This register controls the USB PHY test and Bist. 716 */ 717union cvmx_uctlx_uphy_ctl_status 718{ 719 uint64_t u64; 720 struct cvmx_uctlx_uphy_ctl_status_s 721 { 722#if __BYTE_ORDER == __BIG_ENDIAN 723 uint64_t reserved_10_63 : 54; 724 uint64_t bist_done : 1; /**< PHY BIST DONE. Asserted at the end of the PHY BIST 725 sequence. */ 726 uint64_t bist_err : 1; /**< PHY BIST Error. Valid when BIST_ENB is high. 727 Indicates an internal error was detected during the 728 BIST sequence. */ 729 uint64_t hsbist : 1; /**< High-Speed BIST Enable */ 730 uint64_t fsbist : 1; /**< Full-Speed BIST Enable */ 731 uint64_t lsbist : 1; /**< Low-Speed BIST Enable */ 732 uint64_t siddq : 1; /**< Drives the PHY SIDDQ input. Normally should be set 733 to zero. Customers not using USB PHY interface 734 should do the following: 735 Provide 3.3V to USB_VDD33 Tie USB_REXT to 3.3V 736 supply and Set SIDDQ to 1. */ 737 uint64_t vtest_en : 1; /**< Analog Test Pin Enable. 738 1 = The PHY's ANALOG _TEST pin is enabled for the 739 input and output of applicable analog test 740 signals. 741 0 = The ANALOG_TEST pin is disabled. */ 742 uint64_t uphy_bist : 1; /**< When set to 1, it makes sure that during PHY BIST, 743 utmi_txvld == 0. */ 744 uint64_t bist_en : 1; /**< PHY BIST ENABLE */ 745 uint64_t ate_reset : 1; /**< Reset Input from ATE. This is a test signal. When 746 the USB core is powered up (not in suspend mode), an 747 automatic tester can use this to disable PHYCLOCK 748 and FREECLK, then re-enable them with an aligned 749 phase. 750 - 1: PHYCLOCKs and FREECLK outputs are disable. 751 - 0: PHYCLOCKs and FREECLK are available within a 752 specific period after ATERESET is de-asserted. */ 753#else 754 uint64_t ate_reset : 1; 755 uint64_t bist_en : 1; 756 uint64_t uphy_bist : 1; 757 uint64_t vtest_en : 1; 758 uint64_t siddq : 1; 759 uint64_t lsbist : 1; 760 uint64_t fsbist : 1; 761 uint64_t hsbist : 1; 762 uint64_t bist_err : 1; 763 uint64_t bist_done : 1; 764 uint64_t reserved_10_63 : 54; 765#endif 766 } s; 767 struct cvmx_uctlx_uphy_ctl_status_s cn63xx; 768 struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1; 769}; 770typedef union cvmx_uctlx_uphy_ctl_status cvmx_uctlx_uphy_ctl_status_t; 771 772/** 773 * cvmx_uctl#_uphy_port#_ctl_status 774 * 775 * UPHY_PORTX_CTL_STATUS = USB PHY Port X Control and Status Reigsters 776 * This register controls the each port of the USB PHY. 777 */ 778union cvmx_uctlx_uphy_portx_ctl_status 779{ 780 uint64_t u64; 781 struct cvmx_uctlx_uphy_portx_ctl_status_s 782 { 783#if __BYTE_ORDER == __BIG_ENDIAN 784 uint64_t reserved_43_63 : 21; 785 uint64_t tdata_out : 4; /**< PHY test data out. Presents either interlly 786 generated signals or test register contenets, based 787 upon the value of TDATA_SEL */ 788 uint64_t txbiststuffenh : 1; /**< High-Byte Transmit Bit-Stuffing Enable. It must be 789 set to 1'b1 in normal operation. */ 790 uint64_t txbiststuffen : 1; /**< Low-Byte Transmit Bit-Stuffing Enable. It must be 791 set to 1'b1 in normal operation. */ 792 uint64_t dmpulldown : 1; /**< D- Pull-Down Resistor Enable. It must be set to 1'b1 793 in normal operation. */ 794 uint64_t dppulldown : 1; /**< D+ Pull-Down Resistor Enable. It must be set to 1'b1 795 in normal operation. */ 796 uint64_t vbusvldext : 1; /**< In host mode, this input is not used and can be tied 797 to 1'b0. */ 798 uint64_t portreset : 1; /**< Per-port reset */ 799 uint64_t txhsvxtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 800 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 801 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 802 uint64_t txpreemphasistune : 1; /**< HS transmitter pre-emphasis enable. */ 803 uint64_t txfslstune : 4; /**< FS/LS Source Impedance Adjustment */ 804 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 805 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 806 uint64_t loop_en : 1; /**< Port Loop back Test Enable 807 - 1: During data transmission, the receive logic is 808 enabled 809 - 0: During data transmission, the receive logic is 810 disabled */ 811 uint64_t tclk : 1; /**< PHY port test clock, used to load TDATA_IN to the 812 UPHY. */ 813 uint64_t tdata_sel : 1; /**< Test Data out select 814 - 1: Mode-defined test register contents are output 815 - 0: internally generated signals are output */ 816 uint64_t taddr_in : 4; /**< Mode address for test interface. Specifies the 817 register address for writing to or reading from the 818 PHY test interface register. */ 819 uint64_t tdata_in : 8; /**< Internal testing Register input data and select. 820 This is a test bus. Data presents on [3:0] and the 821 corresponding select (enable) presents on bits[7:4]. */ 822#else 823 uint64_t tdata_in : 8; 824 uint64_t taddr_in : 4; 825 uint64_t tdata_sel : 1; 826 uint64_t tclk : 1; 827 uint64_t loop_en : 1; 828 uint64_t compdistune : 3; 829 uint64_t sqrxtune : 3; 830 uint64_t txfslstune : 4; 831 uint64_t txpreemphasistune : 1; 832 uint64_t txrisetune : 1; 833 uint64_t txvreftune : 4; 834 uint64_t txhsvxtune : 2; 835 uint64_t portreset : 1; 836 uint64_t vbusvldext : 1; 837 uint64_t dppulldown : 1; 838 uint64_t dmpulldown : 1; 839 uint64_t txbiststuffen : 1; 840 uint64_t txbiststuffenh : 1; 841 uint64_t tdata_out : 4; 842 uint64_t reserved_43_63 : 21; 843#endif 844 } s; 845 struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx; 846 struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1; 847}; 848typedef union cvmx_uctlx_uphy_portx_ctl_status cvmx_uctlx_uphy_portx_ctl_status_t; 849 850#endif 851