1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-sriox-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon sriox. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_SRIOX_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_SRIOX_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_SRIOX_ACC_CTRL(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 60215976Sjmallett cvmx_warn("CVMX_SRIOX_ACC_CTRL(%lu) is invalid on this chip\n", block_id); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 1) * 0x1000000ull; 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 1) * 0x1000000ull) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallettstatic inline uint64_t CVMX_SRIOX_ASMBLY_ID(unsigned long block_id) 68215976Sjmallett{ 69215976Sjmallett if (!( 70215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 71215976Sjmallett cvmx_warn("CVMX_SRIOX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 1) * 0x1000000ull; 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 1) * 0x1000000ull) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallettstatic inline uint64_t CVMX_SRIOX_ASMBLY_INFO(unsigned long block_id) 79215976Sjmallett{ 80215976Sjmallett if (!( 81215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 82215976Sjmallett cvmx_warn("CVMX_SRIOX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 1) * 0x1000000ull; 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 1) * 0x1000000ull) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallettstatic inline uint64_t CVMX_SRIOX_BELL_RESP_CTRL(unsigned long block_id) 90215976Sjmallett{ 91215976Sjmallett if (!( 92215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 93215976Sjmallett cvmx_warn("CVMX_SRIOX_BELL_RESP_CTRL(%lu) is invalid on this chip\n", block_id); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 1) * 0x1000000ull; 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 1) * 0x1000000ull) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallettstatic inline uint64_t CVMX_SRIOX_BIST_STATUS(unsigned long block_id) 101215976Sjmallett{ 102215976Sjmallett if (!( 103215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 104215976Sjmallett cvmx_warn("CVMX_SRIOX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 105215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 1) * 0x1000000ull; 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 1) * 0x1000000ull) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallettstatic inline uint64_t CVMX_SRIOX_IMSG_CTRL(unsigned long block_id) 112215976Sjmallett{ 113215976Sjmallett if (!( 114215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 115215976Sjmallett cvmx_warn("CVMX_SRIOX_IMSG_CTRL(%lu) is invalid on this chip\n", block_id); 116215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 1) * 0x1000000ull; 117215976Sjmallett} 118215976Sjmallett#else 119215976Sjmallett#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 1) * 0x1000000ull) 120215976Sjmallett#endif 121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallettstatic inline uint64_t CVMX_SRIOX_IMSG_INST_HDRX(unsigned long offset, unsigned long block_id) 123215976Sjmallett{ 124215976Sjmallett if (!( 125215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 126215976Sjmallett cvmx_warn("CVMX_SRIOX_IMSG_INST_HDRX(%lu,%lu) is invalid on this chip\n", offset, block_id); 127215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 1) * 0x200000ull) * 8; 128215976Sjmallett} 129215976Sjmallett#else 130215976Sjmallett#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 1) * 0x200000ull) * 8) 131215976Sjmallett#endif 132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133215976Sjmallettstatic inline uint64_t CVMX_SRIOX_IMSG_QOS_GRPX(unsigned long offset, unsigned long block_id) 134215976Sjmallett{ 135215976Sjmallett if (!( 136215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 31)) && ((block_id <= 1)))))) 137215976Sjmallett cvmx_warn("CVMX_SRIOX_IMSG_QOS_GRPX(%lu,%lu) is invalid on this chip\n", offset, block_id); 138215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8; 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8) 142215976Sjmallett#endif 143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144215976Sjmallettstatic inline uint64_t CVMX_SRIOX_IMSG_STATUSX(unsigned long offset, unsigned long block_id) 145215976Sjmallett{ 146215976Sjmallett if (!( 147215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 23)) && ((block_id <= 1)))))) 148215976Sjmallett cvmx_warn("CVMX_SRIOX_IMSG_STATUSX(%lu,%lu) is invalid on this chip\n", offset, block_id); 149215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8; 150215976Sjmallett} 151215976Sjmallett#else 152215976Sjmallett#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 1) * 0x200000ull) * 8) 153215976Sjmallett#endif 154215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155215976Sjmallettstatic inline uint64_t CVMX_SRIOX_IMSG_VPORT_THR(unsigned long block_id) 156215976Sjmallett{ 157215976Sjmallett if (!( 158215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 159215976Sjmallett cvmx_warn("CVMX_SRIOX_IMSG_VPORT_THR(%lu) is invalid on this chip\n", block_id); 160215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 1) * 0x1000000ull; 161215976Sjmallett} 162215976Sjmallett#else 163215976Sjmallett#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 1) * 0x1000000ull) 164215976Sjmallett#endif 165215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT2_ENABLE(unsigned long block_id) 167215976Sjmallett{ 168215976Sjmallett if (!( 169215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 170215976Sjmallett cvmx_warn("CVMX_SRIOX_INT2_ENABLE(%lu) is invalid on this chip\n", block_id); 171215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 1) * 0x1000000ull; 172215976Sjmallett} 173215976Sjmallett#else 174215976Sjmallett#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 1) * 0x1000000ull) 175215976Sjmallett#endif 176215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT2_REG(unsigned long block_id) 178215976Sjmallett{ 179215976Sjmallett if (!( 180215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 181215976Sjmallett cvmx_warn("CVMX_SRIOX_INT2_REG(%lu) is invalid on this chip\n", block_id); 182215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 1) * 0x1000000ull; 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 1) * 0x1000000ull) 186215976Sjmallett#endif 187215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT_ENABLE(unsigned long block_id) 189215976Sjmallett{ 190215976Sjmallett if (!( 191215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 192215976Sjmallett cvmx_warn("CVMX_SRIOX_INT_ENABLE(%lu) is invalid on this chip\n", block_id); 193215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 1) * 0x1000000ull; 194215976Sjmallett} 195215976Sjmallett#else 196215976Sjmallett#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 1) * 0x1000000ull) 197215976Sjmallett#endif 198215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT_INFO0(unsigned long block_id) 200215976Sjmallett{ 201215976Sjmallett if (!( 202215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 203215976Sjmallett cvmx_warn("CVMX_SRIOX_INT_INFO0(%lu) is invalid on this chip\n", block_id); 204215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 1) * 0x1000000ull; 205215976Sjmallett} 206215976Sjmallett#else 207215976Sjmallett#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 1) * 0x1000000ull) 208215976Sjmallett#endif 209215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT_INFO1(unsigned long block_id) 211215976Sjmallett{ 212215976Sjmallett if (!( 213215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 214215976Sjmallett cvmx_warn("CVMX_SRIOX_INT_INFO1(%lu) is invalid on this chip\n", block_id); 215215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 1) * 0x1000000ull; 216215976Sjmallett} 217215976Sjmallett#else 218215976Sjmallett#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 1) * 0x1000000ull) 219215976Sjmallett#endif 220215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT_INFO2(unsigned long block_id) 222215976Sjmallett{ 223215976Sjmallett if (!( 224215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 225215976Sjmallett cvmx_warn("CVMX_SRIOX_INT_INFO2(%lu) is invalid on this chip\n", block_id); 226215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 1) * 0x1000000ull; 227215976Sjmallett} 228215976Sjmallett#else 229215976Sjmallett#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 1) * 0x1000000ull) 230215976Sjmallett#endif 231215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT_INFO3(unsigned long block_id) 233215976Sjmallett{ 234215976Sjmallett if (!( 235215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 236215976Sjmallett cvmx_warn("CVMX_SRIOX_INT_INFO3(%lu) is invalid on this chip\n", block_id); 237215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 1) * 0x1000000ull; 238215976Sjmallett} 239215976Sjmallett#else 240215976Sjmallett#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 1) * 0x1000000ull) 241215976Sjmallett#endif 242215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT_REG(unsigned long block_id) 244215976Sjmallett{ 245215976Sjmallett if (!( 246215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 247215976Sjmallett cvmx_warn("CVMX_SRIOX_INT_REG(%lu) is invalid on this chip\n", block_id); 248215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 1) * 0x1000000ull; 249215976Sjmallett} 250215976Sjmallett#else 251215976Sjmallett#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 1) * 0x1000000ull) 252215976Sjmallett#endif 253215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254215976Sjmallettstatic inline uint64_t CVMX_SRIOX_IP_FEATURE(unsigned long block_id) 255215976Sjmallett{ 256215976Sjmallett if (!( 257215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 258215976Sjmallett cvmx_warn("CVMX_SRIOX_IP_FEATURE(%lu) is invalid on this chip\n", block_id); 259215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 1) * 0x1000000ull; 260215976Sjmallett} 261215976Sjmallett#else 262215976Sjmallett#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 1) * 0x1000000ull) 263215976Sjmallett#endif 264215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265215976Sjmallettstatic inline uint64_t CVMX_SRIOX_MAC_BUFFERS(unsigned long block_id) 266215976Sjmallett{ 267215976Sjmallett if (!( 268215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 269215976Sjmallett cvmx_warn("CVMX_SRIOX_MAC_BUFFERS(%lu) is invalid on this chip\n", block_id); 270215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 1) * 0x1000000ull; 271215976Sjmallett} 272215976Sjmallett#else 273215976Sjmallett#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 1) * 0x1000000ull) 274215976Sjmallett#endif 275215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276215976Sjmallettstatic inline uint64_t CVMX_SRIOX_MAINT_OP(unsigned long block_id) 277215976Sjmallett{ 278215976Sjmallett if (!( 279215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 280215976Sjmallett cvmx_warn("CVMX_SRIOX_MAINT_OP(%lu) is invalid on this chip\n", block_id); 281215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 1) * 0x1000000ull; 282215976Sjmallett} 283215976Sjmallett#else 284215976Sjmallett#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 1) * 0x1000000ull) 285215976Sjmallett#endif 286215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287215976Sjmallettstatic inline uint64_t CVMX_SRIOX_MAINT_RD_DATA(unsigned long block_id) 288215976Sjmallett{ 289215976Sjmallett if (!( 290215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 291215976Sjmallett cvmx_warn("CVMX_SRIOX_MAINT_RD_DATA(%lu) is invalid on this chip\n", block_id); 292215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 1) * 0x1000000ull; 293215976Sjmallett} 294215976Sjmallett#else 295215976Sjmallett#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 1) * 0x1000000ull) 296215976Sjmallett#endif 297215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298215976Sjmallettstatic inline uint64_t CVMX_SRIOX_MCE_TX_CTL(unsigned long block_id) 299215976Sjmallett{ 300215976Sjmallett if (!( 301215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 302215976Sjmallett cvmx_warn("CVMX_SRIOX_MCE_TX_CTL(%lu) is invalid on this chip\n", block_id); 303215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 1) * 0x1000000ull; 304215976Sjmallett} 305215976Sjmallett#else 306215976Sjmallett#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 1) * 0x1000000ull) 307215976Sjmallett#endif 308215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309215976Sjmallettstatic inline uint64_t CVMX_SRIOX_MEM_OP_CTRL(unsigned long block_id) 310215976Sjmallett{ 311215976Sjmallett if (!( 312215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 313215976Sjmallett cvmx_warn("CVMX_SRIOX_MEM_OP_CTRL(%lu) is invalid on this chip\n", block_id); 314215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 1) * 0x1000000ull; 315215976Sjmallett} 316215976Sjmallett#else 317215976Sjmallett#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 1) * 0x1000000ull) 318215976Sjmallett#endif 319215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_CTRLX(unsigned long offset, unsigned long block_id) 321215976Sjmallett{ 322215976Sjmallett if (!( 323215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 324215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_CTRLX(%lu,%lu) is invalid on this chip\n", offset, block_id); 325215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64; 326215976Sjmallett} 327215976Sjmallett#else 328215976Sjmallett#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64) 329215976Sjmallett#endif 330215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_DONE_COUNTSX(unsigned long offset, unsigned long block_id) 332215976Sjmallett{ 333215976Sjmallett if (!( 334215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 335215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_DONE_COUNTSX(%lu,%lu) is invalid on this chip\n", offset, block_id); 336215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64; 337215976Sjmallett} 338215976Sjmallett#else 339215976Sjmallett#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64) 340215976Sjmallett#endif 341215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_FMP_MRX(unsigned long offset, unsigned long block_id) 343215976Sjmallett{ 344215976Sjmallett if (!( 345215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 346215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_FMP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id); 347215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64; 348215976Sjmallett} 349215976Sjmallett#else 350215976Sjmallett#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64) 351215976Sjmallett#endif 352215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 353215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_NMP_MRX(unsigned long offset, unsigned long block_id) 354215976Sjmallett{ 355215976Sjmallett if (!( 356215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 357215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_NMP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id); 358215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64; 359215976Sjmallett} 360215976Sjmallett#else 361215976Sjmallett#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64) 362215976Sjmallett#endif 363215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 364215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_PORTX(unsigned long offset, unsigned long block_id) 365215976Sjmallett{ 366215976Sjmallett if (!( 367215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 368215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_PORTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 369215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64; 370215976Sjmallett} 371215976Sjmallett#else 372215976Sjmallett#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64) 373215976Sjmallett#endif 374215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 375215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_SILO_THR(unsigned long block_id) 376215976Sjmallett{ 377215976Sjmallett if (!( 378215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 379215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_SILO_THR(%lu) is invalid on this chip\n", block_id); 380215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 1) * 0x1000000ull; 381215976Sjmallett} 382215976Sjmallett#else 383215976Sjmallett#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 1) * 0x1000000ull) 384215976Sjmallett#endif 385215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_SP_MRX(unsigned long offset, unsigned long block_id) 387215976Sjmallett{ 388215976Sjmallett if (!( 389215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))))) 390215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_SP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id); 391215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64; 392215976Sjmallett} 393215976Sjmallett#else 394215976Sjmallett#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 1) * 0x40000ull) * 64) 395215976Sjmallett#endif 396215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397215976Sjmallettstatic inline uint64_t CVMX_SRIOX_PRIOX_IN_USE(unsigned long offset, unsigned long block_id) 398215976Sjmallett{ 399215976Sjmallett if (!( 400215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))))) 401215976Sjmallett cvmx_warn("CVMX_SRIOX_PRIOX_IN_USE(%lu,%lu) is invalid on this chip\n", offset, block_id); 402215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x200000ull) * 8; 403215976Sjmallett} 404215976Sjmallett#else 405215976Sjmallett#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x200000ull) * 8) 406215976Sjmallett#endif 407215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408215976Sjmallettstatic inline uint64_t CVMX_SRIOX_RX_BELL(unsigned long block_id) 409215976Sjmallett{ 410215976Sjmallett if (!( 411215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 412215976Sjmallett cvmx_warn("CVMX_SRIOX_RX_BELL(%lu) is invalid on this chip\n", block_id); 413215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 1) * 0x1000000ull; 414215976Sjmallett} 415215976Sjmallett#else 416215976Sjmallett#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 1) * 0x1000000ull) 417215976Sjmallett#endif 418215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 419215976Sjmallettstatic inline uint64_t CVMX_SRIOX_RX_BELL_SEQ(unsigned long block_id) 420215976Sjmallett{ 421215976Sjmallett if (!( 422215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 423215976Sjmallett cvmx_warn("CVMX_SRIOX_RX_BELL_SEQ(%lu) is invalid on this chip\n", block_id); 424215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 1) * 0x1000000ull; 425215976Sjmallett} 426215976Sjmallett#else 427215976Sjmallett#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 1) * 0x1000000ull) 428215976Sjmallett#endif 429215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430215976Sjmallettstatic inline uint64_t CVMX_SRIOX_RX_STATUS(unsigned long block_id) 431215976Sjmallett{ 432215976Sjmallett if (!( 433215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 434215976Sjmallett cvmx_warn("CVMX_SRIOX_RX_STATUS(%lu) is invalid on this chip\n", block_id); 435215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 1) * 0x1000000ull; 436215976Sjmallett} 437215976Sjmallett#else 438215976Sjmallett#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 1) * 0x1000000ull) 439215976Sjmallett#endif 440215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441215976Sjmallettstatic inline uint64_t CVMX_SRIOX_S2M_TYPEX(unsigned long offset, unsigned long block_id) 442215976Sjmallett{ 443215976Sjmallett if (!( 444215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))))) 445215976Sjmallett cvmx_warn("CVMX_SRIOX_S2M_TYPEX(%lu,%lu) is invalid on this chip\n", offset, block_id); 446215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8; 447215976Sjmallett} 448215976Sjmallett#else 449215976Sjmallett#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8) 450215976Sjmallett#endif 451215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452215976Sjmallettstatic inline uint64_t CVMX_SRIOX_SEQ(unsigned long block_id) 453215976Sjmallett{ 454215976Sjmallett if (!( 455215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 456215976Sjmallett cvmx_warn("CVMX_SRIOX_SEQ(%lu) is invalid on this chip\n", block_id); 457215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 1) * 0x1000000ull; 458215976Sjmallett} 459215976Sjmallett#else 460215976Sjmallett#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 1) * 0x1000000ull) 461215976Sjmallett#endif 462215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463215976Sjmallettstatic inline uint64_t CVMX_SRIOX_STATUS_REG(unsigned long block_id) 464215976Sjmallett{ 465215976Sjmallett if (!( 466215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 467215976Sjmallett cvmx_warn("CVMX_SRIOX_STATUS_REG(%lu) is invalid on this chip\n", block_id); 468215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 1) * 0x1000000ull; 469215976Sjmallett} 470215976Sjmallett#else 471215976Sjmallett#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 1) * 0x1000000ull) 472215976Sjmallett#endif 473215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TAG_CTRL(unsigned long block_id) 475215976Sjmallett{ 476215976Sjmallett if (!( 477215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 478215976Sjmallett cvmx_warn("CVMX_SRIOX_TAG_CTRL(%lu) is invalid on this chip\n", block_id); 479215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 1) * 0x1000000ull; 480215976Sjmallett} 481215976Sjmallett#else 482215976Sjmallett#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 1) * 0x1000000ull) 483215976Sjmallett#endif 484215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TLP_CREDITS(unsigned long block_id) 486215976Sjmallett{ 487215976Sjmallett if (!( 488215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 489215976Sjmallett cvmx_warn("CVMX_SRIOX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id); 490215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 1) * 0x1000000ull; 491215976Sjmallett} 492215976Sjmallett#else 493215976Sjmallett#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 1) * 0x1000000ull) 494215976Sjmallett#endif 495215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TX_BELL(unsigned long block_id) 497215976Sjmallett{ 498215976Sjmallett if (!( 499215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 500215976Sjmallett cvmx_warn("CVMX_SRIOX_TX_BELL(%lu) is invalid on this chip\n", block_id); 501215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 1) * 0x1000000ull; 502215976Sjmallett} 503215976Sjmallett#else 504215976Sjmallett#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 1) * 0x1000000ull) 505215976Sjmallett#endif 506215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TX_BELL_INFO(unsigned long block_id) 508215976Sjmallett{ 509215976Sjmallett if (!( 510215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 511215976Sjmallett cvmx_warn("CVMX_SRIOX_TX_BELL_INFO(%lu) is invalid on this chip\n", block_id); 512215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 1) * 0x1000000ull; 513215976Sjmallett} 514215976Sjmallett#else 515215976Sjmallett#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 1) * 0x1000000ull) 516215976Sjmallett#endif 517215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TX_CTRL(unsigned long block_id) 519215976Sjmallett{ 520215976Sjmallett if (!( 521215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 522215976Sjmallett cvmx_warn("CVMX_SRIOX_TX_CTRL(%lu) is invalid on this chip\n", block_id); 523215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 1) * 0x1000000ull; 524215976Sjmallett} 525215976Sjmallett#else 526215976Sjmallett#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 1) * 0x1000000ull) 527215976Sjmallett#endif 528215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TX_EMPHASIS(unsigned long block_id) 530215976Sjmallett{ 531215976Sjmallett if (!( 532215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 533215976Sjmallett cvmx_warn("CVMX_SRIOX_TX_EMPHASIS(%lu) is invalid on this chip\n", block_id); 534215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 1) * 0x1000000ull; 535215976Sjmallett} 536215976Sjmallett#else 537215976Sjmallett#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 1) * 0x1000000ull) 538215976Sjmallett#endif 539215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TX_STATUS(unsigned long block_id) 541215976Sjmallett{ 542215976Sjmallett if (!( 543215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 544215976Sjmallett cvmx_warn("CVMX_SRIOX_TX_STATUS(%lu) is invalid on this chip\n", block_id); 545215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 1) * 0x1000000ull; 546215976Sjmallett} 547215976Sjmallett#else 548215976Sjmallett#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 1) * 0x1000000ull) 549215976Sjmallett#endif 550215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551215976Sjmallettstatic inline uint64_t CVMX_SRIOX_WR_DONE_COUNTS(unsigned long block_id) 552215976Sjmallett{ 553215976Sjmallett if (!( 554215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 555215976Sjmallett cvmx_warn("CVMX_SRIOX_WR_DONE_COUNTS(%lu) is invalid on this chip\n", block_id); 556215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 1) * 0x1000000ull; 557215976Sjmallett} 558215976Sjmallett#else 559215976Sjmallett#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 1) * 0x1000000ull) 560215976Sjmallett#endif 561215976Sjmallett 562215976Sjmallett/** 563215976Sjmallett * cvmx_srio#_acc_ctrl 564215976Sjmallett * 565215976Sjmallett * SRIO_ACC_CTRL = SRIO Access Control 566215976Sjmallett * 567215976Sjmallett * General access control of the incoming BAR registers. 568215976Sjmallett * 569215976Sjmallett * Notes: 570215976Sjmallett * This register controls write access to the BAR registers via SRIO Maintenance Operations. At 571215976Sjmallett * powerup the BAR registers can be accessed via RSL and Maintenance Operations. If the DENY_BAR* 572215976Sjmallett * bits are set then Maintenance Writes to the corresponding BAR registers are ignored. This 573215976Sjmallett * register does not effect read operations. 574215976Sjmallett * 575215976Sjmallett * Clk_Rst: SRIO(0..1)_ACC_CTRL hclk hrst_n 576215976Sjmallett */ 577215976Sjmallettunion cvmx_sriox_acc_ctrl 578215976Sjmallett{ 579215976Sjmallett uint64_t u64; 580215976Sjmallett struct cvmx_sriox_acc_ctrl_s 581215976Sjmallett { 582215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 583215976Sjmallett uint64_t reserved_3_63 : 61; 584215976Sjmallett uint64_t deny_bar2 : 1; /**< Deny SRIO Write Access to BAR2 Registers */ 585215976Sjmallett uint64_t deny_bar1 : 1; /**< Deny SRIO Write Access to BAR1 Registers */ 586215976Sjmallett uint64_t deny_bar0 : 1; /**< Deny SRIO Write Access to BAR0 Registers */ 587215976Sjmallett#else 588215976Sjmallett uint64_t deny_bar0 : 1; 589215976Sjmallett uint64_t deny_bar1 : 1; 590215976Sjmallett uint64_t deny_bar2 : 1; 591215976Sjmallett uint64_t reserved_3_63 : 61; 592215976Sjmallett#endif 593215976Sjmallett } s; 594215976Sjmallett struct cvmx_sriox_acc_ctrl_s cn63xx; 595215976Sjmallett struct cvmx_sriox_acc_ctrl_s cn63xxp1; 596215976Sjmallett}; 597215976Sjmalletttypedef union cvmx_sriox_acc_ctrl cvmx_sriox_acc_ctrl_t; 598215976Sjmallett 599215976Sjmallett/** 600215976Sjmallett * cvmx_srio#_asmbly_id 601215976Sjmallett * 602215976Sjmallett * SRIO_ASMBLY_ID = SRIO Assembly ID 603215976Sjmallett * 604215976Sjmallett * The Assembly ID register controls the Assembly ID and Vendor 605215976Sjmallett * 606215976Sjmallett * Notes: 607215976Sjmallett * This register specifies the Assembly ID and Vendor visible in SRIOMAINT(0..1)_ASMBLY_ID register. The 608215976Sjmallett * Assembly Vendor ID is typically supplied by the RapidIO Trade Association. This register is only 609215976Sjmallett * reset during COLD boot and may only be modified while SRIO(0..1)_STATUS_REG.ACCESS is zero. 610215976Sjmallett * 611215976Sjmallett * Clk_Rst: SRIO(0..1)_ASMBLY_ID sclk srst_cold_n 612215976Sjmallett */ 613215976Sjmallettunion cvmx_sriox_asmbly_id 614215976Sjmallett{ 615215976Sjmallett uint64_t u64; 616215976Sjmallett struct cvmx_sriox_asmbly_id_s 617215976Sjmallett { 618215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 619215976Sjmallett uint64_t reserved_32_63 : 32; 620215976Sjmallett uint64_t assy_id : 16; /**< Assembly Identifer */ 621215976Sjmallett uint64_t assy_ven : 16; /**< Assembly Vendor Identifer */ 622215976Sjmallett#else 623215976Sjmallett uint64_t assy_ven : 16; 624215976Sjmallett uint64_t assy_id : 16; 625215976Sjmallett uint64_t reserved_32_63 : 32; 626215976Sjmallett#endif 627215976Sjmallett } s; 628215976Sjmallett struct cvmx_sriox_asmbly_id_s cn63xx; 629215976Sjmallett struct cvmx_sriox_asmbly_id_s cn63xxp1; 630215976Sjmallett}; 631215976Sjmalletttypedef union cvmx_sriox_asmbly_id cvmx_sriox_asmbly_id_t; 632215976Sjmallett 633215976Sjmallett/** 634215976Sjmallett * cvmx_srio#_asmbly_info 635215976Sjmallett * 636215976Sjmallett * SRIO_ASMBLY_INFO = SRIO Assembly Information 637215976Sjmallett * 638215976Sjmallett * The Assembly Info register controls the Assembly Revision 639215976Sjmallett * 640215976Sjmallett * Notes: 641215976Sjmallett * The Assembly Info register controls the Assembly Revision visible in the ASSY_REV field of the 642215976Sjmallett * SRIOMAINT(0..1)_ASMBLY_INFO register. This register is only reset during COLD boot and may only be 643215976Sjmallett * modified while SRIO(0..1)_STATUS_REG.ACCESS is zero. 644215976Sjmallett * 645215976Sjmallett * Clk_Rst: SRIO(0..1)_ASMBLY_INFO sclk srst_cold_n 646215976Sjmallett */ 647215976Sjmallettunion cvmx_sriox_asmbly_info 648215976Sjmallett{ 649215976Sjmallett uint64_t u64; 650215976Sjmallett struct cvmx_sriox_asmbly_info_s 651215976Sjmallett { 652215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 653215976Sjmallett uint64_t reserved_32_63 : 32; 654215976Sjmallett uint64_t assy_rev : 16; /**< Assembly Revision */ 655215976Sjmallett uint64_t reserved_0_15 : 16; 656215976Sjmallett#else 657215976Sjmallett uint64_t reserved_0_15 : 16; 658215976Sjmallett uint64_t assy_rev : 16; 659215976Sjmallett uint64_t reserved_32_63 : 32; 660215976Sjmallett#endif 661215976Sjmallett } s; 662215976Sjmallett struct cvmx_sriox_asmbly_info_s cn63xx; 663215976Sjmallett struct cvmx_sriox_asmbly_info_s cn63xxp1; 664215976Sjmallett}; 665215976Sjmalletttypedef union cvmx_sriox_asmbly_info cvmx_sriox_asmbly_info_t; 666215976Sjmallett 667215976Sjmallett/** 668215976Sjmallett * cvmx_srio#_bell_resp_ctrl 669215976Sjmallett * 670215976Sjmallett * SRIO_BELL_RESP_CTRL = SRIO Doorbell Response Control 671215976Sjmallett * 672215976Sjmallett * The SRIO Doorbell Response Control Register 673215976Sjmallett * 674215976Sjmallett * Notes: 675215976Sjmallett * This register is used to override the response priority of the outgoing doorbell responses. 676215976Sjmallett * 677215976Sjmallett * Clk_Rst: SRIO(0..1)_BELL_RESP_CTRL hclk hrst_n 678215976Sjmallett */ 679215976Sjmallettunion cvmx_sriox_bell_resp_ctrl 680215976Sjmallett{ 681215976Sjmallett uint64_t u64; 682215976Sjmallett struct cvmx_sriox_bell_resp_ctrl_s 683215976Sjmallett { 684215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 685215976Sjmallett uint64_t reserved_6_63 : 58; 686215976Sjmallett uint64_t rp1_sid : 1; /**< Sets response priority for incomimg doorbells 687215976Sjmallett of priority 1 on the secondary ID (0=2, 1=3) */ 688215976Sjmallett uint64_t rp0_sid : 2; /**< Sets response priority for incomimg doorbells 689215976Sjmallett of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */ 690215976Sjmallett uint64_t rp1_pid : 1; /**< Sets response priority for incomimg doorbells 691215976Sjmallett of priority 1 on the primary ID (0=2, 1=3) */ 692215976Sjmallett uint64_t rp0_pid : 2; /**< Sets response priority for incomimg doorbells 693215976Sjmallett of priority 0 on the primary ID (0,1=1 2=2, 3=3) */ 694215976Sjmallett#else 695215976Sjmallett uint64_t rp0_pid : 2; 696215976Sjmallett uint64_t rp1_pid : 1; 697215976Sjmallett uint64_t rp0_sid : 2; 698215976Sjmallett uint64_t rp1_sid : 1; 699215976Sjmallett uint64_t reserved_6_63 : 58; 700215976Sjmallett#endif 701215976Sjmallett } s; 702215976Sjmallett struct cvmx_sriox_bell_resp_ctrl_s cn63xx; 703215976Sjmallett struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1; 704215976Sjmallett}; 705215976Sjmalletttypedef union cvmx_sriox_bell_resp_ctrl cvmx_sriox_bell_resp_ctrl_t; 706215976Sjmallett 707215976Sjmallett/** 708215976Sjmallett * cvmx_srio#_bist_status 709215976Sjmallett * 710215976Sjmallett * SRIO_BIST_STATUS = SRIO Bist Status 711215976Sjmallett * 712215976Sjmallett * Results from BIST runs of SRIO's memories. 713215976Sjmallett * 714215976Sjmallett * Notes: 715215976Sjmallett * BIST Results. 716215976Sjmallett * 717215976Sjmallett * Clk_Rst: SRIO(0..1)_BIST_STATUS hclk hrst_n 718215976Sjmallett */ 719215976Sjmallettunion cvmx_sriox_bist_status 720215976Sjmallett{ 721215976Sjmallett uint64_t u64; 722215976Sjmallett struct cvmx_sriox_bist_status_s 723215976Sjmallett { 724215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 725215976Sjmallett uint64_t reserved_44_63 : 20; 726215976Sjmallett uint64_t mram : 2; /**< Incoming Message SLI FIFO. */ 727215976Sjmallett uint64_t cram : 2; /**< Incoming Rd/Wr/Response Command FIFO. */ 728215976Sjmallett uint64_t bell : 2; /**< Incoming Doorbell FIFO. */ 729215976Sjmallett uint64_t otag : 2; /**< Outgoing Tag Data. */ 730215976Sjmallett uint64_t itag : 1; /**< Incoming TAG Data. */ 731215976Sjmallett uint64_t ofree : 1; /**< Outgoing Free Pointer RAM (OFIFO) */ 732215976Sjmallett uint64_t rtn : 2; /**< Outgoing Response Return FIFO. */ 733215976Sjmallett uint64_t obulk : 4; /**< Outgoing Bulk Data RAMs (OFIFO) */ 734215976Sjmallett uint64_t optrs : 4; /**< Outgoing Priority Pointer RAMs (OFIFO) */ 735215976Sjmallett uint64_t reserved_22_23 : 2; 736215976Sjmallett uint64_t rxbuf2 : 2; /**< Additional Incoming SRIO MAC Buffers (Pass 2). */ 737215976Sjmallett uint64_t oarb : 2; /**< Outgoing Priority RAMs (OARB) */ 738215976Sjmallett uint64_t ispf : 1; /**< Incoming Soft Packet FIFO */ 739215976Sjmallett uint64_t ospf : 1; /**< Outgoing Soft Packet FIFO */ 740215976Sjmallett uint64_t txbuf : 2; /**< Outgoing SRIO MAC Buffer. */ 741215976Sjmallett uint64_t rxbuf : 2; /**< Incoming SRIO MAC Buffer. */ 742215976Sjmallett uint64_t imsg : 5; /**< Incoming Message RAMs. */ 743215976Sjmallett uint64_t omsg : 7; /**< Outgoing Message RAMs. */ 744215976Sjmallett#else 745215976Sjmallett uint64_t omsg : 7; 746215976Sjmallett uint64_t imsg : 5; 747215976Sjmallett uint64_t rxbuf : 2; 748215976Sjmallett uint64_t txbuf : 2; 749215976Sjmallett uint64_t ospf : 1; 750215976Sjmallett uint64_t ispf : 1; 751215976Sjmallett uint64_t oarb : 2; 752215976Sjmallett uint64_t rxbuf2 : 2; 753215976Sjmallett uint64_t reserved_22_23 : 2; 754215976Sjmallett uint64_t optrs : 4; 755215976Sjmallett uint64_t obulk : 4; 756215976Sjmallett uint64_t rtn : 2; 757215976Sjmallett uint64_t ofree : 1; 758215976Sjmallett uint64_t itag : 1; 759215976Sjmallett uint64_t otag : 2; 760215976Sjmallett uint64_t bell : 2; 761215976Sjmallett uint64_t cram : 2; 762215976Sjmallett uint64_t mram : 2; 763215976Sjmallett uint64_t reserved_44_63 : 20; 764215976Sjmallett#endif 765215976Sjmallett } s; 766215976Sjmallett struct cvmx_sriox_bist_status_s cn63xx; 767215976Sjmallett struct cvmx_sriox_bist_status_cn63xxp1 768215976Sjmallett { 769215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 770215976Sjmallett uint64_t reserved_44_63 : 20; 771215976Sjmallett uint64_t mram : 2; /**< Incoming Message SLI FIFO. */ 772215976Sjmallett uint64_t cram : 2; /**< Incoming Rd/Wr/Response Command FIFO. */ 773215976Sjmallett uint64_t bell : 2; /**< Incoming Doorbell FIFO. */ 774215976Sjmallett uint64_t otag : 2; /**< Outgoing Tag Data. */ 775215976Sjmallett uint64_t itag : 1; /**< Incoming TAG Data. */ 776215976Sjmallett uint64_t ofree : 1; /**< Outgoing Free Pointer RAM (OFIFO) */ 777215976Sjmallett uint64_t rtn : 2; /**< Outgoing Response Return FIFO. */ 778215976Sjmallett uint64_t obulk : 4; /**< Outgoing Bulk Data RAMs (OFIFO) */ 779215976Sjmallett uint64_t optrs : 4; /**< Outgoing Priority Pointer RAMs (OFIFO) */ 780215976Sjmallett uint64_t reserved_20_23 : 4; 781215976Sjmallett uint64_t oarb : 2; /**< Outgoing Priority RAMs (OARB) */ 782215976Sjmallett uint64_t ispf : 1; /**< Incoming Soft Packet FIFO */ 783215976Sjmallett uint64_t ospf : 1; /**< Outgoing Soft Packet FIFO */ 784215976Sjmallett uint64_t txbuf : 2; /**< Outgoing SRIO MAC Buffer. */ 785215976Sjmallett uint64_t rxbuf : 2; /**< Incoming SRIO MAC Buffer. */ 786215976Sjmallett uint64_t imsg : 5; /**< Incoming Message RAMs. */ 787215976Sjmallett uint64_t omsg : 7; /**< Outgoing Message RAMs. */ 788215976Sjmallett#else 789215976Sjmallett uint64_t omsg : 7; 790215976Sjmallett uint64_t imsg : 5; 791215976Sjmallett uint64_t rxbuf : 2; 792215976Sjmallett uint64_t txbuf : 2; 793215976Sjmallett uint64_t ospf : 1; 794215976Sjmallett uint64_t ispf : 1; 795215976Sjmallett uint64_t oarb : 2; 796215976Sjmallett uint64_t reserved_20_23 : 4; 797215976Sjmallett uint64_t optrs : 4; 798215976Sjmallett uint64_t obulk : 4; 799215976Sjmallett uint64_t rtn : 2; 800215976Sjmallett uint64_t ofree : 1; 801215976Sjmallett uint64_t itag : 1; 802215976Sjmallett uint64_t otag : 2; 803215976Sjmallett uint64_t bell : 2; 804215976Sjmallett uint64_t cram : 2; 805215976Sjmallett uint64_t mram : 2; 806215976Sjmallett uint64_t reserved_44_63 : 20; 807215976Sjmallett#endif 808215976Sjmallett } cn63xxp1; 809215976Sjmallett}; 810215976Sjmalletttypedef union cvmx_sriox_bist_status cvmx_sriox_bist_status_t; 811215976Sjmallett 812215976Sjmallett/** 813215976Sjmallett * cvmx_srio#_imsg_ctrl 814215976Sjmallett * 815215976Sjmallett * SRIO_IMSG_CTRL = SRIO Incoming Message Control 816215976Sjmallett * 817215976Sjmallett * The SRIO Incoming Message Control Register 818215976Sjmallett * 819215976Sjmallett * Notes: 820215976Sjmallett * RSP_THR should not typically be modified from reset value. 821215976Sjmallett * 822215976Sjmallett * Clk_Rst: SRIO(0..1)_IMSG_CTRL hclk hrst_n 823215976Sjmallett */ 824215976Sjmallettunion cvmx_sriox_imsg_ctrl 825215976Sjmallett{ 826215976Sjmallett uint64_t u64; 827215976Sjmallett struct cvmx_sriox_imsg_ctrl_s 828215976Sjmallett { 829215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 830215976Sjmallett uint64_t reserved_32_63 : 32; 831215976Sjmallett uint64_t to_mode : 1; /**< MP message timeout mode: 832215976Sjmallett - 0: The timeout counter gets reset whenever the 833215976Sjmallett next sequential segment is received, regardless 834215976Sjmallett of whether it is accepted 835215976Sjmallett - 1: The timeout counter gets reset only when the 836215976Sjmallett next sequential segment is received and 837215976Sjmallett accepted */ 838215976Sjmallett uint64_t reserved_30_30 : 1; 839215976Sjmallett uint64_t rsp_thr : 6; /**< Sets max number of msg responses in queue before 840215976Sjmallett sending link-layer retries (field value is added 841215976Sjmallett to 16 to create threshold value) */ 842215976Sjmallett uint64_t reserved_22_23 : 2; 843215976Sjmallett uint64_t rp1_sid : 1; /**< Sets msg response priority for incomimg messages 844215976Sjmallett of priority 1 on the secondary ID (0=2, 1=3) */ 845215976Sjmallett uint64_t rp0_sid : 2; /**< Sets msg response priority for incomimg messages 846215976Sjmallett of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */ 847215976Sjmallett uint64_t rp1_pid : 1; /**< Sets msg response priority for incomimg messages 848215976Sjmallett of priority 1 on the primary ID (0=2, 1=3) */ 849215976Sjmallett uint64_t rp0_pid : 2; /**< Sets msg response priority for incomimg messages 850215976Sjmallett of priority 0 on the primary ID (0,1=1 2=2, 3=3) */ 851215976Sjmallett uint64_t reserved_15_15 : 1; 852215976Sjmallett uint64_t prt_sel : 3; /**< Port/Controller selection method: 853215976Sjmallett - 0: Table lookup based on mailbox 854215976Sjmallett - 1: Table lookup based on priority 855215976Sjmallett - 2: Table lookup based on letter 856215976Sjmallett - 3: Size-based (SP to port 0, MP to port 1) 857215976Sjmallett - 4: ID-based (pri ID to port 0, sec ID to port 1) */ 858215976Sjmallett uint64_t lttr : 4; /**< Port/Controller selection letter table */ 859215976Sjmallett uint64_t prio : 4; /**< Port/Controller selection priority table */ 860215976Sjmallett uint64_t mbox : 4; /**< Port/Controller selection mailbox table */ 861215976Sjmallett#else 862215976Sjmallett uint64_t mbox : 4; 863215976Sjmallett uint64_t prio : 4; 864215976Sjmallett uint64_t lttr : 4; 865215976Sjmallett uint64_t prt_sel : 3; 866215976Sjmallett uint64_t reserved_15_15 : 1; 867215976Sjmallett uint64_t rp0_pid : 2; 868215976Sjmallett uint64_t rp1_pid : 1; 869215976Sjmallett uint64_t rp0_sid : 2; 870215976Sjmallett uint64_t rp1_sid : 1; 871215976Sjmallett uint64_t reserved_22_23 : 2; 872215976Sjmallett uint64_t rsp_thr : 6; 873215976Sjmallett uint64_t reserved_30_30 : 1; 874215976Sjmallett uint64_t to_mode : 1; 875215976Sjmallett uint64_t reserved_32_63 : 32; 876215976Sjmallett#endif 877215976Sjmallett } s; 878215976Sjmallett struct cvmx_sriox_imsg_ctrl_s cn63xx; 879215976Sjmallett struct cvmx_sriox_imsg_ctrl_s cn63xxp1; 880215976Sjmallett}; 881215976Sjmalletttypedef union cvmx_sriox_imsg_ctrl cvmx_sriox_imsg_ctrl_t; 882215976Sjmallett 883215976Sjmallett/** 884215976Sjmallett * cvmx_srio#_imsg_inst_hdr# 885215976Sjmallett * 886215976Sjmallett * SRIO_IMSG_INST_HDRX = SRIO Incoming Message Packet Instruction Header 887215976Sjmallett * 888215976Sjmallett * The SRIO Port/Controller X Incoming Message Packet Instruction Header Register 889215976Sjmallett * 890215976Sjmallett * Notes: 891215976Sjmallett * SRIO HW generates most of the SRIO_WORD1 fields from these values. SRIO_WORD1 is the 2nd of two 892215976Sjmallett * header words that SRIO inserts in front of all received messages. SRIO_WORD1 may commonly be used 893215976Sjmallett * as a PIP/IPD PKT_INST_HDR. This CSR matches the PIP/IPD PKT_INST_HDR format except for the QOS 894215976Sjmallett * and GRP fields. SRIO*_IMSG_QOS_GRP*[QOS*,GRP*] supply the QOS and GRP fields. 895215976Sjmallett * 896215976Sjmallett * Clk_Rst: SRIO(0..1)_IMSG_INST_HDR[0:1] hclk hrst_n 897215976Sjmallett */ 898215976Sjmallettunion cvmx_sriox_imsg_inst_hdrx 899215976Sjmallett{ 900215976Sjmallett uint64_t u64; 901215976Sjmallett struct cvmx_sriox_imsg_inst_hdrx_s 902215976Sjmallett { 903215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 904215976Sjmallett uint64_t r : 1; /**< Port/Controller X R */ 905215976Sjmallett uint64_t reserved_58_62 : 5; 906215976Sjmallett uint64_t pm : 2; /**< Port/Controller X PM */ 907215976Sjmallett uint64_t reserved_55_55 : 1; 908215976Sjmallett uint64_t sl : 7; /**< Port/Controller X SL */ 909215976Sjmallett uint64_t reserved_46_47 : 2; 910215976Sjmallett uint64_t nqos : 1; /**< Port/Controller X NQOS */ 911215976Sjmallett uint64_t ngrp : 1; /**< Port/Controller X NGRP */ 912215976Sjmallett uint64_t ntt : 1; /**< Port/Controller X NTT */ 913215976Sjmallett uint64_t ntag : 1; /**< Port/Controller X NTAG */ 914215976Sjmallett uint64_t reserved_35_41 : 7; 915215976Sjmallett uint64_t rs : 1; /**< Port/Controller X RS */ 916215976Sjmallett uint64_t tt : 2; /**< Port/Controller X TT */ 917215976Sjmallett uint64_t tag : 32; /**< Port/Controller X TAG */ 918215976Sjmallett#else 919215976Sjmallett uint64_t tag : 32; 920215976Sjmallett uint64_t tt : 2; 921215976Sjmallett uint64_t rs : 1; 922215976Sjmallett uint64_t reserved_35_41 : 7; 923215976Sjmallett uint64_t ntag : 1; 924215976Sjmallett uint64_t ntt : 1; 925215976Sjmallett uint64_t ngrp : 1; 926215976Sjmallett uint64_t nqos : 1; 927215976Sjmallett uint64_t reserved_46_47 : 2; 928215976Sjmallett uint64_t sl : 7; 929215976Sjmallett uint64_t reserved_55_55 : 1; 930215976Sjmallett uint64_t pm : 2; 931215976Sjmallett uint64_t reserved_58_62 : 5; 932215976Sjmallett uint64_t r : 1; 933215976Sjmallett#endif 934215976Sjmallett } s; 935215976Sjmallett struct cvmx_sriox_imsg_inst_hdrx_s cn63xx; 936215976Sjmallett struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1; 937215976Sjmallett}; 938215976Sjmalletttypedef union cvmx_sriox_imsg_inst_hdrx cvmx_sriox_imsg_inst_hdrx_t; 939215976Sjmallett 940215976Sjmallett/** 941215976Sjmallett * cvmx_srio#_imsg_qos_grp# 942215976Sjmallett * 943215976Sjmallett * SRIO_IMSG_QOS_GRPX = SRIO Incoming Message QOS/GRP Table 944215976Sjmallett * 945215976Sjmallett * The SRIO Incoming Message QOS/GRP Table Entry X 946215976Sjmallett * 947215976Sjmallett * Notes: 948215976Sjmallett * The QOS/GRP table contains 32 entries with 8 QOS/GRP pairs per entry - 256 pairs total. 949215976Sjmallett * HW selects the table entry by the concatenation of SRIO_WORD0[PRIO,DIS,MBOX], thus entry 0 is 950215976Sjmallett * used for messages with PRIO=0,DIS=0,MBOX=0, entry 1 is for PRIO=0,DIS=0,MBOX=1, etc. HW 951215976Sjmallett * selects the QOS/GRP pair from the table entry by the concatenation of SRIO_WORD0[ID,LETTER] as 952215976Sjmallett * shown above. HW then inserts the QOS/GRP pair into SRIO_WORD1[QOS,GRP], which may commonly 953215976Sjmallett * be used for the PIP/IPD PKT_INST_HDR[QOS,GRP] fields. 954215976Sjmallett * 955215976Sjmallett * Clk_Rst: SRIO(0..1)_IMSG_QOS_GRP[0:1] hclk hrst_n 956215976Sjmallett */ 957215976Sjmallettunion cvmx_sriox_imsg_qos_grpx 958215976Sjmallett{ 959215976Sjmallett uint64_t u64; 960215976Sjmallett struct cvmx_sriox_imsg_qos_grpx_s 961215976Sjmallett { 962215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 963215976Sjmallett uint64_t reserved_63_63 : 1; 964215976Sjmallett uint64_t qos7 : 3; /**< Entry X:7 QOS (ID=1, LETTER=3) */ 965215976Sjmallett uint64_t grp7 : 4; /**< Entry X:7 GRP (ID=1, LETTER=3) */ 966215976Sjmallett uint64_t reserved_55_55 : 1; 967215976Sjmallett uint64_t qos6 : 3; /**< Entry X:6 QOS (ID=1, LETTER=2) */ 968215976Sjmallett uint64_t grp6 : 4; /**< Entry X:6 GRP (ID=1, LETTER=2) */ 969215976Sjmallett uint64_t reserved_47_47 : 1; 970215976Sjmallett uint64_t qos5 : 3; /**< Entry X:5 QOS (ID=1, LETTER=1) */ 971215976Sjmallett uint64_t grp5 : 4; /**< Entry X:5 GRP (ID=1, LETTER=1) */ 972215976Sjmallett uint64_t reserved_39_39 : 1; 973215976Sjmallett uint64_t qos4 : 3; /**< Entry X:4 QOS (ID=1, LETTER=0) */ 974215976Sjmallett uint64_t grp4 : 4; /**< Entry X:4 GRP (ID=1, LETTER=0) */ 975215976Sjmallett uint64_t reserved_31_31 : 1; 976215976Sjmallett uint64_t qos3 : 3; /**< Entry X:3 QOS (ID=0, LETTER=3) */ 977215976Sjmallett uint64_t grp3 : 4; /**< Entry X:3 GRP (ID=0, LETTER=3) */ 978215976Sjmallett uint64_t reserved_23_23 : 1; 979215976Sjmallett uint64_t qos2 : 3; /**< Entry X:2 QOS (ID=0, LETTER=2) */ 980215976Sjmallett uint64_t grp2 : 4; /**< Entry X:2 GRP (ID=0, LETTER=2) */ 981215976Sjmallett uint64_t reserved_15_15 : 1; 982215976Sjmallett uint64_t qos1 : 3; /**< Entry X:1 QOS (ID=0, LETTER=1) */ 983215976Sjmallett uint64_t grp1 : 4; /**< Entry X:1 GRP (ID=0, LETTER=1) */ 984215976Sjmallett uint64_t reserved_7_7 : 1; 985215976Sjmallett uint64_t qos0 : 3; /**< Entry X:0 QOS (ID=0, LETTER=0) */ 986215976Sjmallett uint64_t grp0 : 4; /**< Entry X:0 GRP (ID=0, LETTER=0) */ 987215976Sjmallett#else 988215976Sjmallett uint64_t grp0 : 4; 989215976Sjmallett uint64_t qos0 : 3; 990215976Sjmallett uint64_t reserved_7_7 : 1; 991215976Sjmallett uint64_t grp1 : 4; 992215976Sjmallett uint64_t qos1 : 3; 993215976Sjmallett uint64_t reserved_15_15 : 1; 994215976Sjmallett uint64_t grp2 : 4; 995215976Sjmallett uint64_t qos2 : 3; 996215976Sjmallett uint64_t reserved_23_23 : 1; 997215976Sjmallett uint64_t grp3 : 4; 998215976Sjmallett uint64_t qos3 : 3; 999215976Sjmallett uint64_t reserved_31_31 : 1; 1000215976Sjmallett uint64_t grp4 : 4; 1001215976Sjmallett uint64_t qos4 : 3; 1002215976Sjmallett uint64_t reserved_39_39 : 1; 1003215976Sjmallett uint64_t grp5 : 4; 1004215976Sjmallett uint64_t qos5 : 3; 1005215976Sjmallett uint64_t reserved_47_47 : 1; 1006215976Sjmallett uint64_t grp6 : 4; 1007215976Sjmallett uint64_t qos6 : 3; 1008215976Sjmallett uint64_t reserved_55_55 : 1; 1009215976Sjmallett uint64_t grp7 : 4; 1010215976Sjmallett uint64_t qos7 : 3; 1011215976Sjmallett uint64_t reserved_63_63 : 1; 1012215976Sjmallett#endif 1013215976Sjmallett } s; 1014215976Sjmallett struct cvmx_sriox_imsg_qos_grpx_s cn63xx; 1015215976Sjmallett struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1; 1016215976Sjmallett}; 1017215976Sjmalletttypedef union cvmx_sriox_imsg_qos_grpx cvmx_sriox_imsg_qos_grpx_t; 1018215976Sjmallett 1019215976Sjmallett/** 1020215976Sjmallett * cvmx_srio#_imsg_status# 1021215976Sjmallett * 1022215976Sjmallett * SRIO_IMSG_STATUSX = SRIO Incoming Message Status Table 1023215976Sjmallett * 1024215976Sjmallett * The SRIO Incoming Message Status Table Entry X 1025215976Sjmallett * 1026215976Sjmallett * Notes: 1027215976Sjmallett * Clk_Rst: SRIO(0..1)_IMSG_STATUS[0:1] hclk hrst_n 1028215976Sjmallett * 1029215976Sjmallett */ 1030215976Sjmallettunion cvmx_sriox_imsg_statusx 1031215976Sjmallett{ 1032215976Sjmallett uint64_t u64; 1033215976Sjmallett struct cvmx_sriox_imsg_statusx_s 1034215976Sjmallett { 1035215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1036215976Sjmallett uint64_t val1 : 1; /**< Entry X:1 Valid */ 1037215976Sjmallett uint64_t err1 : 1; /**< Entry X:1 Error */ 1038215976Sjmallett uint64_t toe1 : 1; /**< Entry X:1 Timeout Error */ 1039215976Sjmallett uint64_t toc1 : 1; /**< Entry X:1 Timeout Count */ 1040215976Sjmallett uint64_t prt1 : 1; /**< Entry X:1 Port */ 1041215976Sjmallett uint64_t reserved_58_58 : 1; 1042215976Sjmallett uint64_t tt1 : 1; /**< Entry X:1 TT ID */ 1043215976Sjmallett uint64_t dis1 : 1; /**< Entry X:1 Dest ID */ 1044215976Sjmallett uint64_t seg1 : 4; /**< Entry X:1 Next Segment */ 1045215976Sjmallett uint64_t mbox1 : 2; /**< Entry X:1 Mailbox */ 1046215976Sjmallett uint64_t lttr1 : 2; /**< Entry X:1 Letter */ 1047215976Sjmallett uint64_t sid1 : 16; /**< Entry X:1 Source ID */ 1048215976Sjmallett uint64_t val0 : 1; /**< Entry X:0 Valid */ 1049215976Sjmallett uint64_t err0 : 1; /**< Entry X:0 Error */ 1050215976Sjmallett uint64_t toe0 : 1; /**< Entry X:0 Timeout Error */ 1051215976Sjmallett uint64_t toc0 : 1; /**< Entry X:0 Timeout Count */ 1052215976Sjmallett uint64_t prt0 : 1; /**< Entry X:0 Port */ 1053215976Sjmallett uint64_t reserved_26_26 : 1; 1054215976Sjmallett uint64_t tt0 : 1; /**< Entry X:0 TT ID */ 1055215976Sjmallett uint64_t dis0 : 1; /**< Entry X:0 Dest ID */ 1056215976Sjmallett uint64_t seg0 : 4; /**< Entry X:0 Next Segment */ 1057215976Sjmallett uint64_t mbox0 : 2; /**< Entry X:0 Mailbox */ 1058215976Sjmallett uint64_t lttr0 : 2; /**< Entry X:0 Letter */ 1059215976Sjmallett uint64_t sid0 : 16; /**< Entry X:0 Source ID */ 1060215976Sjmallett#else 1061215976Sjmallett uint64_t sid0 : 16; 1062215976Sjmallett uint64_t lttr0 : 2; 1063215976Sjmallett uint64_t mbox0 : 2; 1064215976Sjmallett uint64_t seg0 : 4; 1065215976Sjmallett uint64_t dis0 : 1; 1066215976Sjmallett uint64_t tt0 : 1; 1067215976Sjmallett uint64_t reserved_26_26 : 1; 1068215976Sjmallett uint64_t prt0 : 1; 1069215976Sjmallett uint64_t toc0 : 1; 1070215976Sjmallett uint64_t toe0 : 1; 1071215976Sjmallett uint64_t err0 : 1; 1072215976Sjmallett uint64_t val0 : 1; 1073215976Sjmallett uint64_t sid1 : 16; 1074215976Sjmallett uint64_t lttr1 : 2; 1075215976Sjmallett uint64_t mbox1 : 2; 1076215976Sjmallett uint64_t seg1 : 4; 1077215976Sjmallett uint64_t dis1 : 1; 1078215976Sjmallett uint64_t tt1 : 1; 1079215976Sjmallett uint64_t reserved_58_58 : 1; 1080215976Sjmallett uint64_t prt1 : 1; 1081215976Sjmallett uint64_t toc1 : 1; 1082215976Sjmallett uint64_t toe1 : 1; 1083215976Sjmallett uint64_t err1 : 1; 1084215976Sjmallett uint64_t val1 : 1; 1085215976Sjmallett#endif 1086215976Sjmallett } s; 1087215976Sjmallett struct cvmx_sriox_imsg_statusx_s cn63xx; 1088215976Sjmallett struct cvmx_sriox_imsg_statusx_s cn63xxp1; 1089215976Sjmallett}; 1090215976Sjmalletttypedef union cvmx_sriox_imsg_statusx cvmx_sriox_imsg_statusx_t; 1091215976Sjmallett 1092215976Sjmallett/** 1093215976Sjmallett * cvmx_srio#_imsg_vport_thr 1094215976Sjmallett * 1095215976Sjmallett * SRIO_IMSG_VPORT_THR = SRIO Incoming Message Virtual Port Threshold 1096215976Sjmallett * 1097215976Sjmallett * The SRIO Incoming Message Virtual Port Threshold Register 1098215976Sjmallett * 1099215976Sjmallett * Notes: 1100215976Sjmallett * SRIO0_IMSG_VPORT_THR.MAX_TOT must be >= SRIO0_IMSG_VPORT_THR.BUF_THR + SRIO1_IMSG_VPORT_THR.BUF_THR 1101215976Sjmallett * This register can be accessed regardless of the value in SRIO(0..1)_STATUS_REG.ACCESS and is not 1102215976Sjmallett * effected by MAC reset. 1103215976Sjmallett * 1104215976Sjmallett * Clk_Rst: SRIO(0..1)_IMSG_VPORT_THR sclk srst_n 1105215976Sjmallett */ 1106215976Sjmallettunion cvmx_sriox_imsg_vport_thr 1107215976Sjmallett{ 1108215976Sjmallett uint64_t u64; 1109215976Sjmallett struct cvmx_sriox_imsg_vport_thr_s 1110215976Sjmallett { 1111215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1112215976Sjmallett uint64_t reserved_54_63 : 10; 1113215976Sjmallett uint64_t max_tot : 6; /**< Sets max number of vports available to SRIO0+SRIO1 1114215976Sjmallett This field is only used in SRIO0. 1115215976Sjmallett SRIO1 never uses SRIO1_IMSG_VPORT_THR[MAX_TOT]. */ 1116215976Sjmallett uint64_t reserved_46_47 : 2; 1117215976Sjmallett uint64_t max_s1 : 6; /**< Sets max number of vports available to SRIO1 1118215976Sjmallett This field is only used in SRIO0. 1119215976Sjmallett SRIO1 never uses SRIO1_IMSG_VPORT_THR[MAX_S1]. */ 1120215976Sjmallett uint64_t reserved_38_39 : 2; 1121215976Sjmallett uint64_t max_s0 : 6; /**< Sets max number of vports available to SRIO0 1122215976Sjmallett This field is only used in SRIO0. 1123215976Sjmallett SRIO1 never uses SRIO1_IMSG_VPORT_THR[MAX_S0]. */ 1124215976Sjmallett uint64_t sp_vport : 1; /**< Single-segment vport pre-allocation. 1125215976Sjmallett When set, single-segment messages use pre-allocated 1126215976Sjmallett vport slots (that do not count toward thresholds). 1127215976Sjmallett When clear, single-segment messages must allocate 1128215976Sjmallett vport slots just like multi-segment messages do. */ 1129215976Sjmallett uint64_t reserved_20_30 : 11; 1130215976Sjmallett uint64_t buf_thr : 4; /**< Sets number of vports to be buffered by this 1131215976Sjmallett interface. BUF_THR must not be zero when receiving 1132215976Sjmallett messages. The max BUF_THR value is 8. 1133215976Sjmallett Recommend BUF_THR values 1-4. If the 46 available 1134215976Sjmallett vports are not statically-allocated across the two 1135215976Sjmallett SRIO's, smaller BUF_THR values may leave more 1136215976Sjmallett vports available for the other SRIO. Lack of a 1137215976Sjmallett buffered vport can force a retry for a received 1138215976Sjmallett first segment, so, particularly if SP_VPORT=0 1139215976Sjmallett (which is not recommended) or the segment size is 1140215976Sjmallett small, larger BUF_THR values may improve 1141215976Sjmallett performance. */ 1142215976Sjmallett uint64_t reserved_14_15 : 2; 1143215976Sjmallett uint64_t max_p1 : 6; /**< Sets max number of open vports in port 1 */ 1144215976Sjmallett uint64_t reserved_6_7 : 2; 1145215976Sjmallett uint64_t max_p0 : 6; /**< Sets max number of open vports in port 0 */ 1146215976Sjmallett#else 1147215976Sjmallett uint64_t max_p0 : 6; 1148215976Sjmallett uint64_t reserved_6_7 : 2; 1149215976Sjmallett uint64_t max_p1 : 6; 1150215976Sjmallett uint64_t reserved_14_15 : 2; 1151215976Sjmallett uint64_t buf_thr : 4; 1152215976Sjmallett uint64_t reserved_20_30 : 11; 1153215976Sjmallett uint64_t sp_vport : 1; 1154215976Sjmallett uint64_t max_s0 : 6; 1155215976Sjmallett uint64_t reserved_38_39 : 2; 1156215976Sjmallett uint64_t max_s1 : 6; 1157215976Sjmallett uint64_t reserved_46_47 : 2; 1158215976Sjmallett uint64_t max_tot : 6; 1159215976Sjmallett uint64_t reserved_54_63 : 10; 1160215976Sjmallett#endif 1161215976Sjmallett } s; 1162215976Sjmallett struct cvmx_sriox_imsg_vport_thr_s cn63xx; 1163215976Sjmallett struct cvmx_sriox_imsg_vport_thr_s cn63xxp1; 1164215976Sjmallett}; 1165215976Sjmalletttypedef union cvmx_sriox_imsg_vport_thr cvmx_sriox_imsg_vport_thr_t; 1166215976Sjmallett 1167215976Sjmallett/** 1168215976Sjmallett * cvmx_srio#_int2_enable 1169215976Sjmallett * 1170215976Sjmallett * SRIO_INT2_ENABLE = SRIO Interrupt 2 Enable (Pass 2) 1171215976Sjmallett * 1172215976Sjmallett * Allows SRIO to generate additional interrupts when corresponding enable bit is set. 1173215976Sjmallett * 1174215976Sjmallett * Notes: 1175215976Sjmallett * This register enables interrupts in SRIO(0..1)_INT2_REG that can be asserted while the MAC is in reset. 1176215976Sjmallett * The register can be accessed/modified regardless of the value of SRIO(0..1)_STATUS_REG.ACCESS. 1177215976Sjmallett * 1178215976Sjmallett * Clk_Rst: SRIO(0..1)_INT2_ENABLE sclk srst_n 1179215976Sjmallett */ 1180215976Sjmallettunion cvmx_sriox_int2_enable 1181215976Sjmallett{ 1182215976Sjmallett uint64_t u64; 1183215976Sjmallett struct cvmx_sriox_int2_enable_s 1184215976Sjmallett { 1185215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1186215976Sjmallett uint64_t reserved_1_63 : 63; 1187215976Sjmallett uint64_t pko_rst : 1; /**< PKO Reset Error Enable */ 1188215976Sjmallett#else 1189215976Sjmallett uint64_t pko_rst : 1; 1190215976Sjmallett uint64_t reserved_1_63 : 63; 1191215976Sjmallett#endif 1192215976Sjmallett } s; 1193215976Sjmallett struct cvmx_sriox_int2_enable_s cn63xx; 1194215976Sjmallett}; 1195215976Sjmalletttypedef union cvmx_sriox_int2_enable cvmx_sriox_int2_enable_t; 1196215976Sjmallett 1197215976Sjmallett/** 1198215976Sjmallett * cvmx_srio#_int2_reg 1199215976Sjmallett * 1200215976Sjmallett * SRIO_INT2_REG = SRIO Interrupt 2 Register (Pass 2) 1201215976Sjmallett * 1202215976Sjmallett * Displays and clears which enabled interrupts have occured 1203215976Sjmallett * 1204215976Sjmallett * Notes: 1205215976Sjmallett * This register provides interrupt status. Unlike SRIO*_INT_REG, SRIO*_INT2_REG can be accessed 1206215976Sjmallett * whenever the SRIO is present, regardless of whether the corresponding SRIO is in reset or not. 1207215976Sjmallett * INT_SUM shows the status of the interrupts in SRIO(0..1)_INT_REG. Any set bits written to this 1208215976Sjmallett * register clear the corresponding interrupt. The register can be accessed/modified regardless of 1209215976Sjmallett * the value of SRIO(0..1)_STATUS_REG.ACCESS and probably should be the first register read when an SRIO 1210215976Sjmallett * interrupt occurs. 1211215976Sjmallett * 1212215976Sjmallett * Clk_Rst: SRIO(0..1)_INT2_REG sclk srst_n 1213215976Sjmallett */ 1214215976Sjmallettunion cvmx_sriox_int2_reg 1215215976Sjmallett{ 1216215976Sjmallett uint64_t u64; 1217215976Sjmallett struct cvmx_sriox_int2_reg_s 1218215976Sjmallett { 1219215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1220215976Sjmallett uint64_t reserved_32_63 : 32; 1221215976Sjmallett uint64_t int_sum : 1; /**< Interrupt Set and Enabled in SRIO(0..1)_INT_REG */ 1222215976Sjmallett uint64_t reserved_1_30 : 30; 1223215976Sjmallett uint64_t pko_rst : 1; /**< PKO Reset Error - Message Received from PKO while 1224215976Sjmallett MAC in reset. */ 1225215976Sjmallett#else 1226215976Sjmallett uint64_t pko_rst : 1; 1227215976Sjmallett uint64_t reserved_1_30 : 30; 1228215976Sjmallett uint64_t int_sum : 1; 1229215976Sjmallett uint64_t reserved_32_63 : 32; 1230215976Sjmallett#endif 1231215976Sjmallett } s; 1232215976Sjmallett struct cvmx_sriox_int2_reg_s cn63xx; 1233215976Sjmallett}; 1234215976Sjmalletttypedef union cvmx_sriox_int2_reg cvmx_sriox_int2_reg_t; 1235215976Sjmallett 1236215976Sjmallett/** 1237215976Sjmallett * cvmx_srio#_int_enable 1238215976Sjmallett * 1239215976Sjmallett * SRIO_INT_ENABLE = SRIO Interrupt Enable 1240215976Sjmallett * 1241215976Sjmallett * Allows SRIO to generate interrupts when corresponding enable bit is set. 1242215976Sjmallett * 1243215976Sjmallett * Notes: 1244215976Sjmallett * This register enables interrupts. 1245215976Sjmallett * 1246215976Sjmallett * Clk_Rst: SRIO(0..1)_INT_ENABLE hclk hrst_n 1247215976Sjmallett */ 1248215976Sjmallettunion cvmx_sriox_int_enable 1249215976Sjmallett{ 1250215976Sjmallett uint64_t u64; 1251215976Sjmallett struct cvmx_sriox_int_enable_s 1252215976Sjmallett { 1253215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1254215976Sjmallett uint64_t reserved_26_63 : 38; 1255215976Sjmallett uint64_t ttl_tout : 1; /**< Outgoing Packet Time to Live Timeout (Pass 2) */ 1256215976Sjmallett uint64_t fail : 1; /**< ERB Error Rate reached Fail Count (Pass 2) */ 1257215976Sjmallett uint64_t degrade : 1; /**< ERB Error Rate reached Degrade Count (Pass 2) */ 1258215976Sjmallett uint64_t mac_buf : 1; /**< SRIO MAC Buffer CRC Error (Pass 2) */ 1259215976Sjmallett uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */ 1260215976Sjmallett uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded */ 1261215976Sjmallett uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */ 1262215976Sjmallett uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error */ 1263215976Sjmallett uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */ 1264215976Sjmallett uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */ 1265215976Sjmallett uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */ 1266215976Sjmallett uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */ 1267215976Sjmallett uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB */ 1268215976Sjmallett uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB */ 1269215976Sjmallett uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */ 1270215976Sjmallett uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */ 1271215976Sjmallett uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */ 1272215976Sjmallett uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */ 1273215976Sjmallett uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */ 1274215976Sjmallett uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. */ 1275215976Sjmallett uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */ 1276215976Sjmallett uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */ 1277215976Sjmallett uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. */ 1278215976Sjmallett uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. */ 1279215976Sjmallett uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. */ 1280215976Sjmallett uint64_t txbell : 1; /**< Outgoing Doorbell Complete. */ 1281215976Sjmallett#else 1282215976Sjmallett uint64_t txbell : 1; 1283215976Sjmallett uint64_t bell_err : 1; 1284215976Sjmallett uint64_t rxbell : 1; 1285215976Sjmallett uint64_t maint_op : 1; 1286215976Sjmallett uint64_t bar_err : 1; 1287215976Sjmallett uint64_t deny_wr : 1; 1288215976Sjmallett uint64_t sli_err : 1; 1289215976Sjmallett uint64_t wr_done : 1; 1290215976Sjmallett uint64_t mce_tx : 1; 1291215976Sjmallett uint64_t mce_rx : 1; 1292215976Sjmallett uint64_t soft_tx : 1; 1293215976Sjmallett uint64_t soft_rx : 1; 1294215976Sjmallett uint64_t log_erb : 1; 1295215976Sjmallett uint64_t phy_erb : 1; 1296215976Sjmallett uint64_t link_dwn : 1; 1297215976Sjmallett uint64_t link_up : 1; 1298215976Sjmallett uint64_t omsg0 : 1; 1299215976Sjmallett uint64_t omsg1 : 1; 1300215976Sjmallett uint64_t omsg_err : 1; 1301215976Sjmallett uint64_t pko_err : 1; 1302215976Sjmallett uint64_t rtry_err : 1; 1303215976Sjmallett uint64_t f_error : 1; 1304215976Sjmallett uint64_t mac_buf : 1; 1305215976Sjmallett uint64_t degrade : 1; 1306215976Sjmallett uint64_t fail : 1; 1307215976Sjmallett uint64_t ttl_tout : 1; 1308215976Sjmallett uint64_t reserved_26_63 : 38; 1309215976Sjmallett#endif 1310215976Sjmallett } s; 1311215976Sjmallett struct cvmx_sriox_int_enable_s cn63xx; 1312215976Sjmallett struct cvmx_sriox_int_enable_cn63xxp1 1313215976Sjmallett { 1314215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1315215976Sjmallett uint64_t reserved_22_63 : 42; 1316215976Sjmallett uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */ 1317215976Sjmallett uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded */ 1318215976Sjmallett uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */ 1319215976Sjmallett uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error */ 1320215976Sjmallett uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */ 1321215976Sjmallett uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */ 1322215976Sjmallett uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */ 1323215976Sjmallett uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */ 1324215976Sjmallett uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB */ 1325215976Sjmallett uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB */ 1326215976Sjmallett uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */ 1327215976Sjmallett uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */ 1328215976Sjmallett uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */ 1329215976Sjmallett uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */ 1330215976Sjmallett uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */ 1331215976Sjmallett uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. */ 1332215976Sjmallett uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */ 1333215976Sjmallett uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */ 1334215976Sjmallett uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. */ 1335215976Sjmallett uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. */ 1336215976Sjmallett uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. */ 1337215976Sjmallett uint64_t txbell : 1; /**< Outgoing Doorbell Complete. */ 1338215976Sjmallett#else 1339215976Sjmallett uint64_t txbell : 1; 1340215976Sjmallett uint64_t bell_err : 1; 1341215976Sjmallett uint64_t rxbell : 1; 1342215976Sjmallett uint64_t maint_op : 1; 1343215976Sjmallett uint64_t bar_err : 1; 1344215976Sjmallett uint64_t deny_wr : 1; 1345215976Sjmallett uint64_t sli_err : 1; 1346215976Sjmallett uint64_t wr_done : 1; 1347215976Sjmallett uint64_t mce_tx : 1; 1348215976Sjmallett uint64_t mce_rx : 1; 1349215976Sjmallett uint64_t soft_tx : 1; 1350215976Sjmallett uint64_t soft_rx : 1; 1351215976Sjmallett uint64_t log_erb : 1; 1352215976Sjmallett uint64_t phy_erb : 1; 1353215976Sjmallett uint64_t link_dwn : 1; 1354215976Sjmallett uint64_t link_up : 1; 1355215976Sjmallett uint64_t omsg0 : 1; 1356215976Sjmallett uint64_t omsg1 : 1; 1357215976Sjmallett uint64_t omsg_err : 1; 1358215976Sjmallett uint64_t pko_err : 1; 1359215976Sjmallett uint64_t rtry_err : 1; 1360215976Sjmallett uint64_t f_error : 1; 1361215976Sjmallett uint64_t reserved_22_63 : 42; 1362215976Sjmallett#endif 1363215976Sjmallett } cn63xxp1; 1364215976Sjmallett}; 1365215976Sjmalletttypedef union cvmx_sriox_int_enable cvmx_sriox_int_enable_t; 1366215976Sjmallett 1367215976Sjmallett/** 1368215976Sjmallett * cvmx_srio#_int_info0 1369215976Sjmallett * 1370215976Sjmallett * SRIO_INT_INFO0 = SRIO Interrupt Information 1371215976Sjmallett * 1372215976Sjmallett * The SRIO Interrupt Information 1373215976Sjmallett * 1374215976Sjmallett * Notes: 1375215976Sjmallett * This register contains the first header word of the illegal s2m transaction associated with the 1376215976Sjmallett * SLI_ERR interrupt. The remaining information is located in SRIO(0..1)_INT_INFO1. This register is 1377215976Sjmallett * only updated when the SLI_ERR is initially detected. Once the interrupt is cleared then 1378215976Sjmallett * additional information can be captured. 1379215976Sjmallett * Common Errors Include: 1380215976Sjmallett * 1. Load/Stores with Length over 32 1381215976Sjmallett * 2. Load/Stores that translate to Maintenance Ops with a length over 8 1382215976Sjmallett * 3. Load Ops that translate to Atomic Ops with other than 1, 2 and 4 byte accesses 1383215976Sjmallett * 4. Load/Store Ops with a Length 0 1384215976Sjmallett * 5. Unexpected Responses 1385215976Sjmallett * 1386215976Sjmallett * Clk_Rst: SRIO(0..1)_INT_REG hclk hrst_n 1387215976Sjmallett */ 1388215976Sjmallettunion cvmx_sriox_int_info0 1389215976Sjmallett{ 1390215976Sjmallett uint64_t u64; 1391215976Sjmallett struct cvmx_sriox_int_info0_s 1392215976Sjmallett { 1393215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1394215976Sjmallett uint64_t cmd : 4; /**< Command 1395215976Sjmallett 0 = Load, Outgoing Read Request 1396215976Sjmallett 4 = Store, Outgoing Write Request 1397215976Sjmallett 8 = Response, Outgoing Read Response 1398215976Sjmallett All Others are reserved and generate errors */ 1399215976Sjmallett uint64_t type : 4; /**< Command Type 1400215976Sjmallett Load/Store SRIO_S2M_TYPE used 1401215976Sjmallett Response (Reserved) */ 1402215976Sjmallett uint64_t tag : 8; /**< Internal Transaction Number */ 1403215976Sjmallett uint64_t reserved_42_47 : 6; 1404215976Sjmallett uint64_t length : 10; /**< Data Length in 64-bit Words (Load/Store Only) */ 1405215976Sjmallett uint64_t status : 3; /**< Response Status 1406215976Sjmallett 0 = Success 1407215976Sjmallett 1 = Error 1408215976Sjmallett All others reserved */ 1409215976Sjmallett uint64_t reserved_16_28 : 13; 1410215976Sjmallett uint64_t be0 : 8; /**< First 64-bit Word Byte Enables (Load/Store Only) */ 1411215976Sjmallett uint64_t be1 : 8; /**< Last 64-bit Word Byte Enables (Load/Store Only) */ 1412215976Sjmallett#else 1413215976Sjmallett uint64_t be1 : 8; 1414215976Sjmallett uint64_t be0 : 8; 1415215976Sjmallett uint64_t reserved_16_28 : 13; 1416215976Sjmallett uint64_t status : 3; 1417215976Sjmallett uint64_t length : 10; 1418215976Sjmallett uint64_t reserved_42_47 : 6; 1419215976Sjmallett uint64_t tag : 8; 1420215976Sjmallett uint64_t type : 4; 1421215976Sjmallett uint64_t cmd : 4; 1422215976Sjmallett#endif 1423215976Sjmallett } s; 1424215976Sjmallett struct cvmx_sriox_int_info0_s cn63xx; 1425215976Sjmallett struct cvmx_sriox_int_info0_s cn63xxp1; 1426215976Sjmallett}; 1427215976Sjmalletttypedef union cvmx_sriox_int_info0 cvmx_sriox_int_info0_t; 1428215976Sjmallett 1429215976Sjmallett/** 1430215976Sjmallett * cvmx_srio#_int_info1 1431215976Sjmallett * 1432215976Sjmallett * SRIO_INT_INFO1 = SRIO Interrupt Information 1433215976Sjmallett * 1434215976Sjmallett * The SRIO Interrupt Information 1435215976Sjmallett * 1436215976Sjmallett * Notes: 1437215976Sjmallett * This register contains the second header word of the illegal s2m transaction associated with the 1438215976Sjmallett * SLI_ERR interrupt. The remaining information is located in SRIO(0..1)_INT_INFO0. This register is 1439215976Sjmallett * only updated when the SLI_ERR is initially detected. Once the interrupt is cleared then 1440215976Sjmallett * additional information can be captured. 1441215976Sjmallett * 1442215976Sjmallett * Clk_Rst: SRIO(0..1)_INT_REG hclk hrst_n 1443215976Sjmallett */ 1444215976Sjmallettunion cvmx_sriox_int_info1 1445215976Sjmallett{ 1446215976Sjmallett uint64_t u64; 1447215976Sjmallett struct cvmx_sriox_int_info1_s 1448215976Sjmallett { 1449215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1450215976Sjmallett uint64_t info1 : 64; /**< Address (Load/Store) or First 64-bit Word of 1451215976Sjmallett Response Data Associated with Interrupt */ 1452215976Sjmallett#else 1453215976Sjmallett uint64_t info1 : 64; 1454215976Sjmallett#endif 1455215976Sjmallett } s; 1456215976Sjmallett struct cvmx_sriox_int_info1_s cn63xx; 1457215976Sjmallett struct cvmx_sriox_int_info1_s cn63xxp1; 1458215976Sjmallett}; 1459215976Sjmalletttypedef union cvmx_sriox_int_info1 cvmx_sriox_int_info1_t; 1460215976Sjmallett 1461215976Sjmallett/** 1462215976Sjmallett * cvmx_srio#_int_info2 1463215976Sjmallett * 1464215976Sjmallett * SRIO_INT_INFO2 = SRIO Interrupt Information 1465215976Sjmallett * 1466215976Sjmallett * The SRIO Interrupt Information 1467215976Sjmallett * 1468215976Sjmallett * Notes: 1469215976Sjmallett * This register contains the invalid outbound message descriptor associated with the OMSG_ERR 1470215976Sjmallett * interrupt. This register is only updated when the OMSG_ERR is initially detected. Once the 1471215976Sjmallett * interrupt is cleared then additional information can be captured. 1472215976Sjmallett * 1473215976Sjmallett * Clk_Rst: SRIO(0..1)_INT_REG hclk hrst_n 1474215976Sjmallett */ 1475215976Sjmallettunion cvmx_sriox_int_info2 1476215976Sjmallett{ 1477215976Sjmallett uint64_t u64; 1478215976Sjmallett struct cvmx_sriox_int_info2_s 1479215976Sjmallett { 1480215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1481215976Sjmallett uint64_t prio : 2; /**< PRIO field of outbound message descriptor 1482215976Sjmallett associated with the OMSG_ERR interrupt */ 1483215976Sjmallett uint64_t tt : 1; /**< TT field of outbound message descriptor 1484215976Sjmallett associated with the OMSG_ERR interrupt */ 1485215976Sjmallett uint64_t sis : 1; /**< SIS field of outbound message descriptor 1486215976Sjmallett associated with the OMSG_ERR interrupt */ 1487215976Sjmallett uint64_t ssize : 4; /**< SSIZE field of outbound message descriptor 1488215976Sjmallett associated with the OMSG_ERR interrupt */ 1489215976Sjmallett uint64_t did : 16; /**< DID field of outbound message descriptor 1490215976Sjmallett associated with the OMSG_ERR interrupt */ 1491215976Sjmallett uint64_t xmbox : 4; /**< XMBOX field of outbound message descriptor 1492215976Sjmallett associated with the OMSG_ERR interrupt */ 1493215976Sjmallett uint64_t mbox : 2; /**< MBOX field of outbound message descriptor 1494215976Sjmallett associated with the OMSG_ERR interrupt */ 1495215976Sjmallett uint64_t letter : 2; /**< LETTER field of outbound message descriptor 1496215976Sjmallett associated with the OMSG_ERR interrupt */ 1497215976Sjmallett uint64_t rsrvd : 30; /**< RSRVD field of outbound message descriptor 1498215976Sjmallett associated with the OMSG_ERR interrupt */ 1499215976Sjmallett uint64_t lns : 1; /**< LNS field of outbound message descriptor 1500215976Sjmallett associated with the OMSG_ERR interrupt */ 1501215976Sjmallett uint64_t intr : 1; /**< INT field of outbound message descriptor 1502215976Sjmallett associated with the OMSG_ERR interrupt */ 1503215976Sjmallett#else 1504215976Sjmallett uint64_t intr : 1; 1505215976Sjmallett uint64_t lns : 1; 1506215976Sjmallett uint64_t rsrvd : 30; 1507215976Sjmallett uint64_t letter : 2; 1508215976Sjmallett uint64_t mbox : 2; 1509215976Sjmallett uint64_t xmbox : 4; 1510215976Sjmallett uint64_t did : 16; 1511215976Sjmallett uint64_t ssize : 4; 1512215976Sjmallett uint64_t sis : 1; 1513215976Sjmallett uint64_t tt : 1; 1514215976Sjmallett uint64_t prio : 2; 1515215976Sjmallett#endif 1516215976Sjmallett } s; 1517215976Sjmallett struct cvmx_sriox_int_info2_s cn63xx; 1518215976Sjmallett struct cvmx_sriox_int_info2_s cn63xxp1; 1519215976Sjmallett}; 1520215976Sjmalletttypedef union cvmx_sriox_int_info2 cvmx_sriox_int_info2_t; 1521215976Sjmallett 1522215976Sjmallett/** 1523215976Sjmallett * cvmx_srio#_int_info3 1524215976Sjmallett * 1525215976Sjmallett * SRIO_INT_INFO3 = SRIO Interrupt Information 1526215976Sjmallett * 1527215976Sjmallett * The SRIO Interrupt Information 1528215976Sjmallett * 1529215976Sjmallett * Notes: 1530215976Sjmallett * This register contains the retry response associated with the RTRY_ERR interrupt. This register 1531215976Sjmallett * is only updated when the RTRY_ERR is initially detected. Once the interrupt is cleared then 1532215976Sjmallett * additional information can be captured. 1533215976Sjmallett * 1534215976Sjmallett * Clk_Rst: SRIO(0..1)_INT_REG hclk hrst_n 1535215976Sjmallett */ 1536215976Sjmallettunion cvmx_sriox_int_info3 1537215976Sjmallett{ 1538215976Sjmallett uint64_t u64; 1539215976Sjmallett struct cvmx_sriox_int_info3_s 1540215976Sjmallett { 1541215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1542215976Sjmallett uint64_t prio : 2; /**< Priority of received retry response message */ 1543215976Sjmallett uint64_t tt : 2; /**< TT of received retry response message */ 1544215976Sjmallett uint64_t type : 4; /**< Type of received retry response message 1545215976Sjmallett (should be 13) */ 1546215976Sjmallett uint64_t other : 48; /**< Other fields of received retry response message 1547215976Sjmallett If TT==0 (8-bit ID's) 1548215976Sjmallett OTHER<47:40> => destination ID 1549215976Sjmallett OTHER<39:32> => source ID 1550215976Sjmallett OTHER<31:28> => transaction (should be 1 - msg) 1551215976Sjmallett OTHER<27:24> => status (should be 3 - retry) 1552215976Sjmallett OTHER<23:22> => letter 1553215976Sjmallett OTHER<21:20> => mbox 1554215976Sjmallett OTHER<19:16> => msgseg 1555215976Sjmallett OTHER<15:0> => unused 1556215976Sjmallett If TT==1 (16-bit ID's) 1557215976Sjmallett OTHER<47:32> => destination ID 1558215976Sjmallett OTHER<31:16> => source ID 1559215976Sjmallett OTHER<15:12> => transaction (should be 1 - msg) 1560215976Sjmallett OTHER<11:8> => status (should be 3 - retry) 1561215976Sjmallett OTHER<7:6> => letter 1562215976Sjmallett OTHER<5:4> => mbox 1563215976Sjmallett OTHER<3:0> => msgseg */ 1564215976Sjmallett uint64_t reserved_0_7 : 8; 1565215976Sjmallett#else 1566215976Sjmallett uint64_t reserved_0_7 : 8; 1567215976Sjmallett uint64_t other : 48; 1568215976Sjmallett uint64_t type : 4; 1569215976Sjmallett uint64_t tt : 2; 1570215976Sjmallett uint64_t prio : 2; 1571215976Sjmallett#endif 1572215976Sjmallett } s; 1573215976Sjmallett struct cvmx_sriox_int_info3_s cn63xx; 1574215976Sjmallett struct cvmx_sriox_int_info3_s cn63xxp1; 1575215976Sjmallett}; 1576215976Sjmalletttypedef union cvmx_sriox_int_info3 cvmx_sriox_int_info3_t; 1577215976Sjmallett 1578215976Sjmallett/** 1579215976Sjmallett * cvmx_srio#_int_reg 1580215976Sjmallett * 1581215976Sjmallett * SRIO_INT_REG = SRIO Interrupt Register 1582215976Sjmallett * 1583215976Sjmallett * Displays and clears which enabled interrupts have occured 1584215976Sjmallett * 1585215976Sjmallett * Notes: 1586215976Sjmallett * This register provides interrupt status. Like most SRIO CSRs, this register can only 1587215976Sjmallett * be read/written when the corresponding SRIO is both present and not in reset. (SRIO*_INT2_REG 1588215976Sjmallett * can be accessed when SRIO is in reset.) Any set bits written to this register clear the 1589215976Sjmallett * corresponding interrupt. The RXBELL interrupt is cleared by reading all the entries in the 1590215976Sjmallett * incoming Doorbell FIFO. The LOG_ERB interrupt must be cleared before writing zeroes 1591215976Sjmallett * to clear the bits in the SRIOMAINT*_ERB_LT_ERR_DET register. Otherwise a new interrupt may be 1592215976Sjmallett * lost. The PHY_ERB interrupt must be cleared before writing a zero to 1593215976Sjmallett * SRIOMAINT*_ERB_ATTR_CAPT[VALID]. Otherwise, a new interrupt may be lost. OMSG_ERR is set when an 1594215976Sjmallett * invalid outbound message descriptor is received. The descriptor is deemed to be invalid if the 1595215976Sjmallett * SSIZE field is set to a reserved value, the SSIZE field combined with the packet length would 1596215976Sjmallett * result in more than 16 message segments, or the packet only contains a descriptor (no data). 1597215976Sjmallett * 1598215976Sjmallett * Clk_Rst: SRIO(0..1)_INT_REG hclk hrst_n 1599215976Sjmallett */ 1600215976Sjmallettunion cvmx_sriox_int_reg 1601215976Sjmallett{ 1602215976Sjmallett uint64_t u64; 1603215976Sjmallett struct cvmx_sriox_int_reg_s 1604215976Sjmallett { 1605215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1606215976Sjmallett uint64_t reserved_32_63 : 32; 1607215976Sjmallett uint64_t int2_sum : 1; /**< Interrupt Set and Enabled in SRIO(0..1)_INT2_REG 1608215976Sjmallett (Pass 2) */ 1609215976Sjmallett uint64_t reserved_26_30 : 5; 1610215976Sjmallett uint64_t ttl_tout : 1; /**< Outgoing Packet Time to Live Timeout (Pass 2) 1611215976Sjmallett See SRIOMAINT(0..1)_DROP_PACKET */ 1612215976Sjmallett uint64_t fail : 1; /**< ERB Error Rate reached Fail Count (Pass 2) 1613215976Sjmallett See SRIOMAINT(0..1)_ERB_ERR_RATE */ 1614215976Sjmallett uint64_t degrad : 1; /**< ERB Error Rate reached Degrade Count (Pass 2) 1615215976Sjmallett See SRIOMAINT(0..1)_ERB_ERR_RATE */ 1616215976Sjmallett uint64_t mac_buf : 1; /**< SRIO MAC Buffer CRC Error (Pass 2) 1617215976Sjmallett See SRIO(0..1)_MAC_BUFFERS */ 1618215976Sjmallett uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */ 1619215976Sjmallett uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded 1620215976Sjmallett See SRIO(0..1)_INT_INFO3 1621215976Sjmallett When one or more of the segments in an outgoing 1622215976Sjmallett message have a RTRY_ERR, SRIO will not set 1623215976Sjmallett OMSG* after the message "transfer". */ 1624215976Sjmallett uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */ 1625215976Sjmallett uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error 1626215976Sjmallett See SRIO(0..1)_INT_INFO2 */ 1627215976Sjmallett uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */ 1628215976Sjmallett uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */ 1629215976Sjmallett uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */ 1630215976Sjmallett uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */ 1631215976Sjmallett uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB 1632215976Sjmallett See SRIOMAINT*_ERB_ATTR_CAPT */ 1633215976Sjmallett uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB 1634215976Sjmallett See SRIOMAINT(0..1)_ERB_LT_ERR_DET */ 1635215976Sjmallett uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */ 1636215976Sjmallett uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */ 1637215976Sjmallett uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */ 1638215976Sjmallett uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */ 1639215976Sjmallett uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */ 1640215976Sjmallett uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. 1641215976Sjmallett See SRIO(0..1)_INT_INFO[1:0] */ 1642215976Sjmallett uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */ 1643215976Sjmallett uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */ 1644215976Sjmallett uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. 1645215976Sjmallett See SRIO(0..1)_MAINT_OP and SRIO(0..1)_MAINT_RD_DATA */ 1646215976Sjmallett uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. 1647215976Sjmallett Read SRIO(0..1)_RX_BELL to empty FIFO */ 1648215976Sjmallett uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. 1649215976Sjmallett See SRIO(0..1)_TX_BELL_INFO */ 1650215976Sjmallett uint64_t txbell : 1; /**< Outgoing Doorbell Complete. 1651215976Sjmallett TXBELL will not be asserted if a Timeout, Retry or 1652215976Sjmallett Error occurs. */ 1653215976Sjmallett#else 1654215976Sjmallett uint64_t txbell : 1; 1655215976Sjmallett uint64_t bell_err : 1; 1656215976Sjmallett uint64_t rxbell : 1; 1657215976Sjmallett uint64_t maint_op : 1; 1658215976Sjmallett uint64_t bar_err : 1; 1659215976Sjmallett uint64_t deny_wr : 1; 1660215976Sjmallett uint64_t sli_err : 1; 1661215976Sjmallett uint64_t wr_done : 1; 1662215976Sjmallett uint64_t mce_tx : 1; 1663215976Sjmallett uint64_t mce_rx : 1; 1664215976Sjmallett uint64_t soft_tx : 1; 1665215976Sjmallett uint64_t soft_rx : 1; 1666215976Sjmallett uint64_t log_erb : 1; 1667215976Sjmallett uint64_t phy_erb : 1; 1668215976Sjmallett uint64_t link_dwn : 1; 1669215976Sjmallett uint64_t link_up : 1; 1670215976Sjmallett uint64_t omsg0 : 1; 1671215976Sjmallett uint64_t omsg1 : 1; 1672215976Sjmallett uint64_t omsg_err : 1; 1673215976Sjmallett uint64_t pko_err : 1; 1674215976Sjmallett uint64_t rtry_err : 1; 1675215976Sjmallett uint64_t f_error : 1; 1676215976Sjmallett uint64_t mac_buf : 1; 1677215976Sjmallett uint64_t degrad : 1; 1678215976Sjmallett uint64_t fail : 1; 1679215976Sjmallett uint64_t ttl_tout : 1; 1680215976Sjmallett uint64_t reserved_26_30 : 5; 1681215976Sjmallett uint64_t int2_sum : 1; 1682215976Sjmallett uint64_t reserved_32_63 : 32; 1683215976Sjmallett#endif 1684215976Sjmallett } s; 1685215976Sjmallett struct cvmx_sriox_int_reg_s cn63xx; 1686215976Sjmallett struct cvmx_sriox_int_reg_cn63xxp1 1687215976Sjmallett { 1688215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1689215976Sjmallett uint64_t reserved_22_63 : 42; 1690215976Sjmallett uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */ 1691215976Sjmallett uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded 1692215976Sjmallett See SRIO(0..1)_INT_INFO3 1693215976Sjmallett When one or more of the segments in an outgoing 1694215976Sjmallett message have a RTRY_ERR, SRIO will not set 1695215976Sjmallett OMSG* after the message "transfer". */ 1696215976Sjmallett uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */ 1697215976Sjmallett uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error 1698215976Sjmallett See SRIO(0..1)_INT_INFO2 */ 1699215976Sjmallett uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */ 1700215976Sjmallett uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */ 1701215976Sjmallett uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */ 1702215976Sjmallett uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */ 1703215976Sjmallett uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB 1704215976Sjmallett See SRIOMAINT*_ERB_ATTR_CAPT */ 1705215976Sjmallett uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB 1706215976Sjmallett See SRIOMAINT(0..1)_ERB_LT_ERR_DET */ 1707215976Sjmallett uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */ 1708215976Sjmallett uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */ 1709215976Sjmallett uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */ 1710215976Sjmallett uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */ 1711215976Sjmallett uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */ 1712215976Sjmallett uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. 1713215976Sjmallett See SRIO(0..1)_INT_INFO[1:0] */ 1714215976Sjmallett uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */ 1715215976Sjmallett uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */ 1716215976Sjmallett uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. 1717215976Sjmallett See SRIO(0..1)_MAINT_OP and SRIO(0..1)_MAINT_RD_DATA */ 1718215976Sjmallett uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. 1719215976Sjmallett Read SRIO(0..1)_RX_BELL to empty FIFO */ 1720215976Sjmallett uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. 1721215976Sjmallett See SRIO(0..1)_TX_BELL_INFO */ 1722215976Sjmallett uint64_t txbell : 1; /**< Outgoing Doorbell Complete. 1723215976Sjmallett TXBELL will not be asserted if a Timeout, Retry or 1724215976Sjmallett Error occurs. */ 1725215976Sjmallett#else 1726215976Sjmallett uint64_t txbell : 1; 1727215976Sjmallett uint64_t bell_err : 1; 1728215976Sjmallett uint64_t rxbell : 1; 1729215976Sjmallett uint64_t maint_op : 1; 1730215976Sjmallett uint64_t bar_err : 1; 1731215976Sjmallett uint64_t deny_wr : 1; 1732215976Sjmallett uint64_t sli_err : 1; 1733215976Sjmallett uint64_t wr_done : 1; 1734215976Sjmallett uint64_t mce_tx : 1; 1735215976Sjmallett uint64_t mce_rx : 1; 1736215976Sjmallett uint64_t soft_tx : 1; 1737215976Sjmallett uint64_t soft_rx : 1; 1738215976Sjmallett uint64_t log_erb : 1; 1739215976Sjmallett uint64_t phy_erb : 1; 1740215976Sjmallett uint64_t link_dwn : 1; 1741215976Sjmallett uint64_t link_up : 1; 1742215976Sjmallett uint64_t omsg0 : 1; 1743215976Sjmallett uint64_t omsg1 : 1; 1744215976Sjmallett uint64_t omsg_err : 1; 1745215976Sjmallett uint64_t pko_err : 1; 1746215976Sjmallett uint64_t rtry_err : 1; 1747215976Sjmallett uint64_t f_error : 1; 1748215976Sjmallett uint64_t reserved_22_63 : 42; 1749215976Sjmallett#endif 1750215976Sjmallett } cn63xxp1; 1751215976Sjmallett}; 1752215976Sjmalletttypedef union cvmx_sriox_int_reg cvmx_sriox_int_reg_t; 1753215976Sjmallett 1754215976Sjmallett/** 1755215976Sjmallett * cvmx_srio#_ip_feature 1756215976Sjmallett * 1757215976Sjmallett * SRIO_IP_FEATURE = SRIO IP Feature Select 1758215976Sjmallett * 1759215976Sjmallett * Debug Register used to enable IP Core Features 1760215976Sjmallett * 1761215976Sjmallett * Notes: 1762215976Sjmallett * This register is used to override powerup values used by the SRIOMAINT Registers and QLM 1763215976Sjmallett * configuration. The register is only reset during COLD boot. It should only be modified only 1764215976Sjmallett * while SRIO(0..1)_STATUS_REG.ACCESS is zero. 1765215976Sjmallett * 1766215976Sjmallett * Clk_Rst: SRIO(0..1)_IP_FEATURE sclk srst_cold_n 1767215976Sjmallett */ 1768215976Sjmallettunion cvmx_sriox_ip_feature 1769215976Sjmallett{ 1770215976Sjmallett uint64_t u64; 1771215976Sjmallett struct cvmx_sriox_ip_feature_s 1772215976Sjmallett { 1773215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1774215976Sjmallett uint64_t ops : 32; /**< Reset Value for the OPs fields in both the 1775215976Sjmallett SRIOMAINT(0..1)_SRC_OPS and SRIOMAINT(0..1)_DST_OPS 1776215976Sjmallett registers. */ 1777215976Sjmallett uint64_t reserved_14_31 : 18; 1778215976Sjmallett uint64_t a66 : 1; /**< 66-bit Address Support. Value for bit 2 of the 1779215976Sjmallett EX_ADDR field in the SRIOMAINT(0..1)_PE_FEAT register. */ 1780215976Sjmallett uint64_t a50 : 1; /**< 50-bit Address Support. Value for bit 1 of the 1781215976Sjmallett EX_ADDR field in the SRIOMAINT(0..1)_PE_FEAT register. */ 1782215976Sjmallett uint64_t reserved_11_11 : 1; 1783215976Sjmallett uint64_t tx_flow : 1; /**< Reset Value for the TX_FLOW field in the 1784215976Sjmallett SRIOMAINT(0..1)_IR_BUFFER_CONFIG register. */ 1785215976Sjmallett uint64_t pt_width : 2; /**< Value for the PT_WIDTH field in the 1786215976Sjmallett SRIOMAINT(0..1)_PORT_0_CTL register. */ 1787215976Sjmallett uint64_t tx_pol : 4; /**< TX Serdes Polarity Lanes 3-0 1788215976Sjmallett 0 = Normal Operation 1789215976Sjmallett 1 = Invert, Swap +/- Tx SERDES Pins */ 1790215976Sjmallett uint64_t rx_pol : 4; /**< RX Serdes Polarity Lanes 3-0 1791215976Sjmallett 0 = Normal Operation 1792215976Sjmallett 1 = Invert, Swap +/- Rx SERDES Pins */ 1793215976Sjmallett#else 1794215976Sjmallett uint64_t rx_pol : 4; 1795215976Sjmallett uint64_t tx_pol : 4; 1796215976Sjmallett uint64_t pt_width : 2; 1797215976Sjmallett uint64_t tx_flow : 1; 1798215976Sjmallett uint64_t reserved_11_11 : 1; 1799215976Sjmallett uint64_t a50 : 1; 1800215976Sjmallett uint64_t a66 : 1; 1801215976Sjmallett uint64_t reserved_14_31 : 18; 1802215976Sjmallett uint64_t ops : 32; 1803215976Sjmallett#endif 1804215976Sjmallett } s; 1805215976Sjmallett struct cvmx_sriox_ip_feature_s cn63xx; 1806215976Sjmallett struct cvmx_sriox_ip_feature_s cn63xxp1; 1807215976Sjmallett}; 1808215976Sjmalletttypedef union cvmx_sriox_ip_feature cvmx_sriox_ip_feature_t; 1809215976Sjmallett 1810215976Sjmallett/** 1811215976Sjmallett * cvmx_srio#_mac_buffers 1812215976Sjmallett * 1813215976Sjmallett * SRIO_MAC_BUFFERS = SRIO MAC Buffer Control (Pass 2) 1814215976Sjmallett * 1815215976Sjmallett * Reports errors and controls buffer usage on the main MAC buffers 1816215976Sjmallett * 1817215976Sjmallett * Notes: 1818215976Sjmallett * Register displays errors status for each of the eight RX and TX buffers and controls use of the 1819215976Sjmallett * buffer in future operations. It also displays the number of RX and TX buffers currently used by 1820215976Sjmallett * the MAC. 1821215976Sjmallett * 1822215976Sjmallett * Clk_Rst: SRIO(0..1)_MAC_BUFFERS hclk hrst_n 1823215976Sjmallett */ 1824215976Sjmallettunion cvmx_sriox_mac_buffers 1825215976Sjmallett{ 1826215976Sjmallett uint64_t u64; 1827215976Sjmallett struct cvmx_sriox_mac_buffers_s 1828215976Sjmallett { 1829215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1830215976Sjmallett uint64_t reserved_56_63 : 8; 1831215976Sjmallett uint64_t tx_enb : 8; /**< TX Buffer Enable. Each bit enables a specific TX 1832215976Sjmallett Buffer. At least 2 of these bits must be set for 1833215976Sjmallett proper operation. These bits must be cleared to 1834215976Sjmallett and then set again to reuese the buffer after an 1835215976Sjmallett error occurs. */ 1836215976Sjmallett uint64_t reserved_44_47 : 4; 1837215976Sjmallett uint64_t tx_inuse : 4; /**< Number of TX buffers containing packets waiting 1838215976Sjmallett to be transmitted or to be acknowledged. */ 1839215976Sjmallett uint64_t tx_stat : 8; /**< Errors detected in main SRIO Transmit Buffers. 1840215976Sjmallett CRC error detected in buffer sets bit of buffer \# 1841215976Sjmallett until the corresponding TX_ENB is disabled. Each 1842215976Sjmallett bit set causes the SRIO(0..1)_INT_REG.MAC_BUF 1843215976Sjmallett interrupt. */ 1844215976Sjmallett uint64_t reserved_24_31 : 8; 1845215976Sjmallett uint64_t rx_enb : 8; /**< RX Buffer Enable. Each bit enables a specific RX 1846215976Sjmallett Buffer. At least 2 of these bits must be set for 1847215976Sjmallett proper operation. These bits must be cleared to 1848215976Sjmallett and then set again to reuese the buffer after an 1849215976Sjmallett error occurs. */ 1850215976Sjmallett uint64_t reserved_12_15 : 4; 1851215976Sjmallett uint64_t rx_inuse : 4; /**< Number of RX buffers containing valid packets 1852215976Sjmallett waiting to be processed by the logical layer. */ 1853215976Sjmallett uint64_t rx_stat : 8; /**< Errors detected in main SRIO Receive Buffers. CRC 1854215976Sjmallett error detected in buffer sets bit of buffer \# 1855215976Sjmallett until the corresponding RX_ENB is disabled. Each 1856215976Sjmallett bit set causes the SRIO(0..1)_INT_REG.MAC_BUF 1857215976Sjmallett interrupt. */ 1858215976Sjmallett#else 1859215976Sjmallett uint64_t rx_stat : 8; 1860215976Sjmallett uint64_t rx_inuse : 4; 1861215976Sjmallett uint64_t reserved_12_15 : 4; 1862215976Sjmallett uint64_t rx_enb : 8; 1863215976Sjmallett uint64_t reserved_24_31 : 8; 1864215976Sjmallett uint64_t tx_stat : 8; 1865215976Sjmallett uint64_t tx_inuse : 4; 1866215976Sjmallett uint64_t reserved_44_47 : 4; 1867215976Sjmallett uint64_t tx_enb : 8; 1868215976Sjmallett uint64_t reserved_56_63 : 8; 1869215976Sjmallett#endif 1870215976Sjmallett } s; 1871215976Sjmallett struct cvmx_sriox_mac_buffers_s cn63xx; 1872215976Sjmallett}; 1873215976Sjmalletttypedef union cvmx_sriox_mac_buffers cvmx_sriox_mac_buffers_t; 1874215976Sjmallett 1875215976Sjmallett/** 1876215976Sjmallett * cvmx_srio#_maint_op 1877215976Sjmallett * 1878215976Sjmallett * SRIO_MAINT_OP = SRIO Maintenance Operation 1879215976Sjmallett * 1880215976Sjmallett * Allows access to maintenance registers. 1881215976Sjmallett * 1882215976Sjmallett * Notes: 1883215976Sjmallett * This register allows write access to the local SRIOMAINT registers. A write to this register 1884215976Sjmallett * posts a read or write operation selected by the OP bit to the local SRIOMAINT register selected by 1885215976Sjmallett * ADDR. This write also sets the PENDING bit. The PENDING bit is cleared by hardware when the 1886215976Sjmallett * operation is complete. The MAINT_OP Interrupt is also set as the PENDING bit is cleared. While 1887215976Sjmallett * this bit is set, additional writes to this register stall the RSL. The FAIL bit is set with the 1888215976Sjmallett * clearing of the PENDING bit when an illegal address is selected. WR_DATA is used only during write 1889215976Sjmallett * operations. Only 32-bit Maintenance Operations are supported. 1890215976Sjmallett * 1891215976Sjmallett * Clk_Rst: SRIO(0..1)_MAINT_OP hclk hrst_n 1892215976Sjmallett */ 1893215976Sjmallettunion cvmx_sriox_maint_op 1894215976Sjmallett{ 1895215976Sjmallett uint64_t u64; 1896215976Sjmallett struct cvmx_sriox_maint_op_s 1897215976Sjmallett { 1898215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1899215976Sjmallett uint64_t wr_data : 32; /**< Write Data[31:0]. */ 1900215976Sjmallett uint64_t reserved_27_31 : 5; 1901215976Sjmallett uint64_t fail : 1; /**< Maintenance Operation Address Error */ 1902215976Sjmallett uint64_t pending : 1; /**< Maintenance Operation Pending */ 1903215976Sjmallett uint64_t op : 1; /**< Operation. 0=Read, 1=Write */ 1904215976Sjmallett uint64_t addr : 24; /**< Address. Addr[1:0] are ignored. */ 1905215976Sjmallett#else 1906215976Sjmallett uint64_t addr : 24; 1907215976Sjmallett uint64_t op : 1; 1908215976Sjmallett uint64_t pending : 1; 1909215976Sjmallett uint64_t fail : 1; 1910215976Sjmallett uint64_t reserved_27_31 : 5; 1911215976Sjmallett uint64_t wr_data : 32; 1912215976Sjmallett#endif 1913215976Sjmallett } s; 1914215976Sjmallett struct cvmx_sriox_maint_op_s cn63xx; 1915215976Sjmallett struct cvmx_sriox_maint_op_s cn63xxp1; 1916215976Sjmallett}; 1917215976Sjmalletttypedef union cvmx_sriox_maint_op cvmx_sriox_maint_op_t; 1918215976Sjmallett 1919215976Sjmallett/** 1920215976Sjmallett * cvmx_srio#_maint_rd_data 1921215976Sjmallett * 1922215976Sjmallett * SRIO_MAINT_RD_DATA = SRIO Maintenance Read Data 1923215976Sjmallett * 1924215976Sjmallett * Allows read access of maintenance registers. 1925215976Sjmallett * 1926215976Sjmallett * Notes: 1927215976Sjmallett * This register allows read access of the local SRIOMAINT registers. A write to the SRIO(0..1)_MAINT_OP 1928215976Sjmallett * register with the OP bit set to zero initiates a read request and clears the VALID bit. The 1929215976Sjmallett * resulting read is returned here and the VALID bit is set. Access to the register will not stall 1930215976Sjmallett * the RSL but the VALID bit should be read. 1931215976Sjmallett * 1932215976Sjmallett * Clk_Rst: SRIO(0..1)_MAINT_RD_DATA hclk hrst_n 1933215976Sjmallett */ 1934215976Sjmallettunion cvmx_sriox_maint_rd_data 1935215976Sjmallett{ 1936215976Sjmallett uint64_t u64; 1937215976Sjmallett struct cvmx_sriox_maint_rd_data_s 1938215976Sjmallett { 1939215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1940215976Sjmallett uint64_t reserved_33_63 : 31; 1941215976Sjmallett uint64_t valid : 1; /**< Read Data Valid. */ 1942215976Sjmallett uint64_t rd_data : 32; /**< Read Data[31:0]. */ 1943215976Sjmallett#else 1944215976Sjmallett uint64_t rd_data : 32; 1945215976Sjmallett uint64_t valid : 1; 1946215976Sjmallett uint64_t reserved_33_63 : 31; 1947215976Sjmallett#endif 1948215976Sjmallett } s; 1949215976Sjmallett struct cvmx_sriox_maint_rd_data_s cn63xx; 1950215976Sjmallett struct cvmx_sriox_maint_rd_data_s cn63xxp1; 1951215976Sjmallett}; 1952215976Sjmalletttypedef union cvmx_sriox_maint_rd_data cvmx_sriox_maint_rd_data_t; 1953215976Sjmallett 1954215976Sjmallett/** 1955215976Sjmallett * cvmx_srio#_mce_tx_ctl 1956215976Sjmallett * 1957215976Sjmallett * SRIO_MCE_TX_CTL = SRIO Multicast Event Transmit Control 1958215976Sjmallett * 1959215976Sjmallett * Multicast Event TX Control 1960215976Sjmallett * 1961215976Sjmallett * Notes: 1962215976Sjmallett * Writes to this register cause the SRIO device to generate a Multicast Event. Setting the MCE bit 1963215976Sjmallett * requests the logic to generate the Multicast Event Symbol. Reading the MCS bit shows the status 1964215976Sjmallett * of the transmit event. The hardware will clear the bit when the event has been transmitted and 1965215976Sjmallett * set the MCS_TX Interrupt. 1966215976Sjmallett * 1967215976Sjmallett * Clk_Rst: SRIO(0..1)_MCE_TX_CTL hclk hrst_n 1968215976Sjmallett */ 1969215976Sjmallettunion cvmx_sriox_mce_tx_ctl 1970215976Sjmallett{ 1971215976Sjmallett uint64_t u64; 1972215976Sjmallett struct cvmx_sriox_mce_tx_ctl_s 1973215976Sjmallett { 1974215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1975215976Sjmallett uint64_t reserved_1_63 : 63; 1976215976Sjmallett uint64_t mce : 1; /**< Multicast Event Transmit. */ 1977215976Sjmallett#else 1978215976Sjmallett uint64_t mce : 1; 1979215976Sjmallett uint64_t reserved_1_63 : 63; 1980215976Sjmallett#endif 1981215976Sjmallett } s; 1982215976Sjmallett struct cvmx_sriox_mce_tx_ctl_s cn63xx; 1983215976Sjmallett struct cvmx_sriox_mce_tx_ctl_s cn63xxp1; 1984215976Sjmallett}; 1985215976Sjmalletttypedef union cvmx_sriox_mce_tx_ctl cvmx_sriox_mce_tx_ctl_t; 1986215976Sjmallett 1987215976Sjmallett/** 1988215976Sjmallett * cvmx_srio#_mem_op_ctrl 1989215976Sjmallett * 1990215976Sjmallett * SRIO_MEM_OP_CTRL = SRIO Memory Operation Control 1991215976Sjmallett * 1992215976Sjmallett * The SRIO Memory Operation Control 1993215976Sjmallett * 1994215976Sjmallett * Notes: 1995215976Sjmallett * This register is used to control memory operations. Bits are provided to override the priority of 1996215976Sjmallett * the outgoing responses to memory operations. The memory operations with responses include NREAD, 1997215976Sjmallett * NWRITE_R, ATOMIC_INC, ATOMIC_DEC, ATOMIC_SET and ATOMIC_CLR. 1998215976Sjmallett * 1999215976Sjmallett * Clk_Rst: SRIO(0..1)_MEM_OP_CTRL hclk hrst_n 2000215976Sjmallett */ 2001215976Sjmallettunion cvmx_sriox_mem_op_ctrl 2002215976Sjmallett{ 2003215976Sjmallett uint64_t u64; 2004215976Sjmallett struct cvmx_sriox_mem_op_ctrl_s 2005215976Sjmallett { 2006215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2007215976Sjmallett uint64_t reserved_10_63 : 54; 2008215976Sjmallett uint64_t rr_ro : 1; /**< Read Response Relaxed Ordering. Controls ordering 2009215976Sjmallett rules for incoming memory operations 2010215976Sjmallett 0 = Normal Ordering 2011215976Sjmallett 1 = Relaxed Ordering */ 2012215976Sjmallett uint64_t w_ro : 1; /**< Write Relaxed Ordering. Controls ordering rules 2013215976Sjmallett for incoming memory operations 2014215976Sjmallett 0 = Normal Ordering 2015215976Sjmallett 1 = Relaxed Ordering */ 2016215976Sjmallett uint64_t reserved_6_7 : 2; 2017215976Sjmallett uint64_t rp1_sid : 1; /**< Sets response priority for incomimg memory ops 2018215976Sjmallett of priority 1 on the secondary ID (0=2, 1=3) */ 2019215976Sjmallett uint64_t rp0_sid : 2; /**< Sets response priority for incomimg memory ops 2020215976Sjmallett of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */ 2021215976Sjmallett uint64_t rp1_pid : 1; /**< Sets response priority for incomimg memory ops 2022215976Sjmallett of priority 1 on the primary ID (0=2, 1=3) */ 2023215976Sjmallett uint64_t rp0_pid : 2; /**< Sets response priority for incomimg memory ops 2024215976Sjmallett of priority 0 on the primary ID (0,1=1 2=2, 3=3) */ 2025215976Sjmallett#else 2026215976Sjmallett uint64_t rp0_pid : 2; 2027215976Sjmallett uint64_t rp1_pid : 1; 2028215976Sjmallett uint64_t rp0_sid : 2; 2029215976Sjmallett uint64_t rp1_sid : 1; 2030215976Sjmallett uint64_t reserved_6_7 : 2; 2031215976Sjmallett uint64_t w_ro : 1; 2032215976Sjmallett uint64_t rr_ro : 1; 2033215976Sjmallett uint64_t reserved_10_63 : 54; 2034215976Sjmallett#endif 2035215976Sjmallett } s; 2036215976Sjmallett struct cvmx_sriox_mem_op_ctrl_s cn63xx; 2037215976Sjmallett struct cvmx_sriox_mem_op_ctrl_s cn63xxp1; 2038215976Sjmallett}; 2039215976Sjmalletttypedef union cvmx_sriox_mem_op_ctrl cvmx_sriox_mem_op_ctrl_t; 2040215976Sjmallett 2041215976Sjmallett/** 2042215976Sjmallett * cvmx_srio#_omsg_ctrl# 2043215976Sjmallett * 2044215976Sjmallett * SRIO_OMSG_CTRLX = SRIO Outbound Message Control 2045215976Sjmallett * 2046215976Sjmallett * The SRIO Controller X Outbound Message Control Register 2047215976Sjmallett * 2048215976Sjmallett * Notes: 2049215976Sjmallett * 1) If IDM_TT, IDM_SIS, and IDM_DID are all clear, then the "ID match" will always be false. 2050215976Sjmallett * 2) LTTR_SP and LTTR_MP must be non-zero at all times, otherwise the message output queue can 2051215976Sjmallett * get blocked 2052215976Sjmallett * 3) TESTMODE has no function on controller 1 2053215976Sjmallett * 4) When IDM_TT=0, it is possible for an ID match to match an 8-bit DID with a 16-bit DID - SRIO 2054215976Sjmallett * zero-extends all 8-bit DID's, and the DID comparisons are always 16-bits. 2055215976Sjmallett * 2056215976Sjmallett * Clk_Rst: SRIO(0..1)_OMSG_CTRL[0:1] hclk hrst_n 2057215976Sjmallett */ 2058215976Sjmallettunion cvmx_sriox_omsg_ctrlx 2059215976Sjmallett{ 2060215976Sjmallett uint64_t u64; 2061215976Sjmallett struct cvmx_sriox_omsg_ctrlx_s 2062215976Sjmallett { 2063215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2064215976Sjmallett uint64_t testmode : 1; /**< Controller X test mode (keep as RSVD in HRM) */ 2065215976Sjmallett uint64_t reserved_37_62 : 26; 2066215976Sjmallett uint64_t silo_max : 5; /**< Sets max number outgoing segments for controller X 2067215976Sjmallett (Pass 2) */ 2068215976Sjmallett uint64_t rtry_thr : 16; /**< Controller X Retry threshold */ 2069215976Sjmallett uint64_t rtry_en : 1; /**< Controller X Retry threshold enable */ 2070215976Sjmallett uint64_t reserved_11_14 : 4; 2071215976Sjmallett uint64_t idm_tt : 1; /**< Controller X ID match includes TT ID */ 2072215976Sjmallett uint64_t idm_sis : 1; /**< Controller X ID match includes SIS */ 2073215976Sjmallett uint64_t idm_did : 1; /**< Controller X ID match includes DID */ 2074215976Sjmallett uint64_t lttr_sp : 4; /**< Controller X SP allowable letters in dynamic 2075215976Sjmallett letter select mode (LNS) */ 2076215976Sjmallett uint64_t lttr_mp : 4; /**< Controller X MP allowable letters in dynamic 2077215976Sjmallett letter select mode (LNS) */ 2078215976Sjmallett#else 2079215976Sjmallett uint64_t lttr_mp : 4; 2080215976Sjmallett uint64_t lttr_sp : 4; 2081215976Sjmallett uint64_t idm_did : 1; 2082215976Sjmallett uint64_t idm_sis : 1; 2083215976Sjmallett uint64_t idm_tt : 1; 2084215976Sjmallett uint64_t reserved_11_14 : 4; 2085215976Sjmallett uint64_t rtry_en : 1; 2086215976Sjmallett uint64_t rtry_thr : 16; 2087215976Sjmallett uint64_t silo_max : 5; 2088215976Sjmallett uint64_t reserved_37_62 : 26; 2089215976Sjmallett uint64_t testmode : 1; 2090215976Sjmallett#endif 2091215976Sjmallett } s; 2092215976Sjmallett struct cvmx_sriox_omsg_ctrlx_s cn63xx; 2093215976Sjmallett struct cvmx_sriox_omsg_ctrlx_cn63xxp1 2094215976Sjmallett { 2095215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2096215976Sjmallett uint64_t testmode : 1; /**< Controller X test mode (keep as RSVD in HRM) */ 2097215976Sjmallett uint64_t reserved_32_62 : 31; 2098215976Sjmallett uint64_t rtry_thr : 16; /**< Controller X Retry threshold */ 2099215976Sjmallett uint64_t rtry_en : 1; /**< Controller X Retry threshold enable */ 2100215976Sjmallett uint64_t reserved_11_14 : 4; 2101215976Sjmallett uint64_t idm_tt : 1; /**< Controller X ID match includes TT ID */ 2102215976Sjmallett uint64_t idm_sis : 1; /**< Controller X ID match includes SIS */ 2103215976Sjmallett uint64_t idm_did : 1; /**< Controller X ID match includes DID */ 2104215976Sjmallett uint64_t lttr_sp : 4; /**< Controller X SP allowable letters in dynamic 2105215976Sjmallett letter select mode (LNS) */ 2106215976Sjmallett uint64_t lttr_mp : 4; /**< Controller X MP allowable letters in dynamic 2107215976Sjmallett letter select mode (LNS) */ 2108215976Sjmallett#else 2109215976Sjmallett uint64_t lttr_mp : 4; 2110215976Sjmallett uint64_t lttr_sp : 4; 2111215976Sjmallett uint64_t idm_did : 1; 2112215976Sjmallett uint64_t idm_sis : 1; 2113215976Sjmallett uint64_t idm_tt : 1; 2114215976Sjmallett uint64_t reserved_11_14 : 4; 2115215976Sjmallett uint64_t rtry_en : 1; 2116215976Sjmallett uint64_t rtry_thr : 16; 2117215976Sjmallett uint64_t reserved_32_62 : 31; 2118215976Sjmallett uint64_t testmode : 1; 2119215976Sjmallett#endif 2120215976Sjmallett } cn63xxp1; 2121215976Sjmallett}; 2122215976Sjmalletttypedef union cvmx_sriox_omsg_ctrlx cvmx_sriox_omsg_ctrlx_t; 2123215976Sjmallett 2124215976Sjmallett/** 2125215976Sjmallett * cvmx_srio#_omsg_done_counts# 2126215976Sjmallett * 2127215976Sjmallett * SRIO_OMSG_DONE_COUNTSX = SRIO Outbound Message Complete Counts (Pass 2) 2128215976Sjmallett * 2129215976Sjmallett * The SRIO Controller X Outbound Message Complete Counts Register 2130215976Sjmallett * 2131215976Sjmallett * Notes: 2132215976Sjmallett * This register shows the number of successful and unsuccessful Outgoing Messages issued through 2133215976Sjmallett * this controller. The only messages considered are the ones with the INT field set in the PKO 2134215976Sjmallett * message header. This register is typically not written while Outbound SRIO Memory traffic is 2135215976Sjmallett * enabled. The sum of the GOOD and BAD counts should equal the number of messages sent unless 2136215976Sjmallett * the MAC has been reset. 2137215976Sjmallett * 2138215976Sjmallett * Clk_Rst: SRIO(0..1)_OMSG_DONE_COUNTS[0:1] hclk hrst_n 2139215976Sjmallett */ 2140215976Sjmallettunion cvmx_sriox_omsg_done_countsx 2141215976Sjmallett{ 2142215976Sjmallett uint64_t u64; 2143215976Sjmallett struct cvmx_sriox_omsg_done_countsx_s 2144215976Sjmallett { 2145215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2146215976Sjmallett uint64_t reserved_32_63 : 32; 2147215976Sjmallett uint64_t bad : 16; /**< Number of Outbound Messages requesting an INT that 2148215976Sjmallett did not increment GOOD. (One or more segment of the 2149215976Sjmallett message either timed out, reached the retry limit, 2150215976Sjmallett or received an ERROR response.) */ 2151215976Sjmallett uint64_t good : 16; /**< Number of Outbound Messages requesting an INT that 2152215976Sjmallett received a DONE response for every segment. */ 2153215976Sjmallett#else 2154215976Sjmallett uint64_t good : 16; 2155215976Sjmallett uint64_t bad : 16; 2156215976Sjmallett uint64_t reserved_32_63 : 32; 2157215976Sjmallett#endif 2158215976Sjmallett } s; 2159215976Sjmallett struct cvmx_sriox_omsg_done_countsx_s cn63xx; 2160215976Sjmallett}; 2161215976Sjmalletttypedef union cvmx_sriox_omsg_done_countsx cvmx_sriox_omsg_done_countsx_t; 2162215976Sjmallett 2163215976Sjmallett/** 2164215976Sjmallett * cvmx_srio#_omsg_fmp_mr# 2165215976Sjmallett * 2166215976Sjmallett * SRIO_OMSG_FMP_MRX = SRIO Outbound Message FIRSTMP Message Restriction 2167215976Sjmallett * 2168215976Sjmallett * The SRIO Controller X Outbound Message FIRSTMP Message Restriction Register 2169215976Sjmallett * 2170215976Sjmallett * Notes: 2171215976Sjmallett * This CSR controls when FMP candidate message segments (from the two different controllers) can enter 2172215976Sjmallett * the message segment silo to be sent out. A segment remains in the silo until after is has 2173215976Sjmallett * been transmitted and either acknowledged or errored out. 2174215976Sjmallett * 2175215976Sjmallett * Candidates and silo entries are one of 4 types: 2176215976Sjmallett * SP - a single-segment message 2177215976Sjmallett * FMP - the first segment of a multi-segment message 2178215976Sjmallett * NMP - the other segments in a multi-segment message 2179215976Sjmallett * PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing 2180215976Sjmallett * a multi-segment message into the silo and can match against segments generated by 2181215976Sjmallett * the other controller 2182215976Sjmallett * 2183215976Sjmallett * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo. 2184215976Sjmallett * By default (i.e. zeroes in this CSR), the FMP candidate matches against all entries in the 2185215976Sjmallett * silo. When fields in this CSR are set, FMP candidate segments will match fewer silo entries and 2186215976Sjmallett * can enter the silo more freely, probably providing better performance. 2187215976Sjmallett * 2188215976Sjmallett * Clk_Rst: SRIO(0..1)_OMSG_FMP_MR[0:1] hclk hrst_n 2189215976Sjmallett */ 2190215976Sjmallettunion cvmx_sriox_omsg_fmp_mrx 2191215976Sjmallett{ 2192215976Sjmallett uint64_t u64; 2193215976Sjmallett struct cvmx_sriox_omsg_fmp_mrx_s 2194215976Sjmallett { 2195215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2196215976Sjmallett uint64_t reserved_15_63 : 49; 2197215976Sjmallett uint64_t ctlr_sp : 1; /**< Controller X FIRSTMP enable controller SP 2198215976Sjmallett When set, the FMP candidate message segment can 2199215976Sjmallett only match siloed SP segments that were created 2200215976Sjmallett by the same controller. When clear, this FMP-SP 2201215976Sjmallett match can also occur when the segments were 2202215976Sjmallett created by the other controller. 2203215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2204215976Sjmallett uint64_t ctlr_fmp : 1; /**< Controller X FIRSTMP enable controller FIRSTMP 2205215976Sjmallett When set, the FMP candidate message segment can 2206215976Sjmallett only match siloed FMP segments that were created 2207215976Sjmallett by the same controller. When clear, this FMP-FMP 2208215976Sjmallett match can also occur when the segments were 2209215976Sjmallett created by the other controller. 2210215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2211215976Sjmallett uint64_t ctlr_nmp : 1; /**< Controller X FIRSTMP enable controller NFIRSTMP 2212215976Sjmallett When set, the FMP candidate message segment can 2213215976Sjmallett only match siloed NMP segments that were created 2214215976Sjmallett by the same controller. When clear, this FMP-NMP 2215215976Sjmallett match can also occur when the segments were 2216215976Sjmallett created by the other controller. 2217215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2218215976Sjmallett uint64_t id_sp : 1; /**< Controller X FIRSTMP enable ID SP 2219215976Sjmallett When set, the FMP candidate message segment can 2220215976Sjmallett only match siloed SP segments that "ID match" the 2221215976Sjmallett candidate. When clear, this FMP-SP match can occur 2222215976Sjmallett with any ID values. 2223215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2224215976Sjmallett uint64_t id_fmp : 1; /**< Controller X FIRSTMP enable ID FIRSTMP 2225215976Sjmallett When set, the FMP candidate message segment can 2226215976Sjmallett only match siloed FMP segments that "ID match" the 2227215976Sjmallett candidate. When clear, this FMP-FMP match can occur 2228215976Sjmallett with any ID values. 2229215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2230215976Sjmallett uint64_t id_nmp : 1; /**< Controller X FIRSTMP enable ID NFIRSTMP 2231215976Sjmallett When set, the FMP candidate message segment can 2232215976Sjmallett only match siloed NMP segments that "ID match" the 2233215976Sjmallett candidate. When clear, this FMP-NMP match can occur 2234215976Sjmallett with any ID values. 2235215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2236215976Sjmallett uint64_t id_psd : 1; /**< Controller X FIRSTMP enable ID PSEUDO 2237215976Sjmallett When set, the FMP candidate message segment can 2238215976Sjmallett only match the silo pseudo (for the other 2239215976Sjmallett controller) when it is an "ID match". When clear, 2240215976Sjmallett this FMP-PSD match can occur with any ID values. 2241215976Sjmallett Not used by the hardware when ALL_PSD is set. */ 2242215976Sjmallett uint64_t mbox_sp : 1; /**< Controller X FIRSTMP enable MBOX SP 2243215976Sjmallett When set, the FMP candidate message segment can 2244215976Sjmallett only match siloed SP segments with the same 2-bit 2245215976Sjmallett mbox value as the candidate. When clear, this 2246215976Sjmallett FMP-SP match can occur with any mbox values. 2247215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2248215976Sjmallett uint64_t mbox_fmp : 1; /**< Controller X FIRSTMP enable MBOX FIRSTMP 2249215976Sjmallett When set, the FMP candidate message segment can 2250215976Sjmallett only match siloed FMP segments with the same 2-bit 2251215976Sjmallett mbox value as the candidate. When clear, this 2252215976Sjmallett FMP-FMP match can occur with any mbox values. 2253215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2254215976Sjmallett uint64_t mbox_nmp : 1; /**< Controller X FIRSTMP enable MBOX NFIRSTMP 2255215976Sjmallett When set, the FMP candidate message segment can 2256215976Sjmallett only match siloed NMP segments with the same 2-bit 2257215976Sjmallett mbox value as the candidate. When clear, this 2258215976Sjmallett FMP-NMP match can occur with any mbox values. 2259215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2260215976Sjmallett uint64_t mbox_psd : 1; /**< Controller X FIRSTMP enable MBOX PSEUDO 2261215976Sjmallett When set, the FMP candidate message segment can 2262215976Sjmallett only match the silo pseudo (for the other 2263215976Sjmallett controller) if the pseudo has the same 2-bit mbox 2264215976Sjmallett value as the candidate. When clear, this FMP-PSD 2265215976Sjmallett match can occur with any mbox values. 2266215976Sjmallett Not used by the hardware when ALL_PSD is set. */ 2267215976Sjmallett uint64_t all_sp : 1; /**< Controller X FIRSTMP enable all SP 2268215976Sjmallett When set, no FMP candidate message segments ever 2269215976Sjmallett match siloed SP segments and ID_SP 2270215976Sjmallett and MBOX_SP are not used. When clear, FMP-SP 2271215976Sjmallett matches can occur. */ 2272215976Sjmallett uint64_t all_fmp : 1; /**< Controller X FIRSTMP enable all FIRSTMP 2273215976Sjmallett When set, no FMP candidate message segments ever 2274215976Sjmallett match siloed FMP segments and ID_FMP and MBOX_FMP 2275215976Sjmallett are not used. When clear, FMP-FMP matches can 2276215976Sjmallett occur. */ 2277215976Sjmallett uint64_t all_nmp : 1; /**< Controller X FIRSTMP enable all NFIRSTMP 2278215976Sjmallett When set, no FMP candidate message segments ever 2279215976Sjmallett match siloed NMP segments and ID_NMP and MBOX_NMP 2280215976Sjmallett are not used. When clear, FMP-NMP matches can 2281215976Sjmallett occur. */ 2282215976Sjmallett uint64_t all_psd : 1; /**< Controller X FIRSTMP enable all PSEUDO 2283215976Sjmallett When set, no FMP candidate message segments ever 2284215976Sjmallett match the silo pseudo (for the other controller) 2285215976Sjmallett and ID_PSD and MBOX_PSD are not used. When clear, 2286215976Sjmallett FMP-PSD matches can occur. */ 2287215976Sjmallett#else 2288215976Sjmallett uint64_t all_psd : 1; 2289215976Sjmallett uint64_t all_nmp : 1; 2290215976Sjmallett uint64_t all_fmp : 1; 2291215976Sjmallett uint64_t all_sp : 1; 2292215976Sjmallett uint64_t mbox_psd : 1; 2293215976Sjmallett uint64_t mbox_nmp : 1; 2294215976Sjmallett uint64_t mbox_fmp : 1; 2295215976Sjmallett uint64_t mbox_sp : 1; 2296215976Sjmallett uint64_t id_psd : 1; 2297215976Sjmallett uint64_t id_nmp : 1; 2298215976Sjmallett uint64_t id_fmp : 1; 2299215976Sjmallett uint64_t id_sp : 1; 2300215976Sjmallett uint64_t ctlr_nmp : 1; 2301215976Sjmallett uint64_t ctlr_fmp : 1; 2302215976Sjmallett uint64_t ctlr_sp : 1; 2303215976Sjmallett uint64_t reserved_15_63 : 49; 2304215976Sjmallett#endif 2305215976Sjmallett } s; 2306215976Sjmallett struct cvmx_sriox_omsg_fmp_mrx_s cn63xx; 2307215976Sjmallett struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1; 2308215976Sjmallett}; 2309215976Sjmalletttypedef union cvmx_sriox_omsg_fmp_mrx cvmx_sriox_omsg_fmp_mrx_t; 2310215976Sjmallett 2311215976Sjmallett/** 2312215976Sjmallett * cvmx_srio#_omsg_nmp_mr# 2313215976Sjmallett * 2314215976Sjmallett * SRIO_OMSG_NMP_MRX = SRIO Outbound Message NFIRSTMP Message Restriction 2315215976Sjmallett * 2316215976Sjmallett * The SRIO Controller X Outbound Message NFIRSTMP Message Restriction Register 2317215976Sjmallett * 2318215976Sjmallett * Notes: 2319215976Sjmallett * This CSR controls when NMP candidate message segments (from the two different controllers) can enter 2320215976Sjmallett * the message segment silo to be sent out. A segment remains in the silo until after is has 2321215976Sjmallett * been transmitted and either acknowledged or errored out. 2322215976Sjmallett * 2323215976Sjmallett * Candidates and silo entries are one of 4 types: 2324215976Sjmallett * SP - a single-segment message 2325215976Sjmallett * FMP - the first segment of a multi-segment message 2326215976Sjmallett * NMP - the other segments in a multi-segment message 2327215976Sjmallett * PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing 2328215976Sjmallett * a multi-segment message into the silo and can match against segments generated by 2329215976Sjmallett * the other controller 2330215976Sjmallett * 2331215976Sjmallett * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo. 2332215976Sjmallett * By default (i.e. zeroes in this CSR), the NMP candidate matches against all entries in the 2333215976Sjmallett * silo. When fields in this CSR are set, NMP candidate segments will match fewer silo entries and 2334215976Sjmallett * can enter the silo more freely, probably providing better performance. 2335215976Sjmallett * 2336215976Sjmallett * Clk_Rst: SRIO(0..1)_OMSG_NMP_MR[0:1] hclk hrst_n 2337215976Sjmallett */ 2338215976Sjmallettunion cvmx_sriox_omsg_nmp_mrx 2339215976Sjmallett{ 2340215976Sjmallett uint64_t u64; 2341215976Sjmallett struct cvmx_sriox_omsg_nmp_mrx_s 2342215976Sjmallett { 2343215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2344215976Sjmallett uint64_t reserved_15_63 : 49; 2345215976Sjmallett uint64_t ctlr_sp : 1; /**< Controller X NFIRSTMP enable controller SP 2346215976Sjmallett When set, the NMP candidate message segment can 2347215976Sjmallett only match siloed SP segments that were created 2348215976Sjmallett by the same controller. When clear, this NMP-SP 2349215976Sjmallett match can also occur when the segments were 2350215976Sjmallett created by the other controller. 2351215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2352215976Sjmallett uint64_t ctlr_fmp : 1; /**< Controller X NFIRSTMP enable controller FIRSTMP 2353215976Sjmallett When set, the NMP candidate message segment can 2354215976Sjmallett only match siloed FMP segments that were created 2355215976Sjmallett by the same controller. When clear, this NMP-FMP 2356215976Sjmallett match can also occur when the segments were 2357215976Sjmallett created by the other controller. 2358215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2359215976Sjmallett uint64_t ctlr_nmp : 1; /**< Controller X NFIRSTMP enable controller NFIRSTMP 2360215976Sjmallett When set, the NMP candidate message segment can 2361215976Sjmallett only match siloed NMP segments that were created 2362215976Sjmallett by the same controller. When clear, this NMP-NMP 2363215976Sjmallett match can also occur when the segments were 2364215976Sjmallett created by the other controller. 2365215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2366215976Sjmallett uint64_t id_sp : 1; /**< Controller X NFIRSTMP enable ID SP 2367215976Sjmallett When set, the NMP candidate message segment can 2368215976Sjmallett only match siloed SP segments that "ID match" the 2369215976Sjmallett candidate. When clear, this NMP-SP match can occur 2370215976Sjmallett with any ID values. 2371215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2372215976Sjmallett uint64_t id_fmp : 1; /**< Controller X NFIRSTMP enable ID FIRSTMP 2373215976Sjmallett When set, the NMP candidate message segment can 2374215976Sjmallett only match siloed FMP segments that "ID match" the 2375215976Sjmallett candidate. When clear, this NMP-FMP match can occur 2376215976Sjmallett with any ID values. 2377215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2378215976Sjmallett uint64_t id_nmp : 1; /**< Controller X NFIRSTMP enable ID NFIRSTMP 2379215976Sjmallett When set, the NMP candidate message segment can 2380215976Sjmallett only match siloed NMP segments that "ID match" the 2381215976Sjmallett candidate. When clear, this NMP-NMP match can occur 2382215976Sjmallett with any ID values. 2383215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2384215976Sjmallett uint64_t reserved_8_8 : 1; 2385215976Sjmallett uint64_t mbox_sp : 1; /**< Controller X NFIRSTMP enable MBOX SP 2386215976Sjmallett When set, the NMP candidate message segment can 2387215976Sjmallett only match siloed SP segments with the same 2-bit 2388215976Sjmallett mbox value as the candidate. When clear, this 2389215976Sjmallett NMP-SP match can occur with any mbox values. 2390215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2391215976Sjmallett uint64_t mbox_fmp : 1; /**< Controller X NFIRSTMP enable MBOX FIRSTMP 2392215976Sjmallett When set, the NMP candidate message segment can 2393215976Sjmallett only match siloed FMP segments with the same 2-bit 2394215976Sjmallett mbox value as the candidate. When clear, this 2395215976Sjmallett NMP-FMP match can occur with any mbox values. 2396215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2397215976Sjmallett uint64_t mbox_nmp : 1; /**< Controller X NFIRSTMP enable MBOX NFIRSTMP 2398215976Sjmallett When set, the NMP candidate message segment can 2399215976Sjmallett only match siloed NMP segments with the same 2-bit 2400215976Sjmallett mbox value as the candidate. When clear, this 2401215976Sjmallett NMP-NMP match can occur with any mbox values. 2402215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2403215976Sjmallett uint64_t reserved_4_4 : 1; 2404215976Sjmallett uint64_t all_sp : 1; /**< Controller X NFIRSTMP enable all SP 2405215976Sjmallett When set, no NMP candidate message segments ever 2406215976Sjmallett match siloed SP segments and ID_SP 2407215976Sjmallett and MBOX_SP are not used. When clear, NMP-SP 2408215976Sjmallett matches can occur. */ 2409215976Sjmallett uint64_t all_fmp : 1; /**< Controller X NFIRSTMP enable all FIRSTMP 2410215976Sjmallett When set, no NMP candidate message segments ever 2411215976Sjmallett match siloed FMP segments and ID_FMP and MBOX_FMP 2412215976Sjmallett are not used. When clear, NMP-FMP matches can 2413215976Sjmallett occur. */ 2414215976Sjmallett uint64_t all_nmp : 1; /**< Controller X NFIRSTMP enable all NFIRSTMP 2415215976Sjmallett When set, no NMP candidate message segments ever 2416215976Sjmallett match siloed NMP segments and ID_NMP and MBOX_NMP 2417215976Sjmallett are not used. When clear, NMP-NMP matches can 2418215976Sjmallett occur. */ 2419215976Sjmallett uint64_t reserved_0_0 : 1; 2420215976Sjmallett#else 2421215976Sjmallett uint64_t reserved_0_0 : 1; 2422215976Sjmallett uint64_t all_nmp : 1; 2423215976Sjmallett uint64_t all_fmp : 1; 2424215976Sjmallett uint64_t all_sp : 1; 2425215976Sjmallett uint64_t reserved_4_4 : 1; 2426215976Sjmallett uint64_t mbox_nmp : 1; 2427215976Sjmallett uint64_t mbox_fmp : 1; 2428215976Sjmallett uint64_t mbox_sp : 1; 2429215976Sjmallett uint64_t reserved_8_8 : 1; 2430215976Sjmallett uint64_t id_nmp : 1; 2431215976Sjmallett uint64_t id_fmp : 1; 2432215976Sjmallett uint64_t id_sp : 1; 2433215976Sjmallett uint64_t ctlr_nmp : 1; 2434215976Sjmallett uint64_t ctlr_fmp : 1; 2435215976Sjmallett uint64_t ctlr_sp : 1; 2436215976Sjmallett uint64_t reserved_15_63 : 49; 2437215976Sjmallett#endif 2438215976Sjmallett } s; 2439215976Sjmallett struct cvmx_sriox_omsg_nmp_mrx_s cn63xx; 2440215976Sjmallett struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1; 2441215976Sjmallett}; 2442215976Sjmalletttypedef union cvmx_sriox_omsg_nmp_mrx cvmx_sriox_omsg_nmp_mrx_t; 2443215976Sjmallett 2444215976Sjmallett/** 2445215976Sjmallett * cvmx_srio#_omsg_port# 2446215976Sjmallett * 2447215976Sjmallett * SRIO_OMSG_PORTX = SRIO Outbound Message Port 2448215976Sjmallett * 2449215976Sjmallett * The SRIO Controller X Outbound Message Port Register 2450215976Sjmallett * 2451215976Sjmallett * Notes: 2452215976Sjmallett * PORT maps the PKO port to SRIO interface \# / controller X as follows: 2453215976Sjmallett * 2454215976Sjmallett * 00 == PKO port 40 2455215976Sjmallett * 01 == PKO port 41 2456215976Sjmallett * 10 == PKO port 42 2457215976Sjmallett * 11 == PKO port 43 2458215976Sjmallett * 2459215976Sjmallett * No two PORT fields among the enabled controllers (ENABLE == 1) may be set to the same value. 2460215976Sjmallett * The register is only reset during COLD boot. The register can be accessed/modified regardless of 2461215976Sjmallett * the value in SRIO(0..1)_STATUS_REG.ACCESS. 2462215976Sjmallett * 2463215976Sjmallett * Clk_Rst: SRIO(0..1)_OMSG_PORT[0:1] sclk srst_n 2464215976Sjmallett */ 2465215976Sjmallettunion cvmx_sriox_omsg_portx 2466215976Sjmallett{ 2467215976Sjmallett uint64_t u64; 2468215976Sjmallett struct cvmx_sriox_omsg_portx_s 2469215976Sjmallett { 2470215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2471215976Sjmallett uint64_t reserved_32_63 : 32; 2472215976Sjmallett uint64_t enable : 1; /**< Controller X enable */ 2473215976Sjmallett uint64_t reserved_2_30 : 29; 2474215976Sjmallett uint64_t port : 2; /**< Controller X PKO port */ 2475215976Sjmallett#else 2476215976Sjmallett uint64_t port : 2; 2477215976Sjmallett uint64_t reserved_2_30 : 29; 2478215976Sjmallett uint64_t enable : 1; 2479215976Sjmallett uint64_t reserved_32_63 : 32; 2480215976Sjmallett#endif 2481215976Sjmallett } s; 2482215976Sjmallett struct cvmx_sriox_omsg_portx_s cn63xx; 2483215976Sjmallett struct cvmx_sriox_omsg_portx_s cn63xxp1; 2484215976Sjmallett}; 2485215976Sjmalletttypedef union cvmx_sriox_omsg_portx cvmx_sriox_omsg_portx_t; 2486215976Sjmallett 2487215976Sjmallett/** 2488215976Sjmallett * cvmx_srio#_omsg_silo_thr 2489215976Sjmallett * 2490215976Sjmallett * SRIO_OMSG_SILO_THR = SRIO Outgoing Message SILO Thresholds (Pass 2) 2491215976Sjmallett * 2492215976Sjmallett * The SRIO Outgoing Message SILO Thresholds 2493215976Sjmallett * 2494215976Sjmallett * Notes: 2495215976Sjmallett * Limits the number of Outgoing Message Segments in flight at a time. This register is reserved in 2496215976Sjmallett * pass 1 and the threshold is set to 16. 2497215976Sjmallett * 2498215976Sjmallett * Clk_Rst: SRIO(0..1)_OMSG_SILO_THR hclk hrst_n 2499215976Sjmallett */ 2500215976Sjmallettunion cvmx_sriox_omsg_silo_thr 2501215976Sjmallett{ 2502215976Sjmallett uint64_t u64; 2503215976Sjmallett struct cvmx_sriox_omsg_silo_thr_s 2504215976Sjmallett { 2505215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2506215976Sjmallett uint64_t reserved_5_63 : 59; 2507215976Sjmallett uint64_t tot_silo : 5; /**< Sets max number segments in flight for all 2508215976Sjmallett controllers. */ 2509215976Sjmallett#else 2510215976Sjmallett uint64_t tot_silo : 5; 2511215976Sjmallett uint64_t reserved_5_63 : 59; 2512215976Sjmallett#endif 2513215976Sjmallett } s; 2514215976Sjmallett struct cvmx_sriox_omsg_silo_thr_s cn63xx; 2515215976Sjmallett}; 2516215976Sjmalletttypedef union cvmx_sriox_omsg_silo_thr cvmx_sriox_omsg_silo_thr_t; 2517215976Sjmallett 2518215976Sjmallett/** 2519215976Sjmallett * cvmx_srio#_omsg_sp_mr# 2520215976Sjmallett * 2521215976Sjmallett * SRIO_OMSG_SP_MRX = SRIO Outbound Message SP Message Restriction 2522215976Sjmallett * 2523215976Sjmallett * The SRIO Controller X Outbound Message SP Message Restriction Register 2524215976Sjmallett * 2525215976Sjmallett * Notes: 2526215976Sjmallett * This CSR controls when SP candidate message segments (from the two different controllers) can enter 2527215976Sjmallett * the message segment silo to be sent out. A segment remains in the silo until after is has 2528215976Sjmallett * been transmitted and either acknowledged or errored out. 2529215976Sjmallett * 2530215976Sjmallett * Candidates and silo entries are one of 4 types: 2531215976Sjmallett * SP - a single-segment message 2532215976Sjmallett * FMP - the first segment of a multi-segment message 2533215976Sjmallett * NMP - the other segments in a multi-segment message 2534215976Sjmallett * PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing 2535215976Sjmallett * a multi-segment message into the silo and can match against segments generated by 2536215976Sjmallett * the other controller 2537215976Sjmallett * 2538215976Sjmallett * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo. 2539215976Sjmallett * By default (i.e. zeroes in this CSR), the SP candidate matches against all entries in the 2540215976Sjmallett * silo. When fields in this CSR are set, SP candidate segments will match fewer silo entries and 2541215976Sjmallett * can enter the silo more freely, probably providing better performance. 2542215976Sjmallett * 2543215976Sjmallett * Clk_Rst: SRIO(0..1)_OMSG_SP_MR[0:1] hclk hrst_n 2544215976Sjmallett */ 2545215976Sjmallettunion cvmx_sriox_omsg_sp_mrx 2546215976Sjmallett{ 2547215976Sjmallett uint64_t u64; 2548215976Sjmallett struct cvmx_sriox_omsg_sp_mrx_s 2549215976Sjmallett { 2550215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2551215976Sjmallett uint64_t reserved_16_63 : 48; 2552215976Sjmallett uint64_t xmbox_sp : 1; /**< Controller X SP enable XMBOX SP 2553215976Sjmallett When set, the SP candidate message can only 2554215976Sjmallett match siloed SP segments with the same 4-bit xmbox 2555215976Sjmallett value as the candidate. When clear, this SP-SP 2556215976Sjmallett match can occur with any xmbox values. 2557215976Sjmallett When XMBOX_SP is set, MBOX_SP will commonly be set. 2558215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2559215976Sjmallett uint64_t ctlr_sp : 1; /**< Controller X SP enable controller SP 2560215976Sjmallett When set, the SP candidate message can 2561215976Sjmallett only match siloed SP segments that were created 2562215976Sjmallett by the same controller. When clear, this SP-SP 2563215976Sjmallett match can also occur when the segments were 2564215976Sjmallett created by the other controller. 2565215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2566215976Sjmallett uint64_t ctlr_fmp : 1; /**< Controller X SP enable controller FIRSTMP 2567215976Sjmallett When set, the SP candidate message can 2568215976Sjmallett only match siloed FMP segments that were created 2569215976Sjmallett by the same controller. When clear, this SP-FMP 2570215976Sjmallett match can also occur when the segments were 2571215976Sjmallett created by the other controller. 2572215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2573215976Sjmallett uint64_t ctlr_nmp : 1; /**< Controller X SP enable controller NFIRSTMP 2574215976Sjmallett When set, the SP candidate message can 2575215976Sjmallett only match siloed NMP segments that were created 2576215976Sjmallett by the same controller. When clear, this SP-NMP 2577215976Sjmallett match can also occur when the segments were 2578215976Sjmallett created by the other controller. 2579215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2580215976Sjmallett uint64_t id_sp : 1; /**< Controller X SP enable ID SP 2581215976Sjmallett When set, the SP candidate message can 2582215976Sjmallett only match siloed SP segments that "ID match" the 2583215976Sjmallett candidate. When clear, this SP-SP match can occur 2584215976Sjmallett with any ID values. 2585215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2586215976Sjmallett uint64_t id_fmp : 1; /**< Controller X SP enable ID FIRSTMP 2587215976Sjmallett When set, the SP candidate message can 2588215976Sjmallett only match siloed FMP segments that "ID match" the 2589215976Sjmallett candidate. When clear, this SP-FMP match can occur 2590215976Sjmallett with any ID values. 2591215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2592215976Sjmallett uint64_t id_nmp : 1; /**< Controller X SP enable ID NFIRSTMP 2593215976Sjmallett When set, the SP candidate message can 2594215976Sjmallett only match siloed NMP segments that "ID match" the 2595215976Sjmallett candidate. When clear, this SP-NMP match can occur 2596215976Sjmallett with any ID values. 2597215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2598215976Sjmallett uint64_t id_psd : 1; /**< Controller X SP enable ID PSEUDO 2599215976Sjmallett When set, the SP candidate message can 2600215976Sjmallett only match the silo pseudo (for the other 2601215976Sjmallett controller) when it is an "ID match". When clear, 2602215976Sjmallett this SP-PSD match can occur with any ID values. 2603215976Sjmallett Not used by the hardware when ALL_PSD is set. */ 2604215976Sjmallett uint64_t mbox_sp : 1; /**< Controller X SP enable MBOX SP 2605215976Sjmallett When set, the SP candidate message can only 2606215976Sjmallett match siloed SP segments with the same 2-bit mbox 2607215976Sjmallett value as the candidate. When clear, this SP-SP 2608215976Sjmallett match can occur with any mbox values. 2609215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2610215976Sjmallett uint64_t mbox_fmp : 1; /**< Controller X SP enable MBOX FIRSTMP 2611215976Sjmallett When set, the SP candidate message can only 2612215976Sjmallett match siloed FMP segments with the same 2-bit mbox 2613215976Sjmallett value as the candidate. When clear, this SP-FMP 2614215976Sjmallett match can occur with any mbox values. 2615215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2616215976Sjmallett uint64_t mbox_nmp : 1; /**< Controller X SP enable MBOX NFIRSTMP 2617215976Sjmallett When set, the SP candidate message can only 2618215976Sjmallett match siloed NMP segments with the same 2-bit mbox 2619215976Sjmallett value as the candidate. When clear, this SP-NMP 2620215976Sjmallett match can occur with any mbox values. 2621215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2622215976Sjmallett uint64_t mbox_psd : 1; /**< Controller X SP enable MBOX PSEUDO 2623215976Sjmallett When set, the SP candidate message can only 2624215976Sjmallett match the silo pseudo (for the other controller) 2625215976Sjmallett if the pseudo has the same 2-bit mbox value as the 2626215976Sjmallett candidate. When clear, this SP-PSD match can occur 2627215976Sjmallett with any mbox values. 2628215976Sjmallett Not used by the hardware when ALL_PSD is set. */ 2629215976Sjmallett uint64_t all_sp : 1; /**< Controller X SP enable all SP 2630215976Sjmallett When set, no SP candidate messages ever 2631215976Sjmallett match siloed SP segments, and XMBOX_SP, ID_SP, 2632215976Sjmallett and MBOX_SP are not used. When clear, SP-SP 2633215976Sjmallett matches can occur. */ 2634215976Sjmallett uint64_t all_fmp : 1; /**< Controller X SP enable all FIRSTMP 2635215976Sjmallett When set, no SP candidate messages ever 2636215976Sjmallett match siloed FMP segments and ID_FMP and MBOX_FMP 2637215976Sjmallett are not used. When clear, SP-FMP matches can 2638215976Sjmallett occur. */ 2639215976Sjmallett uint64_t all_nmp : 1; /**< Controller X SP enable all NFIRSTMP 2640215976Sjmallett When set, no SP candidate messages ever 2641215976Sjmallett match siloed NMP segments and ID_NMP and MBOX_NMP 2642215976Sjmallett are not used. When clear, SP-NMP matches can 2643215976Sjmallett occur. */ 2644215976Sjmallett uint64_t all_psd : 1; /**< Controller X SP enable all PSEUDO 2645215976Sjmallett When set, no SP candidate messages ever 2646215976Sjmallett match the silo pseudo (for the other controller) 2647215976Sjmallett and ID_PSD and MBOX_PSD are not used. When clear, 2648215976Sjmallett SP-PSD matches can occur. */ 2649215976Sjmallett#else 2650215976Sjmallett uint64_t all_psd : 1; 2651215976Sjmallett uint64_t all_nmp : 1; 2652215976Sjmallett uint64_t all_fmp : 1; 2653215976Sjmallett uint64_t all_sp : 1; 2654215976Sjmallett uint64_t mbox_psd : 1; 2655215976Sjmallett uint64_t mbox_nmp : 1; 2656215976Sjmallett uint64_t mbox_fmp : 1; 2657215976Sjmallett uint64_t mbox_sp : 1; 2658215976Sjmallett uint64_t id_psd : 1; 2659215976Sjmallett uint64_t id_nmp : 1; 2660215976Sjmallett uint64_t id_fmp : 1; 2661215976Sjmallett uint64_t id_sp : 1; 2662215976Sjmallett uint64_t ctlr_nmp : 1; 2663215976Sjmallett uint64_t ctlr_fmp : 1; 2664215976Sjmallett uint64_t ctlr_sp : 1; 2665215976Sjmallett uint64_t xmbox_sp : 1; 2666215976Sjmallett uint64_t reserved_16_63 : 48; 2667215976Sjmallett#endif 2668215976Sjmallett } s; 2669215976Sjmallett struct cvmx_sriox_omsg_sp_mrx_s cn63xx; 2670215976Sjmallett struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1; 2671215976Sjmallett}; 2672215976Sjmalletttypedef union cvmx_sriox_omsg_sp_mrx cvmx_sriox_omsg_sp_mrx_t; 2673215976Sjmallett 2674215976Sjmallett/** 2675215976Sjmallett * cvmx_srio#_prio#_in_use 2676215976Sjmallett * 2677215976Sjmallett * SRIO_PRIO[0:3]_IN_USE = S2M PRIORITY FIFO IN USE COUNTS (Pass 2) 2678215976Sjmallett * 2679215976Sjmallett * SRIO S2M Priority X FIFO Inuse counts 2680215976Sjmallett * 2681215976Sjmallett * Notes: 2682215976Sjmallett * These registers provide status information on the number of read/write requests pending in the S2M 2683215976Sjmallett * Priority FIFOs. The information can be used to help determine when an S2M_TYPE register can be 2684215976Sjmallett * reallocated. For example, if an S2M_TYPE is used N times in a DMA write operation and the DMA has 2685215976Sjmallett * completed. The register corresponding to the RD/WR_PRIOR of the S2M_TYPE can be read to determine 2686215976Sjmallett * the START_CNT and then can be polled to see if the END_CNT equals the START_CNT or at least 2687215976Sjmallett * START_CNT+N. These registers can be accessed regardless of the value of SRIO(0..1)_STATUS_REG.ACCESS 2688215976Sjmallett * but are reset by either the MAC or Core being reset. 2689215976Sjmallett * 2690215976Sjmallett * Clk_Rst: SRIO(0..1)_PRIO[0:3]_IN_USE sclk srst_n, hrst_n 2691215976Sjmallett */ 2692215976Sjmallettunion cvmx_sriox_priox_in_use 2693215976Sjmallett{ 2694215976Sjmallett uint64_t u64; 2695215976Sjmallett struct cvmx_sriox_priox_in_use_s 2696215976Sjmallett { 2697215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2698215976Sjmallett uint64_t reserved_32_63 : 32; 2699215976Sjmallett uint64_t end_cnt : 16; /**< Count of Packets with S2M_TYPES completed for this 2700215976Sjmallett Priority X FIFO */ 2701215976Sjmallett uint64_t start_cnt : 16; /**< Count of Packets with S2M_TYPES started for this 2702215976Sjmallett Priority X FIFO */ 2703215976Sjmallett#else 2704215976Sjmallett uint64_t start_cnt : 16; 2705215976Sjmallett uint64_t end_cnt : 16; 2706215976Sjmallett uint64_t reserved_32_63 : 32; 2707215976Sjmallett#endif 2708215976Sjmallett } s; 2709215976Sjmallett struct cvmx_sriox_priox_in_use_s cn63xx; 2710215976Sjmallett}; 2711215976Sjmalletttypedef union cvmx_sriox_priox_in_use cvmx_sriox_priox_in_use_t; 2712215976Sjmallett 2713215976Sjmallett/** 2714215976Sjmallett * cvmx_srio#_rx_bell 2715215976Sjmallett * 2716215976Sjmallett * SRIO_RX_BELL = SRIO Receive Doorbell 2717215976Sjmallett * 2718215976Sjmallett * The SRIO Incoming (RX) Doorbell 2719215976Sjmallett * 2720215976Sjmallett * Notes: 2721215976Sjmallett * This register contains the SRIO Information, Device ID, Transaction Type and Priority of the 2722215976Sjmallett * incoming Doorbell Transaction as well as the number of transactions waiting to be read. Reading 2723215976Sjmallett * this register causes a Doorbell to be removed from the RX Bell FIFO and the COUNT to be 2724215976Sjmallett * decremented. If the COUNT is zero then the FIFO is empty and the other fields should be 2725215976Sjmallett * considered invalid. When the FIFO is full an ERROR is automatically issued. The RXBELL Interrupt 2726215976Sjmallett * can be used to detect posts to this FIFO. 2727215976Sjmallett * 2728215976Sjmallett * Clk_Rst: SRIO(0..1)_RX_BELL hclk hrst_n 2729215976Sjmallett */ 2730215976Sjmallettunion cvmx_sriox_rx_bell 2731215976Sjmallett{ 2732215976Sjmallett uint64_t u64; 2733215976Sjmallett struct cvmx_sriox_rx_bell_s 2734215976Sjmallett { 2735215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2736215976Sjmallett uint64_t reserved_48_63 : 16; 2737215976Sjmallett uint64_t data : 16; /**< Information field from received doorbell */ 2738215976Sjmallett uint64_t src_id : 16; /**< Doorbell Source Device ID[15:0] */ 2739215976Sjmallett uint64_t count : 8; /**< RX Bell FIFO Count 2740215976Sjmallett Note: Count must be > 0 for entry to be valid. */ 2741215976Sjmallett uint64_t reserved_5_7 : 3; 2742215976Sjmallett uint64_t dest_id : 1; /**< Destination Device ID 0=Primary, 1=Secondary */ 2743215976Sjmallett uint64_t id16 : 1; /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */ 2744215976Sjmallett uint64_t reserved_2_2 : 1; 2745215976Sjmallett uint64_t priority : 2; /**< Doorbell Priority */ 2746215976Sjmallett#else 2747215976Sjmallett uint64_t priority : 2; 2748215976Sjmallett uint64_t reserved_2_2 : 1; 2749215976Sjmallett uint64_t id16 : 1; 2750215976Sjmallett uint64_t dest_id : 1; 2751215976Sjmallett uint64_t reserved_5_7 : 3; 2752215976Sjmallett uint64_t count : 8; 2753215976Sjmallett uint64_t src_id : 16; 2754215976Sjmallett uint64_t data : 16; 2755215976Sjmallett uint64_t reserved_48_63 : 16; 2756215976Sjmallett#endif 2757215976Sjmallett } s; 2758215976Sjmallett struct cvmx_sriox_rx_bell_s cn63xx; 2759215976Sjmallett struct cvmx_sriox_rx_bell_s cn63xxp1; 2760215976Sjmallett}; 2761215976Sjmalletttypedef union cvmx_sriox_rx_bell cvmx_sriox_rx_bell_t; 2762215976Sjmallett 2763215976Sjmallett/** 2764215976Sjmallett * cvmx_srio#_rx_bell_seq 2765215976Sjmallett * 2766215976Sjmallett * SRIO_RX_BELL_SEQ = SRIO Receive Doorbell Sequence Count 2767215976Sjmallett * 2768215976Sjmallett * The SRIO Incoming (RX) Doorbell Sequence Count 2769215976Sjmallett * 2770215976Sjmallett * Notes: 2771215976Sjmallett * This register contains the value of the sequence counter when the doorbell was received and a 2772215976Sjmallett * shadow copy of the Bell FIFO Count that can be read without emptying the FIFO. This register must 2773215976Sjmallett * be read prior to SRIO(0..1)_RX_BELL to guarantee that the information corresponds to the correct 2774215976Sjmallett * doorbell. 2775215976Sjmallett * 2776215976Sjmallett * Clk_Rst: SRIO(0..1)_RX_BELL_SEQ hclk hrst_n 2777215976Sjmallett */ 2778215976Sjmallettunion cvmx_sriox_rx_bell_seq 2779215976Sjmallett{ 2780215976Sjmallett uint64_t u64; 2781215976Sjmallett struct cvmx_sriox_rx_bell_seq_s 2782215976Sjmallett { 2783215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2784215976Sjmallett uint64_t reserved_40_63 : 24; 2785215976Sjmallett uint64_t count : 8; /**< RX Bell FIFO Count 2786215976Sjmallett Note: Count must be > 0 for entry to be valid. */ 2787215976Sjmallett uint64_t seq : 32; /**< 32-bit Sequence \# associated with Doorbell Message */ 2788215976Sjmallett#else 2789215976Sjmallett uint64_t seq : 32; 2790215976Sjmallett uint64_t count : 8; 2791215976Sjmallett uint64_t reserved_40_63 : 24; 2792215976Sjmallett#endif 2793215976Sjmallett } s; 2794215976Sjmallett struct cvmx_sriox_rx_bell_seq_s cn63xx; 2795215976Sjmallett struct cvmx_sriox_rx_bell_seq_s cn63xxp1; 2796215976Sjmallett}; 2797215976Sjmalletttypedef union cvmx_sriox_rx_bell_seq cvmx_sriox_rx_bell_seq_t; 2798215976Sjmallett 2799215976Sjmallett/** 2800215976Sjmallett * cvmx_srio#_rx_status 2801215976Sjmallett * 2802215976Sjmallett * SRIO_RX_STATUS = SRIO Inbound Credits/Response Status 2803215976Sjmallett * 2804215976Sjmallett * Specifies the current number of credits/responses by SRIO for Inbound Traffic 2805215976Sjmallett * 2806215976Sjmallett * Notes: 2807215976Sjmallett * Debug Register specifying the number of credits/responses currently in use for Inbound Traffic. 2808215976Sjmallett * The maximum value for COMP, N_POST and POST is set in SRIO(0..1)_TLP_CREDITS. When all inbound traffic 2809215976Sjmallett * has stopped the values should eventually return to the maximum values. The RTN_PR[3:1] entry 2810215976Sjmallett * counts should eventually return to the reset values. 2811215976Sjmallett * 2812215976Sjmallett * Clk_Rst: SRIO(0..1)_RX_STATUS hclk hrst_n 2813215976Sjmallett */ 2814215976Sjmallettunion cvmx_sriox_rx_status 2815215976Sjmallett{ 2816215976Sjmallett uint64_t u64; 2817215976Sjmallett struct cvmx_sriox_rx_status_s 2818215976Sjmallett { 2819215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2820215976Sjmallett uint64_t rtn_pr3 : 8; /**< Number of pending Priority 3 Response Entries. */ 2821215976Sjmallett uint64_t rtn_pr2 : 8; /**< Number of pending Priority 2 Response Entries. */ 2822215976Sjmallett uint64_t rtn_pr1 : 8; /**< Number of pending Priority 1 Response Entries. */ 2823215976Sjmallett uint64_t reserved_28_39 : 12; 2824215976Sjmallett uint64_t mbox : 4; /**< Credits for Mailbox Data used in M2S. */ 2825215976Sjmallett uint64_t comp : 8; /**< Credits for Read Completions used in M2S. */ 2826215976Sjmallett uint64_t reserved_13_15 : 3; 2827215976Sjmallett uint64_t n_post : 5; /**< Credits for Read Requests used in M2S. */ 2828215976Sjmallett uint64_t post : 8; /**< Credits for Write Request Postings used in M2S. */ 2829215976Sjmallett#else 2830215976Sjmallett uint64_t post : 8; 2831215976Sjmallett uint64_t n_post : 5; 2832215976Sjmallett uint64_t reserved_13_15 : 3; 2833215976Sjmallett uint64_t comp : 8; 2834215976Sjmallett uint64_t mbox : 4; 2835215976Sjmallett uint64_t reserved_28_39 : 12; 2836215976Sjmallett uint64_t rtn_pr1 : 8; 2837215976Sjmallett uint64_t rtn_pr2 : 8; 2838215976Sjmallett uint64_t rtn_pr3 : 8; 2839215976Sjmallett#endif 2840215976Sjmallett } s; 2841215976Sjmallett struct cvmx_sriox_rx_status_s cn63xx; 2842215976Sjmallett struct cvmx_sriox_rx_status_s cn63xxp1; 2843215976Sjmallett}; 2844215976Sjmalletttypedef union cvmx_sriox_rx_status cvmx_sriox_rx_status_t; 2845215976Sjmallett 2846215976Sjmallett/** 2847215976Sjmallett * cvmx_srio#_s2m_type# 2848215976Sjmallett * 2849215976Sjmallett * SRIO_S2M_TYPE[0:15] = SLI to SRIO MAC Operation Type 2850215976Sjmallett * 2851215976Sjmallett * SRIO Operation Type selected by PP or DMA Accesses 2852215976Sjmallett * 2853215976Sjmallett * Notes: 2854215976Sjmallett * This CSR table specifies how to convert a SLI/DPI MAC read or write into sRIO operations. 2855215976Sjmallett * Each SLI/DPI read or write access supplies a 64-bit address (MACADD[63:0]), 2-bit ADDRTYPE, and 2856215976Sjmallett * 2-bit endian-swap. This SRIO*_S2M_TYPE* CSR description specifies a table with 16 CSRs. SRIO 2857215976Sjmallett * selects one of the table entries with TYPEIDX[3:0], which it creates from the SLI/DPI MAC memory 2858215976Sjmallett * space read or write as follows: 2859215976Sjmallett * TYPEIDX[1:0] = ADDRTYPE[1:0] (ADDRTYPE[1] is no-snoop to the PCIe MAC, 2860215976Sjmallett * ADDRTYPE[0] is relaxed-ordering to the PCIe MAC) 2861215976Sjmallett * TYPEIDX[2] = MACADD[50] 2862215976Sjmallett * TYPEIDX[3] = MACADD[59] 2863215976Sjmallett * 2864215976Sjmallett * Clk_Rst: SRIO(0..1)_S2M_TYPE[0:15] hclk hrst_n 2865215976Sjmallett */ 2866215976Sjmallettunion cvmx_sriox_s2m_typex 2867215976Sjmallett{ 2868215976Sjmallett uint64_t u64; 2869215976Sjmallett struct cvmx_sriox_s2m_typex_s 2870215976Sjmallett { 2871215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2872215976Sjmallett uint64_t reserved_19_63 : 45; 2873215976Sjmallett uint64_t wr_op : 3; /**< sRIO operation for SLI/DPI writes 2874215976Sjmallett 2875215976Sjmallett SLI/DPI hardware break MAC memory space writes 2876215976Sjmallett that they generate into pieces of maximum size 2877215976Sjmallett 256B. For NWRITE/NWRITE_R/SWRITE WR_OP variants 2878215976Sjmallett below, SRIO will, if necessary to obey sRIO 2879215976Sjmallett requirements, automatically break the write into 2880215976Sjmallett even smaller writes. The same is not true for 2881215976Sjmallett MAINTENANCE writes and port-writes. Additional 2882215976Sjmallett SW/usage restrictions are required for these 2883215976Sjmallett MAINTENANCE WR_OP's to work correctly. SW must 2884215976Sjmallett restrict the alignment and length of DPI pointers, 2885215976Sjmallett limit the store sizes that the cores issue, and 2886215976Sjmallett possibly also set SLI_MEM_ACCESS_SUBID*[NMERGE] 2887215976Sjmallett so that all MAC memory space writes with 2888215976Sjmallett MAINTENANCE write and port-write WR_OP's can be 2889215976Sjmallett serviced in a single sRIO operation. 2890215976Sjmallett 2891215976Sjmallett SRIO always sends the write data (64-bit) words 2892215976Sjmallett out in order. 2893215976Sjmallett 2894215976Sjmallett WR_OP = 0 = Normal Write (NWRITE) 2895215976Sjmallett SRIO breaks a MAC memory space write into 2896215976Sjmallett the minimum number of required sRIO NWRITE 2897215976Sjmallett operations. This will be 1-5 total NWRITEs, 2898215976Sjmallett depending on endian-swap, alignment, and 2899215976Sjmallett length. 2900215976Sjmallett 2901215976Sjmallett WR_OP = 1 = Normal Write w/Response (NWRITE_R) 2902215976Sjmallett SRIO breaks a MAC memory space write into 2903215976Sjmallett the minimum number of required sRIO 2904215976Sjmallett NWRITE_R operations. This will be 1-5 total 2905215976Sjmallett NWRITE_R's, depending on endian-swap, 2906215976Sjmallett alignment, and length. 2907215976Sjmallett 2908215976Sjmallett SRIO sets SRIO*_INT_REG[WR_DONE] after it 2909215976Sjmallett receives the DONE response for the last 2910215976Sjmallett NWRITE_R sent. 2911215976Sjmallett 2912215976Sjmallett WR_OP = 2 = NWRITE, Streaming write (SWRITE), 2913215976Sjmallett NWRITE 2914215976Sjmallett SRIO attempts to turn the MAC memory space 2915215976Sjmallett write into an SWRITE operation. There will 2916215976Sjmallett be 1-5 total sRIO operations (0-2 NWRITE's 2917215976Sjmallett followed by 0-1 SWRITE's followed by 0-2 2918215976Sjmallett NWRITE's) generated to complete the MAC 2919215976Sjmallett memory space write, depending on 2920215976Sjmallett endian-swap, alignment, and length. 2921215976Sjmallett 2922215976Sjmallett If the starting address is not 64-bit 2923215976Sjmallett aligned, SRIO first creates 1-4 NWRITE's to 2924215976Sjmallett either align it or complete the write. Then 2925215976Sjmallett SRIO creates a SWRITE including all aligned 2926215976Sjmallett 64-bit words. (SRIO won't create an SWRITE 2927215976Sjmallett when there are none.) If store data 2928215976Sjmallett remains, SRIO finally creates another 1 or 2929215976Sjmallett 2 NWRITE's. 2930215976Sjmallett 2931215976Sjmallett WR_OP = 3 = NWRITE, SWRITE, NWRITE_R 2932215976Sjmallett SRIO attempts to turn the MAC memory space 2933215976Sjmallett write into an SWRITE operation followed by 2934215976Sjmallett a NWRITE_R operation. The last operation 2935215976Sjmallett is always NWRITE_R. There will be 1-5 2936215976Sjmallett total sRIO operations (0-2 NWRITE's, 2937215976Sjmallett followed by 0-1 SWRITE, followed by 1-4 2938215976Sjmallett NWRITE_R's) generated to service the MAC 2939215976Sjmallett memory space write, depending on 2940215976Sjmallett endian-swap, alignment, and length. 2941215976Sjmallett 2942215976Sjmallett If the write is contained in one aligned 2943215976Sjmallett 64-bit word, SRIO will completely service 2944215976Sjmallett the MAC memory space write with 1-4 2945215976Sjmallett NWRITE_R's. 2946215976Sjmallett 2947215976Sjmallett Otherwise, if the write spans multiple 2948215976Sjmallett words, SRIO services the write as follows. 2949215976Sjmallett First, if the start of the write is not 2950215976Sjmallett word-aligned, SRIO creates 1 or 2 NWRITE's 2951215976Sjmallett to align it. Then SRIO creates an SWRITE 2952215976Sjmallett that includes all aligned 64-bit words, 2953215976Sjmallett leaving data for the final NWRITE_R(s). 2954215976Sjmallett (SRIO won't create the SWRITE when there is 2955215976Sjmallett no data for it.) Then SRIO finally creates 2956215976Sjmallett 1 or 2 NWRITE_R's. 2957215976Sjmallett 2958215976Sjmallett In any case, SRIO sets 2959215976Sjmallett SRIO*_INT_REG[WR_DONE] after it receives 2960215976Sjmallett the DONE response for the last NWRITE_R 2961215976Sjmallett sent. 2962215976Sjmallett 2963215976Sjmallett WR_OP = 4 = NWRITE, NWRITE_R 2964215976Sjmallett SRIO attempts to turn the MAC memory space 2965215976Sjmallett write into an NWRITE operation followed by 2966215976Sjmallett a NWRITE_R operation. The last operation 2967215976Sjmallett is always NWRITE_R. There will be 1-5 2968215976Sjmallett total sRIO operations (0-3 NWRITE's 2969215976Sjmallett followed by 1-4 NWRITE_R's) generated to 2970215976Sjmallett service the MAC memory space write, 2971215976Sjmallett depending on endian-swap, alignment, and 2972215976Sjmallett length. 2973215976Sjmallett 2974215976Sjmallett If the write is contained in one aligned 2975215976Sjmallett 64-bit word, SRIO will completely service 2976215976Sjmallett the MAC memory space write with 1-4 2977215976Sjmallett NWRITE_R's. 2978215976Sjmallett 2979215976Sjmallett Otherwise, if the write spans multiple 2980215976Sjmallett words, SRIO services the write as follows. 2981215976Sjmallett First, if the start of the write is not 2982215976Sjmallett word-aligned, SRIO creates 1 or 2 NWRITE's 2983215976Sjmallett to align it. Then SRIO creates an NWRITE 2984215976Sjmallett that includes all aligned 64-bit words, 2985215976Sjmallett leaving data for the final NWRITE_R(s). 2986215976Sjmallett (SRIO won't create this NWRITE when there 2987215976Sjmallett is no data for it.) Then SRIO finally 2988215976Sjmallett creates 1 or 2 NWRITE_R's. 2989215976Sjmallett 2990215976Sjmallett In any case, SRIO sets 2991215976Sjmallett SRIO*_INT_REG[WR_DONE] after it receives 2992215976Sjmallett the DONE response for the last NWRITE_R 2993215976Sjmallett sent. 2994215976Sjmallett 2995215976Sjmallett WR_OP = 5 = Reserved 2996215976Sjmallett 2997215976Sjmallett WR_OP = 6 = Maintenance Write 2998215976Sjmallett - SRIO will create one sRIO MAINTENANCE write 2999215976Sjmallett operation to service the MAC memory space 3000215976Sjmallett write 3001215976Sjmallett - IAOW_SEL must be zero. (see description 3002215976Sjmallett below.) 3003215976Sjmallett - MDS must be zero. (MDS is MACADD[63:62] - 3004215976Sjmallett see IAOW_SEL description below.) 3005215976Sjmallett - Hop Cnt is MACADD[31:24]/SRIOAddress[31:24] 3006215976Sjmallett - MACADD[23:0]/SRIOAddress[23:0] selects 3007215976Sjmallett maintenance register (i.e. config_offset) 3008215976Sjmallett - sRIODestID[15:0] is MACADD[49:34]. 3009215976Sjmallett (MACADD[49:42] unused when ID16=0) 3010215976Sjmallett - Write size/alignment must obey sRIO rules 3011215976Sjmallett (4, 8, 16, 24, 32, 40, 48, 56 and 64 byte 3012215976Sjmallett lengths allowed) 3013215976Sjmallett 3014215976Sjmallett WR_OP = 7 = Maintenance Port Write 3015215976Sjmallett - SRIO will create one sRIO MAINTENANCE port 3016215976Sjmallett write operation to service the MAC memory 3017215976Sjmallett space write 3018215976Sjmallett - IAOW_SEL must be zero. (see description 3019215976Sjmallett below.) 3020215976Sjmallett - MDS must be zero. (MDS is MACADD[63:62] - 3021215976Sjmallett see IAOW_SEL description below.) 3022215976Sjmallett - Hop Cnt is MACADD[31:24]/sRIOAddress[31:24] 3023215976Sjmallett - MACADD[23:0]/sRIOAddress[23:0] MBZ 3024215976Sjmallett (config_offset field reserved by sRIO) 3025215976Sjmallett - sRIODestID[15:0] is MACADD[49:34]. 3026215976Sjmallett (MACADD[49:42] unused when ID16=0) 3027215976Sjmallett - Write size/alignment must obey sRIO rules 3028215976Sjmallett (4, 8, 16, 24, 32, 40, 48, 56 and 64 byte 3029215976Sjmallett lengths allowed) */ 3030215976Sjmallett uint64_t reserved_15_15 : 1; 3031215976Sjmallett uint64_t rd_op : 3; /**< sRIO operation for SLI/DPI reads 3032215976Sjmallett 3033215976Sjmallett SLI/DPI hardware and sRIO configuration 3034215976Sjmallett restrictions guarantee that SRIO can service any 3035215976Sjmallett MAC memory space read that it receives from SLI/DPI 3036215976Sjmallett with a single NREAD, assuming that RD_OP selects 3037215976Sjmallett NREAD. DPI will break a read into multiple MAC 3038215976Sjmallett memory space reads to ensure this holds. The same 3039215976Sjmallett is not true for the ATOMIC and MAINTENANCE RD_OP 3040215976Sjmallett values. Additional SW/usage restrictions are 3041215976Sjmallett required for ATOMIC and MAINTENANCE RD_OP to work 3042215976Sjmallett correctly. SW must restrict the alignment and 3043215976Sjmallett length of DPI pointers and limit the load sizes 3044215976Sjmallett that the cores issue such that all MAC memory space 3045215976Sjmallett reads with ATOMIC and MAINTENANCE RD_OP's can be 3046215976Sjmallett serviced in a single sRIO operation. 3047215976Sjmallett 3048215976Sjmallett RD_OP = 0 = Normal Read (NREAD) 3049215976Sjmallett - SRIO will create one sRIO NREAD 3050215976Sjmallett operation to service the MAC memory 3051215976Sjmallett space read 3052215976Sjmallett - Read size/alignment must obey sRIO rules 3053215976Sjmallett (up to 256 byte lengths). (This requirement 3054215976Sjmallett is guaranteed by SLI/DPI usage restrictions 3055215976Sjmallett and configuration.) 3056215976Sjmallett 3057215976Sjmallett RD_OP = 1 = Reserved 3058215976Sjmallett 3059215976Sjmallett RD_OP = 2 = Atomic Set 3060215976Sjmallett - SRIO will create one sRIO ATOMIC set 3061215976Sjmallett operation to service the MAC memory 3062215976Sjmallett space read 3063215976Sjmallett - Read size/alignment must obey sRIO rules 3064215976Sjmallett (1, 2, and 4 byte lengths allowed) 3065215976Sjmallett 3066215976Sjmallett RD_OP = 3 = Atomic Clear 3067215976Sjmallett - SRIO will create one sRIO ATOMIC clr 3068215976Sjmallett operation to service the MAC memory 3069215976Sjmallett space read 3070215976Sjmallett - Read size/alignment must obey sRIO rules 3071215976Sjmallett (1, 2, and 4 byte lengths allowed) 3072215976Sjmallett 3073215976Sjmallett RD_OP = 4 = Atomic Increment 3074215976Sjmallett - SRIO will create one sRIO ATOMIC inc 3075215976Sjmallett operation to service the MAC memory 3076215976Sjmallett space read 3077215976Sjmallett - Read size/alignment must obey sRIO rules 3078215976Sjmallett (1, 2, and 4 byte lengths allowed) 3079215976Sjmallett 3080215976Sjmallett RD_OP = 5 = Atomic Decrement 3081215976Sjmallett - SRIO will create one sRIO ATOMIC dec 3082215976Sjmallett operation to service the MAC memory 3083215976Sjmallett space read 3084215976Sjmallett - Read size/alignment must obey sRIO rules 3085215976Sjmallett (1, 2, and 4 byte lengths allowed) 3086215976Sjmallett 3087215976Sjmallett RD_OP = 6 = Maintenance Read 3088215976Sjmallett - SRIO will create one sRIO MAINTENANCE read 3089215976Sjmallett operation to service the MAC memory 3090215976Sjmallett space read 3091215976Sjmallett - IAOW_SEL must be zero. (see description 3092215976Sjmallett below.) 3093215976Sjmallett - MDS must be zero. (MDS is MACADD[63:62] - 3094215976Sjmallett see IAOW_SEL description below.) 3095215976Sjmallett - Hop Cnt is MACADD[31:24]/sRIOAddress[31:24] 3096215976Sjmallett - MACADD[23:0]/sRIOAddress[23:0] selects 3097215976Sjmallett maintenance register (i.e. config_offset) 3098215976Sjmallett - sRIODestID[15:0] is MACADD[49:34]. 3099215976Sjmallett (MACADD[49:42] unused when ID16=0) 3100215976Sjmallett - Read size/alignment must obey sRIO rules 3101215976Sjmallett (4, 8, 16, 32 and 64 byte lengths allowed) 3102215976Sjmallett 3103215976Sjmallett RD_OP = 7 = Reserved */ 3104215976Sjmallett uint64_t wr_prior : 2; /**< Transaction Priority 0-3 used for writes */ 3105215976Sjmallett uint64_t rd_prior : 2; /**< Transaction Priority 0-3 used for reads/ATOMICs */ 3106215976Sjmallett uint64_t reserved_6_7 : 2; 3107215976Sjmallett uint64_t src_id : 1; /**< Source ID 3108215976Sjmallett 3109215976Sjmallett 0 = Use Primary ID as Source ID 3110215976Sjmallett (SRIOMAINT*_PRI_DEV_ID[ID16 or ID8], depending 3111215976Sjmallett on SRIO TT ID (i.e. ID16 below)) 3112215976Sjmallett 3113215976Sjmallett 1 = Use Secondary ID as Source ID 3114215976Sjmallett (SRIOMAINT*_SEC_DEV_ID[ID16 or ID8], depending 3115215976Sjmallett on SRIO TT ID (i.e. ID16 below)) */ 3116215976Sjmallett uint64_t id16 : 1; /**< SRIO TT ID 0=8bit, 1=16-bit 3117215976Sjmallett IAOW_SEL must not be 2 when ID16=1. */ 3118215976Sjmallett uint64_t reserved_2_3 : 2; 3119215976Sjmallett uint64_t iaow_sel : 2; /**< Internal Address Offset Width Select 3120215976Sjmallett 3121215976Sjmallett IAOW_SEL determines how to convert the 3122215976Sjmallett MACADD[63:62,58:51,49:0] recieved from SLI/DPI with 3123215976Sjmallett read/write into an sRIO address (sRIOAddress[...]) 3124215976Sjmallett and sRIO destination ID (sRIODestID[...]). The sRIO 3125215976Sjmallett address width mode (SRIOMAINT_PE_LLC[EX_ADDR]) and 3126215976Sjmallett ID16, determine the width of the sRIO address and 3127215976Sjmallett ID in the outgoing request(s), respectively. 3128215976Sjmallett 3129215976Sjmallett MACADD[61:60] is always unused. 3130215976Sjmallett 3131215976Sjmallett MACADD[59] is always TYPEIDX[3] 3132215976Sjmallett MACADD[50] is always TYPEIDX[2] 3133215976Sjmallett (TYPEIDX[3:0] selects one of these 3134215976Sjmallett SRIO*_S2M_TYPE* table entries.) 3135215976Sjmallett 3136215976Sjmallett MACADD[17:0] always becomes sRIOAddress[17:0]. 3137215976Sjmallett 3138215976Sjmallett IAOW_SEL = 0 = 34-bit Address Offset 3139215976Sjmallett 3140215976Sjmallett Must be used when sRIO link is in 34-bit 3141215976Sjmallett address width mode. 3142215976Sjmallett When sRIO is in 50-bit address width mode, 3143215976Sjmallett sRIOAddress[49:34]=0 in the outgoing request. 3144215976Sjmallett When sRIO is in 66-bit address width mode, 3145215976Sjmallett sRIOAddress[65:34]=0 in the outgoing request. 3146215976Sjmallett 3147215976Sjmallett Usage of the SLI/DPI MAC address when 3148215976Sjmallett IAOW_SEL = 0: 3149215976Sjmallett MACADD[63:62] = Multi-Device Swap (MDS) 3150215976Sjmallett MDS value affects MACADD[49:18] usage 3151215976Sjmallett MACADD[58:51] => unused 3152215976Sjmallett MACADD[49:18] usage depends on MDS value 3153215976Sjmallett MDS = 0 3154215976Sjmallett MACADD[49:34] => sRIODestID[15:0] 3155215976Sjmallett (MACADD[49:42] unused when ID16=0) 3156215976Sjmallett MACADD[33:18] => sRIOAddress[33:18] 3157215976Sjmallett MDS = 1 3158215976Sjmallett MACADD[49:42] => sRIODestID[15:8] 3159215976Sjmallett (MACADD[49:42] unused when ID16 = 0) 3160215976Sjmallett MACADD[41:34] => sRIOAddress[33:26] 3161215976Sjmallett MACADD[33:26] => sRIODestID[7:0] 3162215976Sjmallett MACADD[25:18] => sRIOAddress[25:18] 3163215976Sjmallett MDS = 2 3164215976Sjmallett ID16 must be one. 3165215976Sjmallett MACADD[49:34] => sRIOAddress[33:18] 3166215976Sjmallett MACADD[33:18] => sRIODestID[15:0] 3167215976Sjmallett MDS = 3 = Reserved 3168215976Sjmallett 3169215976Sjmallett IAOW_SEL = 1 = 42-bit Address Offset 3170215976Sjmallett 3171215976Sjmallett Must not be used when sRIO link is in 34-bit 3172215976Sjmallett address width mode. 3173215976Sjmallett When sRIO is in 50-bit address width mode, 3174215976Sjmallett sRIOAddress[49:42]=0 in the outgoing request. 3175215976Sjmallett When sRIO is in 66-bit address width mode, 3176215976Sjmallett sRIOAddress[65:42]=0 in the outgoing request. 3177215976Sjmallett 3178215976Sjmallett Usage of the SLI/DPI MAC address when 3179215976Sjmallett IAOW_SEL = 1: 3180215976Sjmallett MACADD[63:62] => Multi-Device Swap (MDS) 3181215976Sjmallett MDS value affects MACADD[58:51,49:42,33:18] 3182215976Sjmallett use 3183215976Sjmallett MACADD[41:34] => sRIOAddress[41:34] 3184215976Sjmallett MACADD[58:51,49:42,33:18] usage depends on 3185215976Sjmallett MDS value: 3186215976Sjmallett MDS = 0 3187215976Sjmallett MACADD[58:51] => sRIODestID[15:8] 3188215976Sjmallett MACADD[49:42] => sRIODestID[7:0] 3189215976Sjmallett (MACADD[58:51] unused when ID16=0) 3190215976Sjmallett MACADD[33:18] => sRIOAddress[33:18] 3191215976Sjmallett MDS = 1 3192215976Sjmallett MACADD[58:51] => sRIODestID[15:8] 3193215976Sjmallett (MACADD[58:51] unused when ID16 = 0) 3194215976Sjmallett MACADD[49:42] => sRIOAddress[33:26] 3195215976Sjmallett MACADD[33:26] => sRIODestID[7:0] 3196215976Sjmallett MACADD[25:18] => sRIOAddress[25:18] 3197215976Sjmallett MDS = 2 3198215976Sjmallett ID16 must be one. 3199215976Sjmallett MACADD[58:51] => sRIOAddress[33:26] 3200215976Sjmallett MACADD[49:42] => sRIOAddress[25:18] 3201215976Sjmallett MACADD[33:18] => sRIODestID[15:0] 3202215976Sjmallett MDS = 3 = Reserved 3203215976Sjmallett 3204215976Sjmallett IAOW_SEL = 2 = 50-bit Address Offset 3205215976Sjmallett 3206215976Sjmallett Must not be used when sRIO link is in 34-bit 3207215976Sjmallett address width mode. 3208215976Sjmallett Must not be used when ID16=1. 3209215976Sjmallett When sRIO is in 66-bit address width mode, 3210215976Sjmallett sRIOAddress[65:50]=0 in the outgoing request. 3211215976Sjmallett 3212215976Sjmallett Usage of the SLI/DPI MAC address when 3213215976Sjmallett IAOW_SEL = 2: 3214215976Sjmallett MACADD[63:62] => Multi-Device Swap (MDS) 3215215976Sjmallett MDS value affects MACADD[58:51,33:26] use 3216215976Sjmallett MDS value 3 is reserved 3217215976Sjmallett MACADD[49:34] => sRIOAddress[49:34] 3218215976Sjmallett MACADD[25:18] => sRIOAddress[25:18] 3219215976Sjmallett MACADD[58:51,33:26] usage depends on 3220215976Sjmallett MDS value: 3221215976Sjmallett MDS = 0 3222215976Sjmallett MACADD[58:51] => sRIODestID[7:0] 3223215976Sjmallett MACADD[33:26] => sRIOAddress[33:26] 3224215976Sjmallett MDS = 1 3225215976Sjmallett MACADD[58:51] => sRIOAddress[33:26] 3226215976Sjmallett MACADD[33:26] => sRIODestID[7:0] 3227215976Sjmallett MDS = 2 = Reserved 3228215976Sjmallett MDS = 3 = Reserved 3229215976Sjmallett 3230215976Sjmallett IAOW_SEL = 3 = Reserved */ 3231215976Sjmallett#else 3232215976Sjmallett uint64_t iaow_sel : 2; 3233215976Sjmallett uint64_t reserved_2_3 : 2; 3234215976Sjmallett uint64_t id16 : 1; 3235215976Sjmallett uint64_t src_id : 1; 3236215976Sjmallett uint64_t reserved_6_7 : 2; 3237215976Sjmallett uint64_t rd_prior : 2; 3238215976Sjmallett uint64_t wr_prior : 2; 3239215976Sjmallett uint64_t rd_op : 3; 3240215976Sjmallett uint64_t reserved_15_15 : 1; 3241215976Sjmallett uint64_t wr_op : 3; 3242215976Sjmallett uint64_t reserved_19_63 : 45; 3243215976Sjmallett#endif 3244215976Sjmallett } s; 3245215976Sjmallett struct cvmx_sriox_s2m_typex_s cn63xx; 3246215976Sjmallett struct cvmx_sriox_s2m_typex_s cn63xxp1; 3247215976Sjmallett}; 3248215976Sjmalletttypedef union cvmx_sriox_s2m_typex cvmx_sriox_s2m_typex_t; 3249215976Sjmallett 3250215976Sjmallett/** 3251215976Sjmallett * cvmx_srio#_seq 3252215976Sjmallett * 3253215976Sjmallett * SRIO_SEQ = SRIO Sequence Count 3254215976Sjmallett * 3255215976Sjmallett * The SRIO Sequence Count 3256215976Sjmallett * 3257215976Sjmallett * Notes: 3258215976Sjmallett * This register contains the current value of the sequence counter. This counter increments every 3259215976Sjmallett * time a doorbell or the first segment of a message is accepted. 3260215976Sjmallett * 3261215976Sjmallett * Clk_Rst: SRIO(0..1)_SEQ hclk hrst_n 3262215976Sjmallett */ 3263215976Sjmallettunion cvmx_sriox_seq 3264215976Sjmallett{ 3265215976Sjmallett uint64_t u64; 3266215976Sjmallett struct cvmx_sriox_seq_s 3267215976Sjmallett { 3268215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3269215976Sjmallett uint64_t reserved_32_63 : 32; 3270215976Sjmallett uint64_t seq : 32; /**< 32-bit Sequence \# */ 3271215976Sjmallett#else 3272215976Sjmallett uint64_t seq : 32; 3273215976Sjmallett uint64_t reserved_32_63 : 32; 3274215976Sjmallett#endif 3275215976Sjmallett } s; 3276215976Sjmallett struct cvmx_sriox_seq_s cn63xx; 3277215976Sjmallett struct cvmx_sriox_seq_s cn63xxp1; 3278215976Sjmallett}; 3279215976Sjmalletttypedef union cvmx_sriox_seq cvmx_sriox_seq_t; 3280215976Sjmallett 3281215976Sjmallett/** 3282215976Sjmallett * cvmx_srio#_status_reg 3283215976Sjmallett * 3284215976Sjmallett * SRIO_STATUS_REG = SRIO Status Register 3285215976Sjmallett * 3286215976Sjmallett * General status of the SRIO. 3287215976Sjmallett * 3288215976Sjmallett * Notes: 3289215976Sjmallett * The SRIO field displays if the port has been configured for SRIO operation. This register can be 3290215976Sjmallett * read regardless of whether the SRIO is selected or being reset. Although some other registers can 3291215976Sjmallett * be accessed while the ACCESS bit is zero (see individual registers for details), the majority of 3292215976Sjmallett * SRIO registers and all the SRIOMAINT registers can be used only when the ACCESS bit is asserted. 3293215976Sjmallett * 3294215976Sjmallett * Clk_Rst: SRIO(0..1)_STATUS_REG sclk srst_n 3295215976Sjmallett */ 3296215976Sjmallettunion cvmx_sriox_status_reg 3297215976Sjmallett{ 3298215976Sjmallett uint64_t u64; 3299215976Sjmallett struct cvmx_sriox_status_reg_s 3300215976Sjmallett { 3301215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3302215976Sjmallett uint64_t reserved_2_63 : 62; 3303215976Sjmallett uint64_t access : 1; /**< SRIO and SRIOMAINT Register Access. 3304215976Sjmallett 0 - Register Access Disabled. 3305215976Sjmallett 1 - Register Access Enabled. */ 3306215976Sjmallett uint64_t srio : 1; /**< SRIO Port Enabled. 3307215976Sjmallett 0 - All SRIO functions disabled. 3308215976Sjmallett 1 - All SRIO Operations permitted. */ 3309215976Sjmallett#else 3310215976Sjmallett uint64_t srio : 1; 3311215976Sjmallett uint64_t access : 1; 3312215976Sjmallett uint64_t reserved_2_63 : 62; 3313215976Sjmallett#endif 3314215976Sjmallett } s; 3315215976Sjmallett struct cvmx_sriox_status_reg_s cn63xx; 3316215976Sjmallett struct cvmx_sriox_status_reg_s cn63xxp1; 3317215976Sjmallett}; 3318215976Sjmalletttypedef union cvmx_sriox_status_reg cvmx_sriox_status_reg_t; 3319215976Sjmallett 3320215976Sjmallett/** 3321215976Sjmallett * cvmx_srio#_tag_ctrl 3322215976Sjmallett * 3323215976Sjmallett * SRIO_TAG_CTRL = SRIO TAG Control 3324215976Sjmallett * 3325215976Sjmallett * The SRIO TAG Control 3326215976Sjmallett * 3327215976Sjmallett * Notes: 3328215976Sjmallett * This register is used to show the state of the internal transaction tags and provides a manual 3329215976Sjmallett * reset of the outgoing tags. 3330215976Sjmallett * 3331215976Sjmallett * Clk_Rst: SRIO(0..1)_TAG_CTRL hclk hrst_n 3332215976Sjmallett */ 3333215976Sjmallettunion cvmx_sriox_tag_ctrl 3334215976Sjmallett{ 3335215976Sjmallett uint64_t u64; 3336215976Sjmallett struct cvmx_sriox_tag_ctrl_s 3337215976Sjmallett { 3338215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3339215976Sjmallett uint64_t reserved_17_63 : 47; 3340215976Sjmallett uint64_t o_clr : 1; /**< Manual OTAG Clear. This bit manually resets the 3341215976Sjmallett number of OTAGs back to 16 and loses track of any 3342215976Sjmallett outgoing packets. This function is automatically 3343215976Sjmallett performed when the SRIO MAC is reset but it may be 3344215976Sjmallett necessary after a chip reset while the MAC is in 3345215976Sjmallett operation. This bit must be set then cleared to 3346215976Sjmallett return to normal operation. Typically, Outgoing 3347215976Sjmallett SRIO packets must be halted 6 seconds prior to 3348215976Sjmallett this bit is set to avoid generating duplicate tags 3349215976Sjmallett and unexpected response errors. */ 3350215976Sjmallett uint64_t reserved_13_15 : 3; 3351215976Sjmallett uint64_t otag : 5; /**< Number of Available Outbound Tags. Tags are 3352215976Sjmallett required for all outgoing memory and maintenance 3353215976Sjmallett operations that require a response. (Max 16) */ 3354215976Sjmallett uint64_t reserved_5_7 : 3; 3355215976Sjmallett uint64_t itag : 5; /**< Number of Available Inbound Tags. Tags are 3356215976Sjmallett required for all incoming memory operations that 3357215976Sjmallett require a response. (Max 16) */ 3358215976Sjmallett#else 3359215976Sjmallett uint64_t itag : 5; 3360215976Sjmallett uint64_t reserved_5_7 : 3; 3361215976Sjmallett uint64_t otag : 5; 3362215976Sjmallett uint64_t reserved_13_15 : 3; 3363215976Sjmallett uint64_t o_clr : 1; 3364215976Sjmallett uint64_t reserved_17_63 : 47; 3365215976Sjmallett#endif 3366215976Sjmallett } s; 3367215976Sjmallett struct cvmx_sriox_tag_ctrl_s cn63xx; 3368215976Sjmallett struct cvmx_sriox_tag_ctrl_s cn63xxp1; 3369215976Sjmallett}; 3370215976Sjmalletttypedef union cvmx_sriox_tag_ctrl cvmx_sriox_tag_ctrl_t; 3371215976Sjmallett 3372215976Sjmallett/** 3373215976Sjmallett * cvmx_srio#_tlp_credits 3374215976Sjmallett * 3375215976Sjmallett * SRIO_TLP_CREDITS = SRIO TLP Credits 3376215976Sjmallett * 3377215976Sjmallett * Specifies the number of credits the SRIO can use for incoming Commands and Messages. 3378215976Sjmallett * 3379215976Sjmallett * Notes: 3380215976Sjmallett * Specifies the number of maximum credits the SRIO can use for incoming Commands and Messages. 3381215976Sjmallett * 3382215976Sjmallett * Clk_Rst: SRIO(0..1)_TLP_CREDITS hclk hrst_n 3383215976Sjmallett */ 3384215976Sjmallettunion cvmx_sriox_tlp_credits 3385215976Sjmallett{ 3386215976Sjmallett uint64_t u64; 3387215976Sjmallett struct cvmx_sriox_tlp_credits_s 3388215976Sjmallett { 3389215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3390215976Sjmallett uint64_t reserved_28_63 : 36; 3391215976Sjmallett uint64_t mbox : 4; /**< Credits for Mailbox Data used in M2S. 3392215976Sjmallett Legal values are 0x2 to 0x8. */ 3393215976Sjmallett uint64_t comp : 8; /**< Credits for Read Completions used in M2S. 3394215976Sjmallett Legal values are 0x22 to 0x80. */ 3395215976Sjmallett uint64_t reserved_13_15 : 3; 3396215976Sjmallett uint64_t n_post : 5; /**< Credits for Read Requests used in M2S. 3397215976Sjmallett Legal values are 0x4 to 0x10. */ 3398215976Sjmallett uint64_t post : 8; /**< Credits for Write Request Postings used in M2S. 3399215976Sjmallett Legal values are 0x22 to 0x80. */ 3400215976Sjmallett#else 3401215976Sjmallett uint64_t post : 8; 3402215976Sjmallett uint64_t n_post : 5; 3403215976Sjmallett uint64_t reserved_13_15 : 3; 3404215976Sjmallett uint64_t comp : 8; 3405215976Sjmallett uint64_t mbox : 4; 3406215976Sjmallett uint64_t reserved_28_63 : 36; 3407215976Sjmallett#endif 3408215976Sjmallett } s; 3409215976Sjmallett struct cvmx_sriox_tlp_credits_s cn63xx; 3410215976Sjmallett struct cvmx_sriox_tlp_credits_s cn63xxp1; 3411215976Sjmallett}; 3412215976Sjmalletttypedef union cvmx_sriox_tlp_credits cvmx_sriox_tlp_credits_t; 3413215976Sjmallett 3414215976Sjmallett/** 3415215976Sjmallett * cvmx_srio#_tx_bell 3416215976Sjmallett * 3417215976Sjmallett * SRIO_TX_BELL = SRIO Transmit Doorbell 3418215976Sjmallett * 3419215976Sjmallett * The SRIO Outgoing (TX) Doorbell 3420215976Sjmallett * 3421215976Sjmallett * Notes: 3422215976Sjmallett * This register specifies SRIO Information, Device ID, Transaction Type and Priority of the outgoing 3423215976Sjmallett * Doorbell Transaction. Writes to this register causes the Doorbell to be issued using these bits. 3424215976Sjmallett * The write also causes the PENDING bit to be set. The hardware automatically clears bit when the 3425215976Sjmallett * Doorbell operation has been acknowledged. A write to this register while the PENDING bit is set 3426215976Sjmallett * should be avoided as it will stall the RSL until the first Doorbell has completed. 3427215976Sjmallett * 3428215976Sjmallett * Clk_Rst: SRIO(0..1)_TX_BELL hclk hrst_n 3429215976Sjmallett */ 3430215976Sjmallettunion cvmx_sriox_tx_bell 3431215976Sjmallett{ 3432215976Sjmallett uint64_t u64; 3433215976Sjmallett struct cvmx_sriox_tx_bell_s 3434215976Sjmallett { 3435215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3436215976Sjmallett uint64_t reserved_48_63 : 16; 3437215976Sjmallett uint64_t data : 16; /**< Information field for next doorbell operation */ 3438215976Sjmallett uint64_t dest_id : 16; /**< Doorbell Destination Device ID[15:0] */ 3439215976Sjmallett uint64_t reserved_9_15 : 7; 3440215976Sjmallett uint64_t pending : 1; /**< Doorbell Transmit in Progress */ 3441215976Sjmallett uint64_t reserved_5_7 : 3; 3442215976Sjmallett uint64_t src_id : 1; /**< Source Device ID 0=Primary, 1=Secondary */ 3443215976Sjmallett uint64_t id16 : 1; /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */ 3444215976Sjmallett uint64_t reserved_2_2 : 1; 3445215976Sjmallett uint64_t priority : 2; /**< Doorbell Priority */ 3446215976Sjmallett#else 3447215976Sjmallett uint64_t priority : 2; 3448215976Sjmallett uint64_t reserved_2_2 : 1; 3449215976Sjmallett uint64_t id16 : 1; 3450215976Sjmallett uint64_t src_id : 1; 3451215976Sjmallett uint64_t reserved_5_7 : 3; 3452215976Sjmallett uint64_t pending : 1; 3453215976Sjmallett uint64_t reserved_9_15 : 7; 3454215976Sjmallett uint64_t dest_id : 16; 3455215976Sjmallett uint64_t data : 16; 3456215976Sjmallett uint64_t reserved_48_63 : 16; 3457215976Sjmallett#endif 3458215976Sjmallett } s; 3459215976Sjmallett struct cvmx_sriox_tx_bell_s cn63xx; 3460215976Sjmallett struct cvmx_sriox_tx_bell_s cn63xxp1; 3461215976Sjmallett}; 3462215976Sjmalletttypedef union cvmx_sriox_tx_bell cvmx_sriox_tx_bell_t; 3463215976Sjmallett 3464215976Sjmallett/** 3465215976Sjmallett * cvmx_srio#_tx_bell_info 3466215976Sjmallett * 3467215976Sjmallett * SRIO_TX_BELL_INFO = SRIO Transmit Doorbell Interrupt Information 3468215976Sjmallett * 3469215976Sjmallett * The SRIO Outgoing (TX) Doorbell Interrupt Information 3470215976Sjmallett * 3471215976Sjmallett * Notes: 3472215976Sjmallett * This register is only updated if the BELL_ERR bit is clear in SRIO(0..1)_INT_REG. This register 3473215976Sjmallett * displays SRIO Information, Device ID, Transaction Type and Priority of the Doorbell Transaction 3474215976Sjmallett * that generated the BELL_ERR Interrupt. The register includes either a RETRY, ERROR or TIMEOUT 3475215976Sjmallett * Status. 3476215976Sjmallett * 3477215976Sjmallett * Clk_Rst: SRIO(0..1)_TX_BELL_INFO hclk hrst_n 3478215976Sjmallett */ 3479215976Sjmallettunion cvmx_sriox_tx_bell_info 3480215976Sjmallett{ 3481215976Sjmallett uint64_t u64; 3482215976Sjmallett struct cvmx_sriox_tx_bell_info_s 3483215976Sjmallett { 3484215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3485215976Sjmallett uint64_t reserved_48_63 : 16; 3486215976Sjmallett uint64_t data : 16; /**< Information field from last doorbell operation */ 3487215976Sjmallett uint64_t dest_id : 16; /**< Doorbell Destination Device ID[15:0] */ 3488215976Sjmallett uint64_t reserved_8_15 : 8; 3489215976Sjmallett uint64_t timeout : 1; /**< Transmit Doorbell Failed with Timeout. */ 3490215976Sjmallett uint64_t error : 1; /**< Transmit Doorbell Destination returned Error. */ 3491215976Sjmallett uint64_t retry : 1; /**< Transmit Doorbell Requests a retransmission. */ 3492215976Sjmallett uint64_t src_id : 1; /**< Source Device ID 0=Primary, 1=Secondary */ 3493215976Sjmallett uint64_t id16 : 1; /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */ 3494215976Sjmallett uint64_t reserved_2_2 : 1; 3495215976Sjmallett uint64_t priority : 2; /**< Doorbell Priority */ 3496215976Sjmallett#else 3497215976Sjmallett uint64_t priority : 2; 3498215976Sjmallett uint64_t reserved_2_2 : 1; 3499215976Sjmallett uint64_t id16 : 1; 3500215976Sjmallett uint64_t src_id : 1; 3501215976Sjmallett uint64_t retry : 1; 3502215976Sjmallett uint64_t error : 1; 3503215976Sjmallett uint64_t timeout : 1; 3504215976Sjmallett uint64_t reserved_8_15 : 8; 3505215976Sjmallett uint64_t dest_id : 16; 3506215976Sjmallett uint64_t data : 16; 3507215976Sjmallett uint64_t reserved_48_63 : 16; 3508215976Sjmallett#endif 3509215976Sjmallett } s; 3510215976Sjmallett struct cvmx_sriox_tx_bell_info_s cn63xx; 3511215976Sjmallett struct cvmx_sriox_tx_bell_info_s cn63xxp1; 3512215976Sjmallett}; 3513215976Sjmalletttypedef union cvmx_sriox_tx_bell_info cvmx_sriox_tx_bell_info_t; 3514215976Sjmallett 3515215976Sjmallett/** 3516215976Sjmallett * cvmx_srio#_tx_ctrl 3517215976Sjmallett * 3518215976Sjmallett * SRIO_TX_CTRL = SRIO Transmit Control 3519215976Sjmallett * 3520215976Sjmallett * The SRIO Transmit Control 3521215976Sjmallett * 3522215976Sjmallett * Notes: 3523215976Sjmallett * This register is used to control SRIO Outgoing Packet Allocation. TX_TH[2:0] set the thresholds 3524215976Sjmallett * to allow each priority traffic to be queued for transmission. 8 TX Buffer are available. A 3525215976Sjmallett * threshold greater than 8 stops all traffic on that priority and should be avoided. TAG_TH[2:0] 3526215976Sjmallett * set the thresholds to allow priority traffic requiring responses to be queued based on the number 3527215976Sjmallett * of outgoing tags (TIDs) available. 16 Tags are available. If a priority is blocked for lack of 3528215976Sjmallett * tags then all lower priority packets are also blocked irregardless of whether they require tags. 3529215976Sjmallett * 3530215976Sjmallett * Clk_Rst: SRIO(0..1)_TX_CTRL hclk hrst_n 3531215976Sjmallett */ 3532215976Sjmallettunion cvmx_sriox_tx_ctrl 3533215976Sjmallett{ 3534215976Sjmallett uint64_t u64; 3535215976Sjmallett struct cvmx_sriox_tx_ctrl_s 3536215976Sjmallett { 3537215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3538215976Sjmallett uint64_t reserved_53_63 : 11; 3539215976Sjmallett uint64_t tag_th2 : 5; /**< Sets threshold for minimum number of OTAGs 3540215976Sjmallett required before a packet of priority 2 requiring a 3541215976Sjmallett response will be queued for transmission. (Max 16) 3542215976Sjmallett There generally should be no priority 3 request 3543215976Sjmallett packets which require a response/tag, so a TAG_THR 3544215976Sjmallett value as low as 0 is allowed. */ 3545215976Sjmallett uint64_t reserved_45_47 : 3; 3546215976Sjmallett uint64_t tag_th1 : 5; /**< Sets threshold for minimum number of OTAGs 3547215976Sjmallett required before a packet of priority 1 requiring a 3548215976Sjmallett response will be queued for transmission. (Max 16) 3549215976Sjmallett Generally, TAG_TH1 must be > TAG_TH2 to leave OTAGs 3550215976Sjmallett for outgoing priority 2 (or 3) requests. */ 3551215976Sjmallett uint64_t reserved_37_39 : 3; 3552215976Sjmallett uint64_t tag_th0 : 5; /**< Sets threshold for minimum number of OTAGs 3553215976Sjmallett required before a packet of priority 0 requiring a 3554215976Sjmallett response will be queued for transmission. (Max 16) 3555215976Sjmallett Generally, TAG_TH0 must be > TAG_TH1 to leave OTAGs 3556215976Sjmallett for outgoing priority 1 or 2 (or 3) requests. */ 3557215976Sjmallett uint64_t reserved_20_31 : 12; 3558215976Sjmallett uint64_t tx_th2 : 4; /**< Sets threshold for minimum number of TX buffers 3559215976Sjmallett before a Priority 2 Packet will be queued for 3560215976Sjmallett transmission. (Max 8) 3561215976Sjmallett Generally, TX_TH2 must be > 0 to leave space for 3562215976Sjmallett outgoing priority 3 packets. */ 3563215976Sjmallett uint64_t reserved_12_15 : 4; 3564215976Sjmallett uint64_t tx_th1 : 4; /**< Sets threshold for minimum number of TX buffers 3565215976Sjmallett before a Priority 1 Packet will be queued for 3566215976Sjmallett transmission. (Max 8) 3567215976Sjmallett Generally, TX_TH1 must be > TX_TH2 to leave space 3568215976Sjmallett for outgoing priority 2 or 3 packets. */ 3569215976Sjmallett uint64_t reserved_4_7 : 4; 3570215976Sjmallett uint64_t tx_th0 : 4; /**< Sets threshold for minimum number of TX buffers 3571215976Sjmallett before a Priority 0 Packet will be queued for 3572215976Sjmallett transmission. (Max 8) 3573215976Sjmallett Generally, TX_TH0 must be > TX_TH1 to leave space 3574215976Sjmallett for outgoing priority 1 or 2 or 3 packets. */ 3575215976Sjmallett#else 3576215976Sjmallett uint64_t tx_th0 : 4; 3577215976Sjmallett uint64_t reserved_4_7 : 4; 3578215976Sjmallett uint64_t tx_th1 : 4; 3579215976Sjmallett uint64_t reserved_12_15 : 4; 3580215976Sjmallett uint64_t tx_th2 : 4; 3581215976Sjmallett uint64_t reserved_20_31 : 12; 3582215976Sjmallett uint64_t tag_th0 : 5; 3583215976Sjmallett uint64_t reserved_37_39 : 3; 3584215976Sjmallett uint64_t tag_th1 : 5; 3585215976Sjmallett uint64_t reserved_45_47 : 3; 3586215976Sjmallett uint64_t tag_th2 : 5; 3587215976Sjmallett uint64_t reserved_53_63 : 11; 3588215976Sjmallett#endif 3589215976Sjmallett } s; 3590215976Sjmallett struct cvmx_sriox_tx_ctrl_s cn63xx; 3591215976Sjmallett struct cvmx_sriox_tx_ctrl_s cn63xxp1; 3592215976Sjmallett}; 3593215976Sjmalletttypedef union cvmx_sriox_tx_ctrl cvmx_sriox_tx_ctrl_t; 3594215976Sjmallett 3595215976Sjmallett/** 3596215976Sjmallett * cvmx_srio#_tx_emphasis 3597215976Sjmallett * 3598215976Sjmallett * SRIO_TX_EMPHASIS = SRIO TX Lane Emphasis (Pass 2) 3599215976Sjmallett * 3600215976Sjmallett * Controls TX Emphasis used by the SRIO SERDES 3601215976Sjmallett * 3602215976Sjmallett * Notes: 3603215976Sjmallett * This controls the emphasis value used by the SRIO SERDES. This register is only reset during COLD 3604215976Sjmallett * boot and may be modified regardless of the value in SRIO(0..1)_STATUS_REG.ACCESS. 3605215976Sjmallett * 3606215976Sjmallett * Clk_Rst: SRIO(0..1)_TX_EMPHASIS sclk srst_cold_n 3607215976Sjmallett */ 3608215976Sjmallettunion cvmx_sriox_tx_emphasis 3609215976Sjmallett{ 3610215976Sjmallett uint64_t u64; 3611215976Sjmallett struct cvmx_sriox_tx_emphasis_s 3612215976Sjmallett { 3613215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3614215976Sjmallett uint64_t reserved_4_63 : 60; 3615215976Sjmallett uint64_t emph : 4; /**< Emphasis Value used for all lanes. Default value 3616215976Sjmallett is 0x0 for 1.25G b/s and 0xA for all other rates. */ 3617215976Sjmallett#else 3618215976Sjmallett uint64_t emph : 4; 3619215976Sjmallett uint64_t reserved_4_63 : 60; 3620215976Sjmallett#endif 3621215976Sjmallett } s; 3622215976Sjmallett struct cvmx_sriox_tx_emphasis_s cn63xx; 3623215976Sjmallett}; 3624215976Sjmalletttypedef union cvmx_sriox_tx_emphasis cvmx_sriox_tx_emphasis_t; 3625215976Sjmallett 3626215976Sjmallett/** 3627215976Sjmallett * cvmx_srio#_tx_status 3628215976Sjmallett * 3629215976Sjmallett * SRIO_TX_STATUS = SRIO Outbound Credits/Ops Status 3630215976Sjmallett * 3631215976Sjmallett * Specifies the current number of credits/ops by SRIO for Outbound Traffic 3632215976Sjmallett * 3633215976Sjmallett * Notes: 3634215976Sjmallett * Debug Register specifying the number of credits/ops currently in use for Outbound Traffic. 3635215976Sjmallett * When all outbound traffic has stopped the values should eventually return to the reset values. 3636215976Sjmallett * 3637215976Sjmallett * Clk_Rst: SRIO(0..1)_TX_STATUS hclk hrst_n 3638215976Sjmallett */ 3639215976Sjmallettunion cvmx_sriox_tx_status 3640215976Sjmallett{ 3641215976Sjmallett uint64_t u64; 3642215976Sjmallett struct cvmx_sriox_tx_status_s 3643215976Sjmallett { 3644215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3645215976Sjmallett uint64_t reserved_32_63 : 32; 3646215976Sjmallett uint64_t s2m_pr3 : 8; /**< Number of pending S2M Priority 3 Entries. */ 3647215976Sjmallett uint64_t s2m_pr2 : 8; /**< Number of pending S2M Priority 2 Entries. */ 3648215976Sjmallett uint64_t s2m_pr1 : 8; /**< Number of pending S2M Priority 1 Entries. */ 3649215976Sjmallett uint64_t s2m_pr0 : 8; /**< Number of pending S2M Priority 0 Entries. */ 3650215976Sjmallett#else 3651215976Sjmallett uint64_t s2m_pr0 : 8; 3652215976Sjmallett uint64_t s2m_pr1 : 8; 3653215976Sjmallett uint64_t s2m_pr2 : 8; 3654215976Sjmallett uint64_t s2m_pr3 : 8; 3655215976Sjmallett uint64_t reserved_32_63 : 32; 3656215976Sjmallett#endif 3657215976Sjmallett } s; 3658215976Sjmallett struct cvmx_sriox_tx_status_s cn63xx; 3659215976Sjmallett struct cvmx_sriox_tx_status_s cn63xxp1; 3660215976Sjmallett}; 3661215976Sjmalletttypedef union cvmx_sriox_tx_status cvmx_sriox_tx_status_t; 3662215976Sjmallett 3663215976Sjmallett/** 3664215976Sjmallett * cvmx_srio#_wr_done_counts 3665215976Sjmallett * 3666215976Sjmallett * SRIO_WR_DONE_COUNTS = SRIO Outgoing Write Done Counts (Pass 2) 3667215976Sjmallett * 3668215976Sjmallett * The SRIO Outbound Write Done Counts 3669215976Sjmallett * 3670215976Sjmallett * Notes: 3671215976Sjmallett * This register shows the number of successful and unsuccessful NwriteRs issued through this MAC. 3672215976Sjmallett * These count only considers the last NwriteR generated by each Store Instruction. If any NwriteR 3673215976Sjmallett * in the series receives an ERROR Status then it is reported in SRIOMAINT(0..1)_ERB_LT_ERR_DET.IO_ERR. 3674215976Sjmallett * If any NwriteR does not receive a response within the timeout period then it is reported in 3675215976Sjmallett * SRIOMAINT(0..1)_ERB_LT_ERR_DET.PKT_TOUT. Only errors on the last NwriteR's are counted as BAD. This 3676215976Sjmallett * register is typically not written while Outbound SRIO Memory traffic is enabled. 3677215976Sjmallett * 3678215976Sjmallett * Clk_Rst: SRIO(0..1)_WR_DONE_COUNTS hclk hrst_n 3679215976Sjmallett */ 3680215976Sjmallettunion cvmx_sriox_wr_done_counts 3681215976Sjmallett{ 3682215976Sjmallett uint64_t u64; 3683215976Sjmallett struct cvmx_sriox_wr_done_counts_s 3684215976Sjmallett { 3685215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3686215976Sjmallett uint64_t reserved_32_63 : 32; 3687215976Sjmallett uint64_t bad : 16; /**< Count of the final outbound NwriteR in the series 3688215976Sjmallett associated with a Store Operation that have timed 3689215976Sjmallett out or received a response with an ERROR status. */ 3690215976Sjmallett uint64_t good : 16; /**< Count of the final outbound NwriteR in the series 3691215976Sjmallett associated with a Store operation that has 3692215976Sjmallett received a response with a DONE status. */ 3693215976Sjmallett#else 3694215976Sjmallett uint64_t good : 16; 3695215976Sjmallett uint64_t bad : 16; 3696215976Sjmallett uint64_t reserved_32_63 : 32; 3697215976Sjmallett#endif 3698215976Sjmallett } s; 3699215976Sjmallett struct cvmx_sriox_wr_done_counts_s cn63xx; 3700215976Sjmallett}; 3701215976Sjmalletttypedef union cvmx_sriox_wr_done_counts cvmx_sriox_wr_done_counts_t; 3702215976Sjmallett 3703215976Sjmallett#endif 3704