1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-rnm-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon rnm. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_RNM_TYPEDEFS_H__ 53#define __CVMX_RNM_TYPEDEFS_H__ 54 55#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull)) 56#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull)) 57#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 58#define CVMX_RNM_EER_DBG CVMX_RNM_EER_DBG_FUNC() 59static inline uint64_t CVMX_RNM_EER_DBG_FUNC(void) 60{ 61 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 62 cvmx_warn("CVMX_RNM_EER_DBG not supported on this chip\n"); 63 return CVMX_ADD_IO_SEG(0x0001180040000018ull); 64} 65#else 66#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull)) 67#endif 68#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69#define CVMX_RNM_EER_KEY CVMX_RNM_EER_KEY_FUNC() 70static inline uint64_t CVMX_RNM_EER_KEY_FUNC(void) 71{ 72 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 73 cvmx_warn("CVMX_RNM_EER_KEY not supported on this chip\n"); 74 return CVMX_ADD_IO_SEG(0x0001180040000010ull); 75} 76#else 77#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull)) 78#endif 79#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80#define CVMX_RNM_SERIAL_NUM CVMX_RNM_SERIAL_NUM_FUNC() 81static inline uint64_t CVMX_RNM_SERIAL_NUM_FUNC(void) 82{ 83 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 84 cvmx_warn("CVMX_RNM_SERIAL_NUM not supported on this chip\n"); 85 return CVMX_ADD_IO_SEG(0x0001180040000020ull); 86} 87#else 88#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull)) 89#endif 90 91/** 92 * cvmx_rnm_bist_status 93 * 94 * RNM_BIST_STATUS = RNM's BIST Status Register 95 * 96 * The RNM's Memory Bist Status register. 97 */ 98union cvmx_rnm_bist_status 99{ 100 uint64_t u64; 101 struct cvmx_rnm_bist_status_s 102 { 103#if __BYTE_ORDER == __BIG_ENDIAN 104 uint64_t reserved_2_63 : 62; 105 uint64_t rrc : 1; /**< Status of RRC block bist. */ 106 uint64_t mem : 1; /**< Status of MEM block bist. */ 107#else 108 uint64_t mem : 1; 109 uint64_t rrc : 1; 110 uint64_t reserved_2_63 : 62; 111#endif 112 } s; 113 struct cvmx_rnm_bist_status_s cn30xx; 114 struct cvmx_rnm_bist_status_s cn31xx; 115 struct cvmx_rnm_bist_status_s cn38xx; 116 struct cvmx_rnm_bist_status_s cn38xxp2; 117 struct cvmx_rnm_bist_status_s cn50xx; 118 struct cvmx_rnm_bist_status_s cn52xx; 119 struct cvmx_rnm_bist_status_s cn52xxp1; 120 struct cvmx_rnm_bist_status_s cn56xx; 121 struct cvmx_rnm_bist_status_s cn56xxp1; 122 struct cvmx_rnm_bist_status_s cn58xx; 123 struct cvmx_rnm_bist_status_s cn58xxp1; 124 struct cvmx_rnm_bist_status_s cn63xx; 125 struct cvmx_rnm_bist_status_s cn63xxp1; 126}; 127typedef union cvmx_rnm_bist_status cvmx_rnm_bist_status_t; 128 129/** 130 * cvmx_rnm_ctl_status 131 * 132 * RNM_CTL_STATUS = RNM's Control/Status Register 133 * 134 * The RNM's interrupt enable register. 135 */ 136union cvmx_rnm_ctl_status 137{ 138 uint64_t u64; 139 struct cvmx_rnm_ctl_status_s 140 { 141#if __BYTE_ORDER == __BIG_ENDIAN 142 uint64_t reserved_11_63 : 53; 143 uint64_t eer_lck : 1; /**< Encryption enable register locked */ 144 uint64_t eer_val : 1; /**< Dormant encryption key match */ 145 uint64_t ent_sel : 4; /**< ? */ 146 uint64_t exp_ent : 1; /**< Exported entropy enable for random number generator */ 147 uint64_t rng_rst : 1; /**< Reset RNG as core reset. */ 148 uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register 149 logic. */ 150 uint64_t rng_en : 1; /**< Enable the output of the RNG. */ 151 uint64_t ent_en : 1; /**< Entropy enable for random number generator. */ 152#else 153 uint64_t ent_en : 1; 154 uint64_t rng_en : 1; 155 uint64_t rnm_rst : 1; 156 uint64_t rng_rst : 1; 157 uint64_t exp_ent : 1; 158 uint64_t ent_sel : 4; 159 uint64_t eer_val : 1; 160 uint64_t eer_lck : 1; 161 uint64_t reserved_11_63 : 53; 162#endif 163 } s; 164 struct cvmx_rnm_ctl_status_cn30xx 165 { 166#if __BYTE_ORDER == __BIG_ENDIAN 167 uint64_t reserved_4_63 : 60; 168 uint64_t rng_rst : 1; /**< Reset RNG as core reset. */ 169 uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register 170 logic. */ 171 uint64_t rng_en : 1; /**< Enable the output of the RNG. */ 172 uint64_t ent_en : 1; /**< Entropy enable for random number generator. */ 173#else 174 uint64_t ent_en : 1; 175 uint64_t rng_en : 1; 176 uint64_t rnm_rst : 1; 177 uint64_t rng_rst : 1; 178 uint64_t reserved_4_63 : 60; 179#endif 180 } cn30xx; 181 struct cvmx_rnm_ctl_status_cn30xx cn31xx; 182 struct cvmx_rnm_ctl_status_cn30xx cn38xx; 183 struct cvmx_rnm_ctl_status_cn30xx cn38xxp2; 184 struct cvmx_rnm_ctl_status_cn50xx 185 { 186#if __BYTE_ORDER == __BIG_ENDIAN 187 uint64_t reserved_9_63 : 55; 188 uint64_t ent_sel : 4; /**< ? */ 189 uint64_t exp_ent : 1; /**< Exported entropy enable for random number generator */ 190 uint64_t rng_rst : 1; /**< Reset RNG as core reset. */ 191 uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register 192 logic. */ 193 uint64_t rng_en : 1; /**< Enable the output of the RNG. */ 194 uint64_t ent_en : 1; /**< Entropy enable for random number generator. */ 195#else 196 uint64_t ent_en : 1; 197 uint64_t rng_en : 1; 198 uint64_t rnm_rst : 1; 199 uint64_t rng_rst : 1; 200 uint64_t exp_ent : 1; 201 uint64_t ent_sel : 4; 202 uint64_t reserved_9_63 : 55; 203#endif 204 } cn50xx; 205 struct cvmx_rnm_ctl_status_cn50xx cn52xx; 206 struct cvmx_rnm_ctl_status_cn50xx cn52xxp1; 207 struct cvmx_rnm_ctl_status_cn50xx cn56xx; 208 struct cvmx_rnm_ctl_status_cn50xx cn56xxp1; 209 struct cvmx_rnm_ctl_status_cn50xx cn58xx; 210 struct cvmx_rnm_ctl_status_cn50xx cn58xxp1; 211 struct cvmx_rnm_ctl_status_s cn63xx; 212 struct cvmx_rnm_ctl_status_s cn63xxp1; 213}; 214typedef union cvmx_rnm_ctl_status cvmx_rnm_ctl_status_t; 215 216/** 217 * cvmx_rnm_eer_dbg 218 * 219 * RNM_EER_DBG = RNM's Encryption enable debug register 220 * 221 * The RNM's Encryption enable debug register 222 */ 223union cvmx_rnm_eer_dbg 224{ 225 uint64_t u64; 226 struct cvmx_rnm_eer_dbg_s 227 { 228#if __BYTE_ORDER == __BIG_ENDIAN 229 uint64_t dat : 64; /**< Dormant encryption debug info. */ 230#else 231 uint64_t dat : 64; 232#endif 233 } s; 234 struct cvmx_rnm_eer_dbg_s cn63xx; 235 struct cvmx_rnm_eer_dbg_s cn63xxp1; 236}; 237typedef union cvmx_rnm_eer_dbg cvmx_rnm_eer_dbg_t; 238 239/** 240 * cvmx_rnm_eer_key 241 * 242 * RNM_EER_KEY = RNM's Encryption enable register 243 * 244 * The RNM's Encryption enable register 245 */ 246union cvmx_rnm_eer_key 247{ 248 uint64_t u64; 249 struct cvmx_rnm_eer_key_s 250 { 251#if __BYTE_ORDER == __BIG_ENDIAN 252 uint64_t key : 64; /**< Dormant encryption key. If dormant crypto is fuse 253 enabled, crypto can be enable by writing this 254 register with the correct key. */ 255#else 256 uint64_t key : 64; 257#endif 258 } s; 259 struct cvmx_rnm_eer_key_s cn63xx; 260 struct cvmx_rnm_eer_key_s cn63xxp1; 261}; 262typedef union cvmx_rnm_eer_key cvmx_rnm_eer_key_t; 263 264/** 265 * cvmx_rnm_serial_num 266 * 267 * RNM_SERIAL_NUM = RNM's fuse serial number register 268 * 269 * The RNM's fuse serial number register 270 * 271 * Notes: 272 * Added RNM_SERIAL_NUM in pass 2.0 273 * 274 */ 275union cvmx_rnm_serial_num 276{ 277 uint64_t u64; 278 struct cvmx_rnm_serial_num_s 279 { 280#if __BYTE_ORDER == __BIG_ENDIAN 281 uint64_t dat : 64; /**< Dormant encryption serial number */ 282#else 283 uint64_t dat : 64; 284#endif 285 } s; 286 struct cvmx_rnm_serial_num_s cn63xx; 287}; 288typedef union cvmx_rnm_serial_num cvmx_rnm_serial_num_t; 289 290#endif 291