/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 41 namespace RegState { namespace in namespace:llvm 58 } // end namespace RegState 93 flags & RegState::Define, 94 flags & RegState::Implicit, 95 flags & RegState::Kill, 96 flags & RegState::Dead, 97 flags & RegState::Undef, 98 flags & RegState::EarlyClobber, 100 flags & RegState::Debug, 101 flags & RegState [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRExpandPseudoInsts.cpp | 155 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) 160 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) 188 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) 196 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) 236 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) 246 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) 284 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) 288 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) 341 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) 349 .addReg(DstHiReg, RegState [all...] |
H A D | AVRFrameLowering.cpp | 72 .addReg(AVR::R29R28, RegState::Kill) 81 .addReg(AVR::R1R0, RegState::Kill) 88 .addReg(AVR::R0, RegState::Kill) 91 .addReg(AVR::R0, RegState::Define) 92 .addReg(AVR::R0, RegState::Kill) 93 .addReg(AVR::R0, RegState::Kill) 132 .addReg(AVR::R29R28, RegState::Kill) 173 .addReg(AVR::R0, RegState::Kill); 209 .addReg(AVR::R29R28, RegState::Kill) 216 .addReg(AVR::R29R28, RegState [all...] |
H A D | AVRRegisterInfo.cpp | 197 .addReg(DstReg, RegState::Kill) 225 .addReg(AVR::R29R28, RegState::Kill) 232 .addReg(AVR::R0, RegState::Kill); 237 .addReg(AVR::R29R28, RegState::Kill)
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H A D | AVRRelaxMemOperations.cpp | 104 .addReg(Ptr.getReg(), RegState::Define)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFInstrInfo.cpp | 79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg) 82 .addReg(ScratchReg, RegState::Kill).addReg(DstReg) 93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); 95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); 100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); 102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); 107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); 109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFormMemoryClauses.cpp | 139 S |= RegState::Implicit; 141 S |= RegState::Dead; 143 S |= RegState::Undef; 145 S |= RegState::Kill; 147 S |= RegState::EarlyClobber; 149 S |= RegState::Renamable; 377 unsigned S = R.second.first | RegState::EarlyClobber; 379 S &= ~(RegState::Undef | RegState::Dead); 386 B.addUse(R.first, R.second.first & ~RegState [all...] |
H A D | SIFrameLowering.cpp | 107 .addReg(SpillReg, RegState::Kill) 127 .addReg(SpillReg, RegState::Kill) 128 .addReg(OffsetReg, RegState::Kill) 175 .addReg(OffsetReg, RegState::Kill) 255 .addReg(FlatScrInitHi, RegState::Kill); 265 .addReg(FlatScrInitLo, RegState::Kill) 490 .addReg(PreloadedPrivateBufferReg, RegState::Kill); 502 .addReg(PreloadedScratchWaveOffsetReg, HasFP ? RegState::Kill : 0); 507 .addReg(PreloadedPrivateBufferReg, RegState::Kill); 555 .addReg(ScratchRsrcReg, RegState [all...] |
H A D | SIRegisterInfo.cpp | 372 .addReg(OffsetReg, RegState::Kill) 730 .addReg(TmpReg, RegState::Kill); 734 MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState); 807 .addReg(Spill.VGPR, VGPRDefined ? 0 : RegState::Undef); 832 Mov.addReg(SuperReg, RegState::Implicit | SuperKillState); 842 .addReg(TmpVGPR, RegState::Kill) // src 900 MIB.addReg(SuperReg, RegState::ImplicitDefine); 927 .addReg(TmpVGPR, RegState::Kill); 930 MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); 1114 .addReg(DiffReg, RegState [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 108 .addReg(ScratchOffset, RegState::Kill) 115 .addReg(ScratchOffset, RegState::Kill) 121 .addReg(ScratchOffset, RegState::Kill); 184 .addReg(ScratchBase, RegState::Kill) 185 .addReg(ScratchOffset, RegState::Kill) 191 .addReg(ScratchBase, RegState::Kill) 192 .addReg(ScratchOffset, RegState::Kill) 197 .addReg(ScratchBase, RegState::Kill) 198 .addReg(ScratchOffset, RegState::Kill);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.cpp | 91 .addReg(ARM::SP).addReg(ScratchReg, RegState::Kill) 413 .addReg(ARM::SP, RegState::Kill) 418 .addReg(ARM::R4, RegState::Kill) 424 .addReg(ARM::R4, RegState::Kill) 429 .addReg(ARM::R4, RegState::Kill) 644 MIB.addReg(ARM::PC, RegState::Define); 722 .addReg(PopReg, RegState::Define) 728 .addReg(ARM::LR, RegState::Define) 729 .addReg(PopReg, RegState::Kill) 744 .addReg(TemporaryReg, RegState [all...] |
H A D | ARMFrameLowering.cpp | 304 .addReg(Reg, RegState::Kill) 309 .addReg(Reg, RegState::Kill) 319 .addReg(Reg, RegState::Kill) 324 .addReg(Reg, RegState::Kill) 334 .addReg(Reg, RegState::Kill) 540 .addReg(ARM::R4, RegState::Implicit) 550 .addReg(ARM::R12, RegState::Kill) 551 .addReg(ARM::R4, RegState::Implicit) 557 .addReg(ARM::SP, RegState::Kill) 558 .addReg(ARM::R4, RegState [all...] |
H A D | ARMBaseInstrInfo.cpp | 785 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); 805 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define); 816 MIB.addReg(DestReg, RegState::Undef); 821 MIB.addReg(ARM::VPR, RegState::Implicit); 1324 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 1325 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 1335 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 1336 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 1340 MIB.addReg(DestReg, RegState [all...] |
H A D | ARMExpandPseudoInsts.cpp | 498 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); 502 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 504 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 506 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 508 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 569 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 645 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. 689 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 691 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 693 MIB.addReg(D2, RegState [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandPseudoInsts.cpp | 114 MI.getOperand(0).isRenamable() ? RegState::Renamable : 0; 148 .addReg(DstReg, RegState::Define | 160 RegState::Define | 216 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill); 287 .addReg(DestLo.getReg(), RegState::Define) 288 .addReg(DestHi.getReg(), RegState::Define) 303 .addUse(StatusReg, RegState::Kill) 304 .addUse(StatusReg, RegState::Kill) 514 .addReg(DstReg, RegState [all...] |
H A D | AArch64FrameLowering.cpp | 714 MIB.addReg(AArch64::SP, RegState::Define); 1070 .addReg(AArch64::X15, RegState::Implicit) 1071 .addReg(AArch64::X16, RegState::Implicit | RegState::Define | RegState::Dead) 1072 .addReg(AArch64::X17, RegState::Implicit | RegState::Define | RegState::Dead) 1073 .addReg(AArch64::NZCV, RegState::Implicit | RegState [all...] |
H A D | AArch64SpeculationHardening.cpp | 399 .addDef(TmpReg, RegState::Renamable) 400 .addUse(TmpReg, RegState::Kill | RegState::Renamable) 401 .addUse(MisspeculatingTaintReg, RegState::Kill) 406 .addUse(TmpReg, RegState::Kill) 578 .addUse(SrcReg, RegState::Kill)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCFrameLowering.cpp | 150 .addReg(ARC::SP, RegState::Define) 167 .addReg(ARC::BLINK, RegState::Implicit | RegState::Kill); 297 .addReg(ARC::BLINK, RegState::Implicit | RegState::Kill); 314 .addReg(ARC::FP, RegState::Define) 315 .addReg(ARC::SP, RegState::Define) 465 .addReg(Reg, RegState::Kill)
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H A D | ARCRegisterInfo.cpp | 76 .addReg(BaseReg, RegState::Define) 80 KillState = RegState::Kill; 116 .addReg(Reg, RegState::Define)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.cpp | 93 MIB.addReg(DestReg, RegState::Define); 265 addSaveRestoreRegs(MIB, CSI, RegState::Define); 267 MIB.addReg(Mips::S2, RegState::Define); 290 MIB2.addReg(Mips::SP, RegState::Kill); 293 MIB3.addReg(Reg2, RegState::Kill); 296 MIB4.addReg(Reg1, RegState::Kill); 418 .addReg(SpReg, RegState::Kill) 423 .addReg(Reg, RegState::Kill);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitDouble.cpp | 653 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) 656 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) 662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) 666 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) 771 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg()); 811 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); 836 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); 839 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); 842 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR) 848 .addReg(Op1.getReg(), RS & ~RegState [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 569 .addReg(NegSizeReg1, RegState::Kill); 574 .addReg(Reg, RegState::Kill) 594 .addReg(NegSizeReg1, RegState::Kill); 599 .addReg(Reg, RegState::Kill) 673 .addReg(Reg1, RegState::Kill) 680 .addReg(Reg, RegState::Kill), 719 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 724 .addReg(Reg, RegState::Kill); 800 .addReg(getCRFromCRBit(SrcReg), RegState::Undef); 811 .addReg(getCRFromCRBit(SrcReg), RegState [all...] |
H A D | PPCFrameLowering.cpp | 391 .addReg(SrcReg, RegState::Kill) 400 .addReg(SrcReg, RegState::Kill) 409 .addReg(SrcReg, RegState::Kill) 413 .addReg(DstReg, RegState::Kill) 971 unsigned CrState = RegState::ImplicitKill; 974 CrState = RegState::Kill; 996 unsigned CrState = RegState::ImplicitKill; 999 CrState = RegState::Kill; 1073 .addReg(ScratchReg, RegState::Kill) 1080 .addReg(TempReg, RegState [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86LoadValueInjectionRetHardening.cpp | 112 .addReg(ClobberReg, RegState::Define)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 223 MIB.addReg(VRBase, RegState::Define); 236 MIB.addReg(VRBase, RegState::Define); 248 MIB.addReg(VRBase, RegState::Define); 693 MIB.addReg(0U, RegState::Debug); 730 MIB.addReg(SD->getVReg(), RegState::Debug); 757 MIB.addReg(0U, RegState::Debug); 903 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | 904 RegState::EarlyClobber); 1095 RegState::Define | 1104 RegState [all...] |