Lines Matching refs:RegState
372 .addReg(OffsetReg, RegState::Kill)
730 .addReg(TmpReg, RegState::Kill);
734 MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState);
807 .addReg(Spill.VGPR, VGPRDefined ? 0 : RegState::Undef);
832 Mov.addReg(SuperReg, RegState::Implicit | SuperKillState);
842 .addReg(TmpVGPR, RegState::Kill) // src
900 MIB.addReg(SuperReg, RegState::ImplicitDefine);
927 .addReg(TmpVGPR, RegState::Kill);
930 MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
1114 .addReg(DiffReg, RegState::Kill);
1122 MIB.addReg(ScaledReg, RegState::Kill);
1138 MIB.addReg(ConstOffsetReg, RegState::Kill);
1139 MIB.addReg(ScaledReg, RegState::Kill);
1154 .addReg(DiffReg, RegState::Kill)
1157 .addReg(ScaledReg, RegState::Kill)
1160 .addReg(ScaledReg, RegState::Kill);
1165 .addReg(ScaledReg, RegState::Kill)
1168 .addReg(DiffReg, RegState::Kill)