Lines Matching refs:RegState
785 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
805 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
816 MIB.addReg(DestReg, RegState::Undef);
821 MIB.addReg(ARM::VPR, RegState::Implicit);
1324 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1325 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1335 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1336 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1340 MIB.addReg(DestReg, RegState::ImplicitDefine);
1382 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1383 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1384 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1386 MIB.addReg(DestReg, RegState::ImplicitDefine);
1405 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1406 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1407 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1408 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1410 MIB.addReg(DestReg, RegState::ImplicitDefine);
1421 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1422 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1423 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1424 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1425 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1426 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1427 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1428 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1430 MIB.addReg(DestReg, RegState::ImplicitDefine);
1557 LDM.addReg(Reg, RegState::Define);
1558 STM.addReg(Reg, RegState::Kill);
1631 MIB.addReg(SrcRegS, RegState::Implicit);
2363 .addReg(BaseReg, RegState::Kill)
2386 .addReg(BaseReg, RegState::Kill)
4780 MIB.addReg(Reg, RegState::Kill).addImm(0);
4790 MIB.addReg(Reg, RegState::Kill)
4952 MIB.addReg(DstReg, RegState::Define)
4975 MIB.addReg(DstReg, RegState::Define)
4976 .addReg(DReg, RegState::Undef)
4982 MIB.addReg(SrcReg, RegState::Implicit);
5005 MIB.addReg(DReg, RegState::Define)
5013 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
5015 MIB.addReg(ImplicitSReg, RegState::Implicit);
5041 MIB.addReg(DDst, RegState::Define)
5048 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
5049 MIB.addReg(SrcReg, RegState::Implicit);
5051 MIB.addReg(ImplicitSReg, RegState::Implicit);
5085 NewMIB.addReg(SrcReg, RegState::Implicit);
5088 MIB.addReg(DDst, RegState::Define);
5103 MIB.addReg(SrcReg, RegState::Implicit);
5107 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
5109 MIB.addReg(ImplicitSReg, RegState::Implicit);