Lines Matching refs:RegState
498 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
502 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
504 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
506 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
508 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
569 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
645 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
689 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
691 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
693 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
695 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
737 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
777 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
848 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
880 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
956 .addReg(DesiredReg, RegState::Kill);
983 .addReg(ARM::CPSR, RegState::Kill);
1000 .addReg(TempReg, RegState::Kill)
1006 .addReg(ARM::CPSR, RegState::Kill);
1086 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);
1098 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
1104 .addReg(ARM::CPSR, RegState::Kill);
1120 .addReg(TempReg, RegState::Kill)
1126 .addReg(ARM::CPSR, RegState::Kill);
1201 .addReg(JumpTarget.getReg(), RegState::Kill);
1371 .addReg(ARM::R6, RegState::Kill)
1391 .addReg(ARM::CPSR, RegState::Define);
1432 MIB.addReg(Reg, RegState::Kill);
1460 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1515 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1556 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1582 .addReg(ARM::CPSR, RegState::Undef);
1607 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1608 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1611 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1639 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
1640 .addReg(D1, SrcIsKill ? RegState::Kill : 0);
1942 .addReg(ARM::SP, RegState::Define)