Lines Matching refs:RegState
653 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
656 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
666 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
771 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());
811 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
836 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
839 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
842 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
848 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
859 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)
870 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));
882 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
885 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);
888 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))
946 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
947 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
953 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
954 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
958 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
975 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
986 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);