/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 22 namespace ARM_AM { namespace in namespace:llvm 25 default: return ARM_AM::no_shift; 26 case ISD::SHL: return ARM_AM::lsl; 27 case ISD::SRL: return ARM_AM::lsr; 28 case ISD::SRA: return ARM_AM::asr; 29 case ISD::ROTR: return ARM_AM::ror; 33 //case ARMISD::RRX: return ARM_AM::rrx; 36 } // end namespace ARM_AM
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H A D | ARMLoadStoreOptimizer.cpp | 191 int Offset = isAM3 ? ARM_AM::getAM3Offset(OffField) 192 : ARM_AM::getAM5Offset(OffField) * 4; 193 ARM_AM::AddrOpc Op = isAM3 ? ARM_AM::getAM3Op(OffField) 194 : ARM_AM::getAM5Op(OffField); 196 if (Op == ARM_AM::sub) 210 static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode) { 217 case ARM_AM::ia: return ARM::LDMIA; 218 case ARM_AM::da: return ARM::LDMDA; 219 case ARM_AM [all...] |
H A D | ARMISelDAGToDAG.cpp | 96 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt); 184 return ARM_AM::getSOImmVal(Imm) != -1; 188 return ARM_AM::getSOImmVal(~Imm) != -1; 192 return ARM_AM::getT2SOImmVal(Imm) != -1; 196 return ARM_AM::getT2SOImmVal(~Imm) != -1; 472 ARM_AM::ShiftOpc ShOpcVal, 479 return ShOpcVal == ARM_AM::lsl && 488 if (ARM_AM::isThumbImmShiftedVal(Val)) return 2; // MOV + LSL 490 if (ARM_AM::getSOImmVal(Val) != -1) return 1; // MOV 491 if (ARM_AM [all...] |
H A D | ARMBaseInstrInfo.cpp | 172 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 173 unsigned Amt = ARM_AM::getAM2Offset(OffImm); 175 if (ARM_AM::getSOImmVal(Amt) == -1) 184 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 185 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 198 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 199 unsigned Amt = ARM_AM [all...] |
H A D | Thumb2InstrInfo.cpp | 235 ARM_AM::getT2SOImmVal(NumBytes) == -1) { 300 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { 305 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); 307 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && 313 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { 322 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); 324 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && 485 if (ARM_AM::getT2SOImmVal(Offset) != -1) { 511 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt); 516 assert(ARM_AM [all...] |
H A D | ARMFastISel.cpp | 163 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy); 476 Imm = ARM_AM::getFP64Imm(Val); 479 Imm = ARM_AM::getFP32Imm(Val); 531 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 532 (ARM_AM::getSOImmVal(Imm) != -1); 1388 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 1389 (ARM_AM::getSOImmVal(Imm) != -1); 1643 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 1644 (ARM_AM::getSOImmVal(Imm) != -1); 2630 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM [all...] |
H A D | ARMBaseRegisterInfo.cpp | 461 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 462 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 469 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 470 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 476 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 477 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
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H A D | ARMMCInstLower.cpp | 156 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm());
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H A D | ARMTargetTransformInfo.cpp | 29 (ARM_AM::getSOImmVal(ZImmVal) != -1) || 30 (ARM_AM::getSOImmVal(~ZImmVal) != -1)) 36 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) || 37 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1)) 44 if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
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H A D | ARMExpandPseudoInsts.cpp | 675 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 676 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 958 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? 959 ARM_AM::lsr : ARM_AM::asr), 971 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
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H A D | ARMFrameLowering.cpp | 274 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero)))); 278 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero)))); 1047 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
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H A D | ARMISelLowering.cpp | 4074 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80); 4097 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), 4964 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); 4983 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal); 5434 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1) 5477 int ImmVal = ARM_AM::getFP32Imm(SplatBits); 7292 .addImm(ARM_AM::getSORegOpc(ARM_AM [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 197 case ARM_AM::da: return 0; 198 case ARM_AM::ia: return 1; 199 case ARM_AM::db: return 2; 200 case ARM_AM::ib: return 3; 205 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 207 case ARM_AM::no_shift: 208 case ARM_AM::lsl: return 0; 209 case ARM_AM [all...] |
H A D | ARMAddressingModes.h | 25 /// ARM_AM - ARM Addressing Mode Stuff 26 namespace ARM_AM { namespace in namespace:llvm 48 case ARM_AM::asr: return "asr"; 49 case ARM_AM::lsl: return "lsl"; 50 case ARM_AM::lsr: return "lsr"; 51 case ARM_AM::ror: return "ror"; 52 case ARM_AM::rrx: return "rrx"; 59 case ARM_AM::asr: return 2; 60 case ARM_AM::lsl: return 0; 61 case ARM_AM [all...] |
H A D | ARMAsmBackend.cpp | 421 if (Ctx && ARM_AM::getSOImmVal(Value) == -1) { 426 return ARM_AM::getSOImmVal(Value) | (opc << 21); 630 Value = ARM_AM::getSOImmVal(Value);
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 43 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, 45 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) 49 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); 52 if (ShOpc != ARM_AM::rrx) { 121 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); 132 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 143 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 204 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 495 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 505 ARM_AM::ShiftOpc ShiftTy; 515 ARM_AM::ShiftOpc ShiftTy; 522 ARM_AM::ShiftOpc ShiftTy; 706 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 977 return (ARM_AM::getSOImmVal(Value) != -1 || 978 ARM_AM::getSOImmVal(-Value) != -1); 985 return ARM_AM::getT2SOImmVal(Value) != -1; 992 return ARM_AM [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1138 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1141 Shift = ARM_AM::lsl; 1144 Shift = ARM_AM::lsr; 1147 Shift = ARM_AM::asr; 1150 Shift = ARM_AM::ror; 1154 if (Shift == ARM_AM::ror && imm == 0) 1155 Shift = ARM_AM::rrx; 1177 ARM_AM::ShiftOpc Shift = ARM_AM [all...] |