1//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the ARMMCCodeEmitter class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "MCTargetDesc/ARMMCTargetDesc.h" 15#include "MCTargetDesc/ARMAddressingModes.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "MCTargetDesc/ARMFixupKinds.h" 18#include "MCTargetDesc/ARMMCExpr.h" 19#include "llvm/ADT/APFloat.h" 20#include "llvm/ADT/Statistic.h" 21#include "llvm/MC/MCCodeEmitter.h" 22#include "llvm/MC/MCContext.h" 23#include "llvm/MC/MCExpr.h" 24#include "llvm/MC/MCInst.h" 25#include "llvm/MC/MCInstrInfo.h" 26#include "llvm/MC/MCRegisterInfo.h" 27#include "llvm/MC/MCSubtargetInfo.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/raw_ostream.h" 30 31using namespace llvm; 32 33#define DEBUG_TYPE "mccodeemitter" 34 35STATISTIC(MCNumEmitted, "Number of MC instructions emitted."); 36STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created."); 37 38namespace { 39class ARMMCCodeEmitter : public MCCodeEmitter { 40 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete; 41 void operator=(const ARMMCCodeEmitter &) = delete; 42 const MCInstrInfo &MCII; 43 const MCContext &CTX; 44 bool IsLittleEndian; 45 46public: 47 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle) 48 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) { 49 } 50 51 ~ARMMCCodeEmitter() override {} 52 53 bool isThumb(const MCSubtargetInfo &STI) const { 54 return STI.getFeatureBits()[ARM::ModeThumb]; 55 } 56 bool isThumb2(const MCSubtargetInfo &STI) const { 57 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; 58 } 59 bool isTargetMachO(const MCSubtargetInfo &STI) const { 60 const Triple &TT = STI.getTargetTriple(); 61 return TT.isOSBinFormatMachO(); 62 } 63 64 unsigned getMachineSoImmOpValue(unsigned SoImm) const; 65 66 // getBinaryCodeForInstr - TableGen'erated function for getting the 67 // binary encoding for an instruction. 68 uint64_t getBinaryCodeForInstr(const MCInst &MI, 69 SmallVectorImpl<MCFixup> &Fixups, 70 const MCSubtargetInfo &STI) const; 71 72 /// getMachineOpValue - Return binary encoding of operand. If the machine 73 /// operand requires relocation, record the relocation and return zero. 74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 75 SmallVectorImpl<MCFixup> &Fixups, 76 const MCSubtargetInfo &STI) const; 77 78 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of 79 /// the specified operand. This is used for operands with :lower16: and 80 /// :upper16: prefixes. 81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 82 SmallVectorImpl<MCFixup> &Fixups, 83 const MCSubtargetInfo &STI) const; 84 85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 86 unsigned &Reg, unsigned &Imm, 87 SmallVectorImpl<MCFixup> &Fixups, 88 const MCSubtargetInfo &STI) const; 89 90 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate 91 /// BL branch target. 92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 93 SmallVectorImpl<MCFixup> &Fixups, 94 const MCSubtargetInfo &STI) const; 95 96 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 97 /// BLX branch target. 98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 99 SmallVectorImpl<MCFixup> &Fixups, 100 const MCSubtargetInfo &STI) const; 101 102 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 104 SmallVectorImpl<MCFixup> &Fixups, 105 const MCSubtargetInfo &STI) const; 106 107 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 109 SmallVectorImpl<MCFixup> &Fixups, 110 const MCSubtargetInfo &STI) const; 111 112 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 114 SmallVectorImpl<MCFixup> &Fixups, 115 const MCSubtargetInfo &STI) const; 116 117 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate 118 /// branch target. 119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 120 SmallVectorImpl<MCFixup> &Fixups, 121 const MCSubtargetInfo &STI) const; 122 123 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 124 /// immediate Thumb2 direct branch target. 125 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 126 SmallVectorImpl<MCFixup> &Fixups, 127 const MCSubtargetInfo &STI) const; 128 129 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate 130 /// branch target. 131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 132 SmallVectorImpl<MCFixup> &Fixups, 133 const MCSubtargetInfo &STI) const; 134 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 135 SmallVectorImpl<MCFixup> &Fixups, 136 const MCSubtargetInfo &STI) const; 137 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 138 SmallVectorImpl<MCFixup> &Fixups, 139 const MCSubtargetInfo &STI) const; 140 141 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate 142 /// ADR label target. 143 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 144 SmallVectorImpl<MCFixup> &Fixups, 145 const MCSubtargetInfo &STI) const; 146 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 147 SmallVectorImpl<MCFixup> &Fixups, 148 const MCSubtargetInfo &STI) const; 149 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 150 SmallVectorImpl<MCFixup> &Fixups, 151 const MCSubtargetInfo &STI) const; 152 153 154 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' 155 /// operand. 156 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 157 SmallVectorImpl<MCFixup> &Fixups, 158 const MCSubtargetInfo &STI) const; 159 160 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. 161 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 162 SmallVectorImpl<MCFixup> &Fixups, 163 const MCSubtargetInfo &STI) const; 164 165 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' 166 /// operand. 167 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 168 SmallVectorImpl<MCFixup> &Fixups, 169 const MCSubtargetInfo &STI) const; 170 171 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' 172 /// operand. 173 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 174 SmallVectorImpl<MCFixup> &Fixups, 175 const MCSubtargetInfo &STI) const; 176 177 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2' 178 /// operand. 179 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 180 SmallVectorImpl<MCFixup> &Fixups, 181 const MCSubtargetInfo &STI) const; 182 183 184 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' 185 /// operand as needed by load/store instructions. 186 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 187 SmallVectorImpl<MCFixup> &Fixups, 188 const MCSubtargetInfo &STI) const; 189 190 /// getLdStmModeOpValue - Return encoding for load/store multiple mode. 191 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, 192 SmallVectorImpl<MCFixup> &Fixups, 193 const MCSubtargetInfo &STI) const { 194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 195 switch (Mode) { 196 default: llvm_unreachable("Unknown addressing sub-mode!"); 197 case ARM_AM::da: return 0; 198 case ARM_AM::ia: return 1; 199 case ARM_AM::db: return 2; 200 case ARM_AM::ib: return 3; 201 } 202 } 203 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 204 /// 205 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 206 switch (ShOpc) { 207 case ARM_AM::no_shift: 208 case ARM_AM::lsl: return 0; 209 case ARM_AM::lsr: return 1; 210 case ARM_AM::asr: return 2; 211 case ARM_AM::ror: 212 case ARM_AM::rrx: return 3; 213 } 214 llvm_unreachable("Invalid ShiftOpc!"); 215 } 216 217 /// getAddrMode2OpValue - Return encoding for addrmode2 operands. 218 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, 219 SmallVectorImpl<MCFixup> &Fixups, 220 const MCSubtargetInfo &STI) const; 221 222 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. 223 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 224 SmallVectorImpl<MCFixup> &Fixups, 225 const MCSubtargetInfo &STI) const; 226 227 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands. 228 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 229 SmallVectorImpl<MCFixup> &Fixups, 230 const MCSubtargetInfo &STI) const; 231 232 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. 233 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 234 SmallVectorImpl<MCFixup> &Fixups, 235 const MCSubtargetInfo &STI) const; 236 237 /// getAddrMode3OpValue - Return encoding for addrmode3 operands. 238 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 239 SmallVectorImpl<MCFixup> &Fixups, 240 const MCSubtargetInfo &STI) const; 241 242 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' 243 /// operand. 244 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 245 SmallVectorImpl<MCFixup> &Fixups, 246 const MCSubtargetInfo &STI) const; 247 248 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 249 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 250 SmallVectorImpl<MCFixup> &Fixups, 251 const MCSubtargetInfo &STI) const; 252 253 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 254 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 255 SmallVectorImpl<MCFixup> &Fixups, 256 const MCSubtargetInfo &STI) const; 257 258 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. 259 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 260 SmallVectorImpl<MCFixup> &Fixups, 261 const MCSubtargetInfo &STI) const; 262 263 /// getCCOutOpValue - Return encoding of the 's' bit. 264 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, 265 SmallVectorImpl<MCFixup> &Fixups, 266 const MCSubtargetInfo &STI) const { 267 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or 268 // '1' respectively. 269 return MI.getOperand(Op).getReg() == ARM::CPSR; 270 } 271 272 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value. 273 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op, 274 SmallVectorImpl<MCFixup> &Fixups, 275 const MCSubtargetInfo &STI) const { 276 277 const MCOperand &MO = MI.getOperand(Op); 278 279 // We expect MO to be an immediate or an expression, 280 // if it is an immediate - that's fine, just encode the value. 281 // Otherwise - create a Fixup. 282 if (MO.isExpr()) { 283 const MCExpr *Expr = MO.getExpr(); 284 // In instruction code this value always encoded as lowest 12 bits, 285 // so we don't have to perform any specific adjustments. 286 // Due to requirements of relocatable records we have to use FK_Data_4. 287 // See ARMELFObjectWriter::ExplicitRelSym and 288 // ARMELFObjectWriter::GetRelocTypeInner for more details. 289 MCFixupKind Kind = MCFixupKind(FK_Data_4); 290 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 291 return 0; 292 } 293 294 unsigned SoImm = MO.getImm(); 295 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 296 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 297 298 // Encode rotate_imm. 299 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 300 << ARMII::SoRotImmShift; 301 302 // Encode immed_8. 303 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 304 return Binary; 305 } 306 307 unsigned getModImmOpValue(const MCInst &MI, unsigned Op, 308 SmallVectorImpl<MCFixup> &Fixups, 309 const MCSubtargetInfo &ST) const { 310 const MCOperand &MO = MI.getOperand(Op); 311 312 // Support for fixups (MCFixup) 313 if (MO.isExpr()) { 314 const MCExpr *Expr = MO.getExpr(); 315 // Fixups resolve to plain values that need to be encoded. 316 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm); 317 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 318 return 0; 319 } 320 321 // Immediate is already in its encoded format 322 return MO.getImm(); 323 } 324 325 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. 326 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, 327 SmallVectorImpl<MCFixup> &Fixups, 328 const MCSubtargetInfo &STI) const { 329 unsigned SoImm = MI.getOperand(Op).getImm(); 330 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); 331 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); 332 return Encoded; 333 } 334 335 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 336 SmallVectorImpl<MCFixup> &Fixups, 337 const MCSubtargetInfo &STI) const; 338 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 339 SmallVectorImpl<MCFixup> &Fixups, 340 const MCSubtargetInfo &STI) const; 341 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 342 SmallVectorImpl<MCFixup> &Fixups, 343 const MCSubtargetInfo &STI) const; 344 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, 345 SmallVectorImpl<MCFixup> &Fixups, 346 const MCSubtargetInfo &STI) const; 347 348 /// getSORegOpValue - Return an encoded so_reg shifted register value. 349 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, 350 SmallVectorImpl<MCFixup> &Fixups, 351 const MCSubtargetInfo &STI) const; 352 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, 353 SmallVectorImpl<MCFixup> &Fixups, 354 const MCSubtargetInfo &STI) const; 355 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, 356 SmallVectorImpl<MCFixup> &Fixups, 357 const MCSubtargetInfo &STI) const; 358 359 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, 360 SmallVectorImpl<MCFixup> &Fixups, 361 const MCSubtargetInfo &STI) const { 362 return 64 - MI.getOperand(Op).getImm(); 363 } 364 365 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 366 SmallVectorImpl<MCFixup> &Fixups, 367 const MCSubtargetInfo &STI) const; 368 369 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, 370 SmallVectorImpl<MCFixup> &Fixups, 371 const MCSubtargetInfo &STI) const; 372 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 373 SmallVectorImpl<MCFixup> &Fixups, 374 const MCSubtargetInfo &STI) const; 375 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 376 SmallVectorImpl<MCFixup> &Fixups, 377 const MCSubtargetInfo &STI) const; 378 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 379 SmallVectorImpl<MCFixup> &Fixups, 380 const MCSubtargetInfo &STI) const; 381 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 382 SmallVectorImpl<MCFixup> &Fixups, 383 const MCSubtargetInfo &STI) const; 384 385 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, 386 SmallVectorImpl<MCFixup> &Fixups, 387 const MCSubtargetInfo &STI) const; 388 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, 389 SmallVectorImpl<MCFixup> &Fixups, 390 const MCSubtargetInfo &STI) const; 391 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, 392 SmallVectorImpl<MCFixup> &Fixups, 393 const MCSubtargetInfo &STI) const; 394 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, 395 SmallVectorImpl<MCFixup> &Fixups, 396 const MCSubtargetInfo &STI) const; 397 398 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, 399 SmallVectorImpl<MCFixup> &Fixups, 400 const MCSubtargetInfo &STI) const; 401 402 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, 403 unsigned EncodedValue, 404 const MCSubtargetInfo &STI) const; 405 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, 406 unsigned EncodedValue, 407 const MCSubtargetInfo &STI) const; 408 unsigned NEONThumb2DupPostEncoder(const MCInst &MI, 409 unsigned EncodedValue, 410 const MCSubtargetInfo &STI) const; 411 unsigned NEONThumb2V8PostEncoder(const MCInst &MI, 412 unsigned EncodedValue, 413 const MCSubtargetInfo &STI) const; 414 415 unsigned VFPThumb2PostEncoder(const MCInst &MI, 416 unsigned EncodedValue, 417 const MCSubtargetInfo &STI) const; 418 419 void EmitByte(unsigned char C, raw_ostream &OS) const { 420 OS << (char)C; 421 } 422 423 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const { 424 // Output the constant in little endian byte order. 425 for (unsigned i = 0; i != Size; ++i) { 426 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; 427 EmitByte((Val >> Shift) & 0xff, OS); 428 } 429 } 430 431 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 432 SmallVectorImpl<MCFixup> &Fixups, 433 const MCSubtargetInfo &STI) const override; 434}; 435 436} // end anonymous namespace 437 438MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 439 const MCRegisterInfo &MRI, 440 MCContext &Ctx) { 441 return new ARMMCCodeEmitter(MCII, Ctx, true); 442} 443 444MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII, 445 const MCRegisterInfo &MRI, 446 MCContext &Ctx) { 447 return new ARMMCCodeEmitter(MCII, Ctx, false); 448} 449 450/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing 451/// instructions, and rewrite them to their Thumb2 form if we are currently in 452/// Thumb2 mode. 453unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, 454 unsigned EncodedValue, 455 const MCSubtargetInfo &STI) const { 456 if (isThumb2(STI)) { 457 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved 458 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are 459 // set to 1111. 460 unsigned Bit24 = EncodedValue & 0x01000000; 461 unsigned Bit28 = Bit24 << 4; 462 EncodedValue &= 0xEFFFFFFF; 463 EncodedValue |= Bit28; 464 EncodedValue |= 0x0F000000; 465 } 466 467 return EncodedValue; 468} 469 470/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store 471/// instructions, and rewrite them to their Thumb2 form if we are currently in 472/// Thumb2 mode. 473unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, 474 unsigned EncodedValue, 475 const MCSubtargetInfo &STI) const { 476 if (isThumb2(STI)) { 477 EncodedValue &= 0xF0FFFFFF; 478 EncodedValue |= 0x09000000; 479 } 480 481 return EncodedValue; 482} 483 484/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup 485/// instructions, and rewrite them to their Thumb2 form if we are currently in 486/// Thumb2 mode. 487unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, 488 unsigned EncodedValue, 489 const MCSubtargetInfo &STI) const { 490 if (isThumb2(STI)) { 491 EncodedValue &= 0x00FFFFFF; 492 EncodedValue |= 0xEE000000; 493 } 494 495 return EncodedValue; 496} 497 498/// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form 499/// if we are in Thumb2. 500unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI, 501 unsigned EncodedValue, 502 const MCSubtargetInfo &STI) const { 503 if (isThumb2(STI)) { 504 EncodedValue |= 0xC000000; // Set bits 27-26 505 } 506 507 return EncodedValue; 508} 509 510/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite 511/// them to their Thumb2 form if we are currently in Thumb2 mode. 512unsigned ARMMCCodeEmitter:: 513VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue, 514 const MCSubtargetInfo &STI) const { 515 if (isThumb2(STI)) { 516 EncodedValue &= 0x0FFFFFFF; 517 EncodedValue |= 0xE0000000; 518 } 519 return EncodedValue; 520} 521 522/// getMachineOpValue - Return binary encoding of operand. If the machine 523/// operand requires relocation, record the relocation and return zero. 524unsigned ARMMCCodeEmitter:: 525getMachineOpValue(const MCInst &MI, const MCOperand &MO, 526 SmallVectorImpl<MCFixup> &Fixups, 527 const MCSubtargetInfo &STI) const { 528 if (MO.isReg()) { 529 unsigned Reg = MO.getReg(); 530 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 531 532 // Q registers are encoded as 2x their register number. 533 switch (Reg) { 534 default: 535 return RegNo; 536 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: 537 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: 538 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: 539 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: 540 return 2 * RegNo; 541 } 542 } else if (MO.isImm()) { 543 return static_cast<unsigned>(MO.getImm()); 544 } else if (MO.isFPImm()) { 545 return static_cast<unsigned>(APFloat(MO.getFPImm()) 546 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 547 } 548 549 llvm_unreachable("Unable to encode MCOperand!"); 550} 551 552/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. 553bool ARMMCCodeEmitter:: 554EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, 555 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, 556 const MCSubtargetInfo &STI) const { 557 const MCOperand &MO = MI.getOperand(OpIdx); 558 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 559 560 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 561 562 int32_t SImm = MO1.getImm(); 563 bool isAdd = true; 564 565 // Special value for #-0 566 if (SImm == INT32_MIN) { 567 SImm = 0; 568 isAdd = false; 569 } 570 571 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 572 if (SImm < 0) { 573 SImm = -SImm; 574 isAdd = false; 575 } 576 577 Imm = SImm; 578 return isAdd; 579} 580 581/// getBranchTargetOpValue - Helper function to get the branch target operand, 582/// which is either an immediate or requires a fixup. 583static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 584 unsigned FixupKind, 585 SmallVectorImpl<MCFixup> &Fixups, 586 const MCSubtargetInfo &STI) { 587 const MCOperand &MO = MI.getOperand(OpIdx); 588 589 // If the destination is an immediate, we have nothing to do. 590 if (MO.isImm()) return MO.getImm(); 591 assert(MO.isExpr() && "Unexpected branch target type!"); 592 const MCExpr *Expr = MO.getExpr(); 593 MCFixupKind Kind = MCFixupKind(FixupKind); 594 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 595 596 // All of the information is in the fixup. 597 return 0; 598} 599 600// Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are 601// determined by negating them and XOR'ing them with bit 23. 602static int32_t encodeThumbBLOffset(int32_t offset) { 603 offset >>= 1; 604 uint32_t S = (offset & 0x800000) >> 23; 605 uint32_t J1 = (offset & 0x400000) >> 22; 606 uint32_t J2 = (offset & 0x200000) >> 21; 607 J1 = (~J1 & 0x1); 608 J2 = (~J2 & 0x1); 609 J1 ^= S; 610 J2 ^= S; 611 612 offset &= ~0x600000; 613 offset |= J1 << 22; 614 offset |= J2 << 21; 615 616 return offset; 617} 618 619/// getThumbBLTargetOpValue - Return encoding info for immediate branch target. 620uint32_t ARMMCCodeEmitter:: 621getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 622 SmallVectorImpl<MCFixup> &Fixups, 623 const MCSubtargetInfo &STI) const { 624 const MCOperand MO = MI.getOperand(OpIdx); 625 if (MO.isExpr()) 626 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, 627 Fixups, STI); 628 return encodeThumbBLOffset(MO.getImm()); 629} 630 631/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 632/// BLX branch target. 633uint32_t ARMMCCodeEmitter:: 634getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 635 SmallVectorImpl<MCFixup> &Fixups, 636 const MCSubtargetInfo &STI) const { 637 const MCOperand MO = MI.getOperand(OpIdx); 638 if (MO.isExpr()) 639 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, 640 Fixups, STI); 641 return encodeThumbBLOffset(MO.getImm()); 642} 643 644/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 645uint32_t ARMMCCodeEmitter:: 646getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 647 SmallVectorImpl<MCFixup> &Fixups, 648 const MCSubtargetInfo &STI) const { 649 const MCOperand MO = MI.getOperand(OpIdx); 650 if (MO.isExpr()) 651 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, 652 Fixups, STI); 653 return (MO.getImm() >> 1); 654} 655 656/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 657uint32_t ARMMCCodeEmitter:: 658getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 659 SmallVectorImpl<MCFixup> &Fixups, 660 const MCSubtargetInfo &STI) const { 661 const MCOperand MO = MI.getOperand(OpIdx); 662 if (MO.isExpr()) 663 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, 664 Fixups, STI); 665 return (MO.getImm() >> 1); 666} 667 668/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 669uint32_t ARMMCCodeEmitter:: 670getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 671 SmallVectorImpl<MCFixup> &Fixups, 672 const MCSubtargetInfo &STI) const { 673 const MCOperand MO = MI.getOperand(OpIdx); 674 if (MO.isExpr()) 675 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI); 676 return (MO.getImm() >> 1); 677} 678 679/// Return true if this branch has a non-always predication 680static bool HasConditionalBranch(const MCInst &MI) { 681 int NumOp = MI.getNumOperands(); 682 if (NumOp >= 2) { 683 for (int i = 0; i < NumOp-1; ++i) { 684 const MCOperand &MCOp1 = MI.getOperand(i); 685 const MCOperand &MCOp2 = MI.getOperand(i + 1); 686 if (MCOp1.isImm() && MCOp2.isReg() && 687 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { 688 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) 689 return true; 690 } 691 } 692 } 693 return false; 694} 695 696/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 697/// target. 698uint32_t ARMMCCodeEmitter:: 699getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 700 SmallVectorImpl<MCFixup> &Fixups, 701 const MCSubtargetInfo &STI) const { 702 // FIXME: This really, really shouldn't use TargetMachine. We don't want 703 // coupling between MC and TM anywhere we can help it. 704 if (isThumb2(STI)) 705 return 706 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI); 707 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI); 708} 709 710/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 711/// target. 712uint32_t ARMMCCodeEmitter:: 713getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 714 SmallVectorImpl<MCFixup> &Fixups, 715 const MCSubtargetInfo &STI) const { 716 const MCOperand MO = MI.getOperand(OpIdx); 717 if (MO.isExpr()) { 718 if (HasConditionalBranch(MI)) 719 return ::getBranchTargetOpValue(MI, OpIdx, 720 ARM::fixup_arm_condbranch, Fixups, STI); 721 return ::getBranchTargetOpValue(MI, OpIdx, 722 ARM::fixup_arm_uncondbranch, Fixups, STI); 723 } 724 725 return MO.getImm() >> 2; 726} 727 728uint32_t ARMMCCodeEmitter:: 729getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 730 SmallVectorImpl<MCFixup> &Fixups, 731 const MCSubtargetInfo &STI) const { 732 const MCOperand MO = MI.getOperand(OpIdx); 733 if (MO.isExpr()) { 734 if (HasConditionalBranch(MI)) 735 return ::getBranchTargetOpValue(MI, OpIdx, 736 ARM::fixup_arm_condbl, Fixups, STI); 737 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI); 738 } 739 740 return MO.getImm() >> 2; 741} 742 743uint32_t ARMMCCodeEmitter:: 744getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 745 SmallVectorImpl<MCFixup> &Fixups, 746 const MCSubtargetInfo &STI) const { 747 const MCOperand MO = MI.getOperand(OpIdx); 748 if (MO.isExpr()) 749 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI); 750 751 return MO.getImm() >> 1; 752} 753 754/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 755/// immediate branch target. 756uint32_t ARMMCCodeEmitter:: 757getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 758 SmallVectorImpl<MCFixup> &Fixups, 759 const MCSubtargetInfo &STI) const { 760 unsigned Val = 0; 761 const MCOperand MO = MI.getOperand(OpIdx); 762 763 if(MO.isExpr()) 764 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI); 765 else 766 Val = MO.getImm() >> 1; 767 768 bool I = (Val & 0x800000); 769 bool J1 = (Val & 0x400000); 770 bool J2 = (Val & 0x200000); 771 if (I ^ J1) 772 Val &= ~0x400000; 773 else 774 Val |= 0x400000; 775 776 if (I ^ J2) 777 Val &= ~0x200000; 778 else 779 Val |= 0x200000; 780 781 return Val; 782} 783 784/// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate 785/// ADR label target. 786uint32_t ARMMCCodeEmitter:: 787getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 788 SmallVectorImpl<MCFixup> &Fixups, 789 const MCSubtargetInfo &STI) const { 790 const MCOperand MO = MI.getOperand(OpIdx); 791 if (MO.isExpr()) 792 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, 793 Fixups, STI); 794 int64_t offset = MO.getImm(); 795 uint32_t Val = 0x2000; 796 797 int SoImmVal; 798 if (offset == INT32_MIN) { 799 Val = 0x1000; 800 SoImmVal = 0; 801 } else if (offset < 0) { 802 Val = 0x1000; 803 offset *= -1; 804 SoImmVal = ARM_AM::getSOImmVal(offset); 805 if(SoImmVal == -1) { 806 Val = 0x2000; 807 offset *= -1; 808 SoImmVal = ARM_AM::getSOImmVal(offset); 809 } 810 } else { 811 SoImmVal = ARM_AM::getSOImmVal(offset); 812 if(SoImmVal == -1) { 813 Val = 0x1000; 814 offset *= -1; 815 SoImmVal = ARM_AM::getSOImmVal(offset); 816 } 817 } 818 819 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 820 821 Val |= SoImmVal; 822 return Val; 823} 824 825/// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 826/// target. 827uint32_t ARMMCCodeEmitter:: 828getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 829 SmallVectorImpl<MCFixup> &Fixups, 830 const MCSubtargetInfo &STI) const { 831 const MCOperand MO = MI.getOperand(OpIdx); 832 if (MO.isExpr()) 833 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, 834 Fixups, STI); 835 int32_t Val = MO.getImm(); 836 if (Val == INT32_MIN) 837 Val = 0x1000; 838 else if (Val < 0) { 839 Val *= -1; 840 Val |= 0x1000; 841 } 842 return Val; 843} 844 845/// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label 846/// target. 847uint32_t ARMMCCodeEmitter:: 848getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 849 SmallVectorImpl<MCFixup> &Fixups, 850 const MCSubtargetInfo &STI) const { 851 const MCOperand MO = MI.getOperand(OpIdx); 852 if (MO.isExpr()) 853 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, 854 Fixups, STI); 855 return MO.getImm(); 856} 857 858/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' 859/// operand. 860uint32_t ARMMCCodeEmitter:: 861getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 862 SmallVectorImpl<MCFixup> &, 863 const MCSubtargetInfo &STI) const { 864 // [Rn, Rm] 865 // {5-3} = Rm 866 // {2-0} = Rn 867 const MCOperand &MO1 = MI.getOperand(OpIdx); 868 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); 869 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 870 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 871 return (Rm << 3) | Rn; 872} 873 874/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. 875uint32_t ARMMCCodeEmitter:: 876getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 877 SmallVectorImpl<MCFixup> &Fixups, 878 const MCSubtargetInfo &STI) const { 879 // {17-13} = reg 880 // {12} = (U)nsigned (add == '1', sub == '0') 881 // {11-0} = imm12 882 unsigned Reg, Imm12; 883 bool isAdd = true; 884 // If The first operand isn't a register, we have a label reference. 885 const MCOperand &MO = MI.getOperand(OpIdx); 886 if (!MO.isReg()) { 887 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 888 Imm12 = 0; 889 890 if (MO.isExpr()) { 891 const MCExpr *Expr = MO.getExpr(); 892 isAdd = false ; // 'U' bit is set as part of the fixup. 893 894 MCFixupKind Kind; 895 if (isThumb2(STI)) 896 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); 897 else 898 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); 899 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 900 901 ++MCNumCPRelocations; 902 } else { 903 Reg = ARM::PC; 904 int32_t Offset = MO.getImm(); 905 if (Offset == INT32_MIN) { 906 Offset = 0; 907 isAdd = false; 908 } else if (Offset < 0) { 909 Offset *= -1; 910 isAdd = false; 911 } 912 Imm12 = Offset; 913 } 914 } else 915 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); 916 917 uint32_t Binary = Imm12 & 0xfff; 918 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 919 if (isAdd) 920 Binary |= (1 << 12); 921 Binary |= (Reg << 13); 922 return Binary; 923} 924 925/// getT2Imm8s4OpValue - Return encoding info for 926/// '+/- imm8<<2' operand. 927uint32_t ARMMCCodeEmitter:: 928getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 929 SmallVectorImpl<MCFixup> &Fixups, 930 const MCSubtargetInfo &STI) const { 931 // FIXME: The immediate operand should have already been encoded like this 932 // before ever getting here. The encoder method should just need to combine 933 // the MI operands for the register and the offset into a single 934 // representation for the complex operand in the .td file. This isn't just 935 // style, unfortunately. As-is, we can't represent the distinct encoding 936 // for #-0. 937 938 // {8} = (U)nsigned (add == '1', sub == '0') 939 // {7-0} = imm8 940 int32_t Imm8 = MI.getOperand(OpIdx).getImm(); 941 bool isAdd = Imm8 >= 0; 942 943 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 944 if (Imm8 < 0) 945 Imm8 = -(uint32_t)Imm8; 946 947 // Scaled by 4. 948 Imm8 /= 4; 949 950 uint32_t Binary = Imm8 & 0xff; 951 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 952 if (isAdd) 953 Binary |= (1 << 8); 954 return Binary; 955} 956 957/// getT2AddrModeImm8s4OpValue - Return encoding info for 958/// 'reg +/- imm8<<2' operand. 959uint32_t ARMMCCodeEmitter:: 960getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 961 SmallVectorImpl<MCFixup> &Fixups, 962 const MCSubtargetInfo &STI) const { 963 // {12-9} = reg 964 // {8} = (U)nsigned (add == '1', sub == '0') 965 // {7-0} = imm8 966 unsigned Reg, Imm8; 967 bool isAdd = true; 968 // If The first operand isn't a register, we have a label reference. 969 const MCOperand &MO = MI.getOperand(OpIdx); 970 if (!MO.isReg()) { 971 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 972 Imm8 = 0; 973 isAdd = false ; // 'U' bit is set as part of the fixup. 974 975 assert(MO.isExpr() && "Unexpected machine operand type!"); 976 const MCExpr *Expr = MO.getExpr(); 977 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 978 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 979 980 ++MCNumCPRelocations; 981 } else 982 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 983 984 // FIXME: The immediate operand should have already been encoded like this 985 // before ever getting here. The encoder method should just need to combine 986 // the MI operands for the register and the offset into a single 987 // representation for the complex operand in the .td file. This isn't just 988 // style, unfortunately. As-is, we can't represent the distinct encoding 989 // for #-0. 990 uint32_t Binary = (Imm8 >> 2) & 0xff; 991 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 992 if (isAdd) 993 Binary |= (1 << 8); 994 Binary |= (Reg << 9); 995 return Binary; 996} 997 998/// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 999/// 'reg + imm8<<2' operand. 1000uint32_t ARMMCCodeEmitter:: 1001getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 1002 SmallVectorImpl<MCFixup> &Fixups, 1003 const MCSubtargetInfo &STI) const { 1004 // {11-8} = reg 1005 // {7-0} = imm8 1006 const MCOperand &MO = MI.getOperand(OpIdx); 1007 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1008 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1009 unsigned Imm8 = MO1.getImm(); 1010 return (Reg << 8) | Imm8; 1011} 1012 1013uint32_t 1014ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 1015 SmallVectorImpl<MCFixup> &Fixups, 1016 const MCSubtargetInfo &STI) const { 1017 // {20-16} = imm{15-12} 1018 // {11-0} = imm{11-0} 1019 const MCOperand &MO = MI.getOperand(OpIdx); 1020 if (MO.isImm()) 1021 // Hi / lo 16 bits already extracted during earlier passes. 1022 return static_cast<unsigned>(MO.getImm()); 1023 1024 // Handle :upper16: and :lower16: assembly prefixes. 1025 const MCExpr *E = MO.getExpr(); 1026 MCFixupKind Kind; 1027 if (E->getKind() == MCExpr::Target) { 1028 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E); 1029 E = ARM16Expr->getSubExpr(); 1030 1031 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) { 1032 const int64_t Value = MCE->getValue(); 1033 if (Value > UINT32_MAX) 1034 report_fatal_error("constant value truncated (limited to 32-bit)"); 1035 1036 switch (ARM16Expr->getKind()) { 1037 case ARMMCExpr::VK_ARM_HI16: 1038 return (int32_t(Value) & 0xffff0000) >> 16; 1039 case ARMMCExpr::VK_ARM_LO16: 1040 return (int32_t(Value) & 0x0000ffff); 1041 default: llvm_unreachable("Unsupported ARMFixup"); 1042 } 1043 } 1044 1045 switch (ARM16Expr->getKind()) { 1046 default: llvm_unreachable("Unsupported ARMFixup"); 1047 case ARMMCExpr::VK_ARM_HI16: 1048 Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movt_hi16 1049 : ARM::fixup_arm_movt_hi16); 1050 break; 1051 case ARMMCExpr::VK_ARM_LO16: 1052 Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movw_lo16 1053 : ARM::fixup_arm_movw_lo16); 1054 break; 1055 } 1056 1057 Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc())); 1058 return 0; 1059 } 1060 // If the expression doesn't have :upper16: or :lower16: on it, 1061 // it's just a plain immediate expression, previously those evaluated to 1062 // the lower 16 bits of the expression regardless of whether 1063 // we have a movt or a movw, but that led to misleadingly results. 1064 // This is disallowed in the AsmParser in validateInstruction() 1065 // so this should never happen. 1066 llvm_unreachable("expression without :upper16: or :lower16:"); 1067} 1068 1069uint32_t ARMMCCodeEmitter:: 1070getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 1071 SmallVectorImpl<MCFixup> &Fixups, 1072 const MCSubtargetInfo &STI) const { 1073 const MCOperand &MO = MI.getOperand(OpIdx); 1074 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1075 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1076 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1077 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1078 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 1079 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 1080 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 1081 unsigned SBits = getShiftOp(ShOp); 1082 1083 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift 1084 // amount. However, it would be an easy mistake to make so check here. 1085 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount"); 1086 1087 // {16-13} = Rn 1088 // {12} = isAdd 1089 // {11-0} = shifter 1090 // {3-0} = Rm 1091 // {4} = 0 1092 // {6-5} = type 1093 // {11-7} = imm 1094 uint32_t Binary = Rm; 1095 Binary |= Rn << 13; 1096 Binary |= SBits << 5; 1097 Binary |= ShImm << 7; 1098 if (isAdd) 1099 Binary |= 1 << 12; 1100 return Binary; 1101} 1102 1103uint32_t ARMMCCodeEmitter:: 1104getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, 1105 SmallVectorImpl<MCFixup> &Fixups, 1106 const MCSubtargetInfo &STI) const { 1107 // {17-14} Rn 1108 // {13} 1 == imm12, 0 == Rm 1109 // {12} isAdd 1110 // {11-0} imm12/Rm 1111 const MCOperand &MO = MI.getOperand(OpIdx); 1112 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1113 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI); 1114 Binary |= Rn << 14; 1115 return Binary; 1116} 1117 1118uint32_t ARMMCCodeEmitter:: 1119getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1120 SmallVectorImpl<MCFixup> &Fixups, 1121 const MCSubtargetInfo &STI) const { 1122 // {13} 1 == imm12, 0 == Rm 1123 // {12} isAdd 1124 // {11-0} imm12/Rm 1125 const MCOperand &MO = MI.getOperand(OpIdx); 1126 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1127 unsigned Imm = MO1.getImm(); 1128 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; 1129 bool isReg = MO.getReg() != 0; 1130 uint32_t Binary = ARM_AM::getAM2Offset(Imm); 1131 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12 1132 if (isReg) { 1133 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); 1134 Binary <<= 7; // Shift amount is bits [11:7] 1135 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] 1136 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0] 1137 } 1138 return Binary | (isAdd << 12) | (isReg << 13); 1139} 1140 1141uint32_t ARMMCCodeEmitter:: 1142getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 1143 SmallVectorImpl<MCFixup> &Fixups, 1144 const MCSubtargetInfo &STI) const { 1145 // {4} isAdd 1146 // {3-0} Rm 1147 const MCOperand &MO = MI.getOperand(OpIdx); 1148 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1149 bool isAdd = MO1.getImm() != 0; 1150 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4); 1151} 1152 1153uint32_t ARMMCCodeEmitter:: 1154getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1155 SmallVectorImpl<MCFixup> &Fixups, 1156 const MCSubtargetInfo &STI) const { 1157 // {9} 1 == imm8, 0 == Rm 1158 // {8} isAdd 1159 // {7-4} imm7_4/zero 1160 // {3-0} imm3_0/Rm 1161 const MCOperand &MO = MI.getOperand(OpIdx); 1162 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1163 unsigned Imm = MO1.getImm(); 1164 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1165 bool isImm = MO.getReg() == 0; 1166 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1167 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1168 if (!isImm) 1169 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1170 return Imm8 | (isAdd << 8) | (isImm << 9); 1171} 1172 1173uint32_t ARMMCCodeEmitter:: 1174getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 1175 SmallVectorImpl<MCFixup> &Fixups, 1176 const MCSubtargetInfo &STI) const { 1177 // {13} 1 == imm8, 0 == Rm 1178 // {12-9} Rn 1179 // {8} isAdd 1180 // {7-4} imm7_4/zero 1181 // {3-0} imm3_0/Rm 1182 const MCOperand &MO = MI.getOperand(OpIdx); 1183 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1184 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1185 1186 // If The first operand isn't a register, we have a label reference. 1187 if (!MO.isReg()) { 1188 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1189 1190 assert(MO.isExpr() && "Unexpected machine operand type!"); 1191 const MCExpr *Expr = MO.getExpr(); 1192 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled); 1193 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1194 1195 ++MCNumCPRelocations; 1196 return (Rn << 9) | (1 << 13); 1197 } 1198 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1199 unsigned Imm = MO2.getImm(); 1200 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1201 bool isImm = MO1.getReg() == 0; 1202 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1203 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1204 if (!isImm) 1205 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1206 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); 1207} 1208 1209/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. 1210uint32_t ARMMCCodeEmitter:: 1211getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 1212 SmallVectorImpl<MCFixup> &Fixups, 1213 const MCSubtargetInfo &STI) const { 1214 // [SP, #imm] 1215 // {7-0} = imm8 1216 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1217 assert(MI.getOperand(OpIdx).getReg() == ARM::SP && 1218 "Unexpected base register!"); 1219 1220 // The immediate is already shifted for the implicit zeroes, so no change 1221 // here. 1222 return MO1.getImm() & 0xff; 1223} 1224 1225/// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 1226uint32_t ARMMCCodeEmitter:: 1227getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 1228 SmallVectorImpl<MCFixup> &Fixups, 1229 const MCSubtargetInfo &STI) const { 1230 // [Rn, #imm] 1231 // {7-3} = imm5 1232 // {2-0} = Rn 1233 const MCOperand &MO = MI.getOperand(OpIdx); 1234 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1235 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1236 unsigned Imm5 = MO1.getImm(); 1237 return ((Imm5 & 0x1f) << 3) | Rn; 1238} 1239 1240/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 1241uint32_t ARMMCCodeEmitter:: 1242getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 1243 SmallVectorImpl<MCFixup> &Fixups, 1244 const MCSubtargetInfo &STI) const { 1245 const MCOperand MO = MI.getOperand(OpIdx); 1246 if (MO.isExpr()) 1247 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI); 1248 return (MO.getImm() >> 2); 1249} 1250 1251/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand. 1252uint32_t ARMMCCodeEmitter:: 1253getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 1254 SmallVectorImpl<MCFixup> &Fixups, 1255 const MCSubtargetInfo &STI) const { 1256 // {12-9} = reg 1257 // {8} = (U)nsigned (add == '1', sub == '0') 1258 // {7-0} = imm8 1259 unsigned Reg, Imm8; 1260 bool isAdd; 1261 // If The first operand isn't a register, we have a label reference. 1262 const MCOperand &MO = MI.getOperand(OpIdx); 1263 if (!MO.isReg()) { 1264 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1265 Imm8 = 0; 1266 isAdd = false; // 'U' bit is handled as part of the fixup. 1267 1268 assert(MO.isExpr() && "Unexpected machine operand type!"); 1269 const MCExpr *Expr = MO.getExpr(); 1270 MCFixupKind Kind; 1271 if (isThumb2(STI)) 1272 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 1273 else 1274 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); 1275 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1276 1277 ++MCNumCPRelocations; 1278 } else { 1279 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1280 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1281 } 1282 1283 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1284 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1285 if (isAdd) 1286 Binary |= (1 << 8); 1287 Binary |= (Reg << 9); 1288 return Binary; 1289} 1290 1291unsigned ARMMCCodeEmitter:: 1292getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, 1293 SmallVectorImpl<MCFixup> &Fixups, 1294 const MCSubtargetInfo &STI) const { 1295 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be 1296 // shifted. The second is Rs, the amount to shift by, and the third specifies 1297 // the type of the shift. 1298 // 1299 // {3-0} = Rm. 1300 // {4} = 1 1301 // {6-5} = type 1302 // {11-8} = Rs 1303 // {7} = 0 1304 1305 const MCOperand &MO = MI.getOperand(OpIdx); 1306 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1307 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); 1308 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1309 1310 // Encode Rm. 1311 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1312 1313 // Encode the shift opcode. 1314 unsigned SBits = 0; 1315 unsigned Rs = MO1.getReg(); 1316 if (Rs) { 1317 // Set shift operand (bit[7:4]). 1318 // LSL - 0001 1319 // LSR - 0011 1320 // ASR - 0101 1321 // ROR - 0111 1322 switch (SOpc) { 1323 default: llvm_unreachable("Unknown shift opc!"); 1324 case ARM_AM::lsl: SBits = 0x1; break; 1325 case ARM_AM::lsr: SBits = 0x3; break; 1326 case ARM_AM::asr: SBits = 0x5; break; 1327 case ARM_AM::ror: SBits = 0x7; break; 1328 } 1329 } 1330 1331 Binary |= SBits << 4; 1332 1333 // Encode the shift operation Rs. 1334 // Encode Rs bit[11:8]. 1335 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1336 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift); 1337} 1338 1339unsigned ARMMCCodeEmitter:: 1340getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, 1341 SmallVectorImpl<MCFixup> &Fixups, 1342 const MCSubtargetInfo &STI) const { 1343 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1344 // shifted. The second is the amount to shift by. 1345 // 1346 // {3-0} = Rm. 1347 // {4} = 0 1348 // {6-5} = type 1349 // {11-7} = imm 1350 1351 const MCOperand &MO = MI.getOperand(OpIdx); 1352 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1353 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1354 1355 // Encode Rm. 1356 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1357 1358 // Encode the shift opcode. 1359 unsigned SBits = 0; 1360 1361 // Set shift operand (bit[6:4]). 1362 // LSL - 000 1363 // LSR - 010 1364 // ASR - 100 1365 // ROR - 110 1366 // RRX - 110 and bit[11:8] clear. 1367 switch (SOpc) { 1368 default: llvm_unreachable("Unknown shift opc!"); 1369 case ARM_AM::lsl: SBits = 0x0; break; 1370 case ARM_AM::lsr: SBits = 0x2; break; 1371 case ARM_AM::asr: SBits = 0x4; break; 1372 case ARM_AM::ror: SBits = 0x6; break; 1373 case ARM_AM::rrx: 1374 Binary |= 0x60; 1375 return Binary; 1376 } 1377 1378 // Encode shift_imm bit[11:7]. 1379 Binary |= SBits << 4; 1380 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm()); 1381 assert(Offset < 32 && "Offset must be in range 0-31!"); 1382 return Binary | (Offset << 7); 1383} 1384 1385 1386unsigned ARMMCCodeEmitter:: 1387getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 1388 SmallVectorImpl<MCFixup> &Fixups, 1389 const MCSubtargetInfo &STI) const { 1390 const MCOperand &MO1 = MI.getOperand(OpNum); 1391 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1392 const MCOperand &MO3 = MI.getOperand(OpNum+2); 1393 1394 // Encoded as [Rn, Rm, imm]. 1395 // FIXME: Needs fixup support. 1396 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1397 Value <<= 4; 1398 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 1399 Value <<= 2; 1400 Value |= MO3.getImm(); 1401 1402 return Value; 1403} 1404 1405unsigned ARMMCCodeEmitter:: 1406getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 1407 SmallVectorImpl<MCFixup> &Fixups, 1408 const MCSubtargetInfo &STI) const { 1409 const MCOperand &MO1 = MI.getOperand(OpNum); 1410 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1411 1412 // FIXME: Needs fixup support. 1413 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1414 1415 // Even though the immediate is 8 bits long, we need 9 bits in order 1416 // to represent the (inverse of the) sign bit. 1417 Value <<= 9; 1418 int32_t tmp = (int32_t)MO2.getImm(); 1419 if (tmp < 0) 1420 tmp = abs(tmp); 1421 else 1422 Value |= 256; // Set the ADD bit 1423 Value |= tmp & 255; 1424 return Value; 1425} 1426 1427unsigned ARMMCCodeEmitter:: 1428getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 1429 SmallVectorImpl<MCFixup> &Fixups, 1430 const MCSubtargetInfo &STI) const { 1431 const MCOperand &MO1 = MI.getOperand(OpNum); 1432 1433 // FIXME: Needs fixup support. 1434 unsigned Value = 0; 1435 int32_t tmp = (int32_t)MO1.getImm(); 1436 if (tmp < 0) 1437 tmp = abs(tmp); 1438 else 1439 Value |= 256; // Set the ADD bit 1440 Value |= tmp & 255; 1441 return Value; 1442} 1443 1444unsigned ARMMCCodeEmitter:: 1445getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, 1446 SmallVectorImpl<MCFixup> &Fixups, 1447 const MCSubtargetInfo &STI) const { 1448 const MCOperand &MO1 = MI.getOperand(OpNum); 1449 1450 // FIXME: Needs fixup support. 1451 unsigned Value = 0; 1452 int32_t tmp = (int32_t)MO1.getImm(); 1453 if (tmp < 0) 1454 tmp = abs(tmp); 1455 else 1456 Value |= 4096; // Set the ADD bit 1457 Value |= tmp & 4095; 1458 return Value; 1459} 1460 1461unsigned ARMMCCodeEmitter:: 1462getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, 1463 SmallVectorImpl<MCFixup> &Fixups, 1464 const MCSubtargetInfo &STI) const { 1465 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1466 // shifted. The second is the amount to shift by. 1467 // 1468 // {3-0} = Rm. 1469 // {4} = 0 1470 // {6-5} = type 1471 // {11-7} = imm 1472 1473 const MCOperand &MO = MI.getOperand(OpIdx); 1474 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1475 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1476 1477 // Encode Rm. 1478 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1479 1480 // Encode the shift opcode. 1481 unsigned SBits = 0; 1482 // Set shift operand (bit[6:4]). 1483 // LSL - 000 1484 // LSR - 010 1485 // ASR - 100 1486 // ROR - 110 1487 switch (SOpc) { 1488 default: llvm_unreachable("Unknown shift opc!"); 1489 case ARM_AM::lsl: SBits = 0x0; break; 1490 case ARM_AM::lsr: SBits = 0x2; break; 1491 case ARM_AM::asr: SBits = 0x4; break; 1492 case ARM_AM::rrx: // FALLTHROUGH 1493 case ARM_AM::ror: SBits = 0x6; break; 1494 } 1495 1496 Binary |= SBits << 4; 1497 if (SOpc == ARM_AM::rrx) 1498 return Binary; 1499 1500 // Encode shift_imm bit[11:7]. 1501 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; 1502} 1503 1504unsigned ARMMCCodeEmitter:: 1505getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 1506 SmallVectorImpl<MCFixup> &Fixups, 1507 const MCSubtargetInfo &STI) const { 1508 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the 1509 // msb of the mask. 1510 const MCOperand &MO = MI.getOperand(Op); 1511 uint32_t v = ~MO.getImm(); 1512 uint32_t lsb = countTrailingZeros(v); 1513 uint32_t msb = (32 - countLeadingZeros (v)) - 1; 1514 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!"); 1515 return lsb | (msb << 5); 1516} 1517 1518unsigned ARMMCCodeEmitter:: 1519getRegisterListOpValue(const MCInst &MI, unsigned Op, 1520 SmallVectorImpl<MCFixup> &Fixups, 1521 const MCSubtargetInfo &STI) const { 1522 // VLDM/VSTM: 1523 // {12-8} = Vd 1524 // {7-0} = Number of registers 1525 // 1526 // LDM/STM: 1527 // {15-0} = Bitfield of GPRs. 1528 unsigned Reg = MI.getOperand(Op).getReg(); 1529 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg); 1530 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg); 1531 1532 unsigned Binary = 0; 1533 1534 if (SPRRegs || DPRRegs) { 1535 // VLDM/VSTM 1536 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 1537 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; 1538 Binary |= (RegNo & 0x1f) << 8; 1539 if (SPRRegs) 1540 Binary |= NumRegs; 1541 else 1542 Binary |= NumRegs * 2; 1543 } else { 1544 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) { 1545 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg()); 1546 Binary |= 1 << RegNo; 1547 } 1548 } 1549 1550 return Binary; 1551} 1552 1553/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along 1554/// with the alignment operand. 1555unsigned ARMMCCodeEmitter:: 1556getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 1557 SmallVectorImpl<MCFixup> &Fixups, 1558 const MCSubtargetInfo &STI) const { 1559 const MCOperand &Reg = MI.getOperand(Op); 1560 const MCOperand &Imm = MI.getOperand(Op + 1); 1561 1562 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1563 unsigned Align = 0; 1564 1565 switch (Imm.getImm()) { 1566 default: break; 1567 case 2: 1568 case 4: 1569 case 8: Align = 0x01; break; 1570 case 16: Align = 0x02; break; 1571 case 32: Align = 0x03; break; 1572 } 1573 1574 return RegNo | (Align << 4); 1575} 1576 1577/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number 1578/// along with the alignment operand for use in VST1 and VLD1 with size 32. 1579unsigned ARMMCCodeEmitter:: 1580getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 1581 SmallVectorImpl<MCFixup> &Fixups, 1582 const MCSubtargetInfo &STI) const { 1583 const MCOperand &Reg = MI.getOperand(Op); 1584 const MCOperand &Imm = MI.getOperand(Op + 1); 1585 1586 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1587 unsigned Align = 0; 1588 1589 switch (Imm.getImm()) { 1590 default: break; 1591 case 8: 1592 case 16: 1593 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes. 1594 case 2: Align = 0x00; break; 1595 case 4: Align = 0x03; break; 1596 } 1597 1598 return RegNo | (Align << 4); 1599} 1600 1601 1602/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and 1603/// alignment operand for use in VLD-dup instructions. This is the same as 1604/// getAddrMode6AddressOpValue except for the alignment encoding, which is 1605/// different for VLD4-dup. 1606unsigned ARMMCCodeEmitter:: 1607getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 1608 SmallVectorImpl<MCFixup> &Fixups, 1609 const MCSubtargetInfo &STI) const { 1610 const MCOperand &Reg = MI.getOperand(Op); 1611 const MCOperand &Imm = MI.getOperand(Op + 1); 1612 1613 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1614 unsigned Align = 0; 1615 1616 switch (Imm.getImm()) { 1617 default: break; 1618 case 2: 1619 case 4: 1620 case 8: Align = 0x01; break; 1621 case 16: Align = 0x03; break; 1622 } 1623 1624 return RegNo | (Align << 4); 1625} 1626 1627unsigned ARMMCCodeEmitter:: 1628getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 1629 SmallVectorImpl<MCFixup> &Fixups, 1630 const MCSubtargetInfo &STI) const { 1631 const MCOperand &MO = MI.getOperand(Op); 1632 if (MO.getReg() == 0) return 0x0D; 1633 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1634} 1635 1636unsigned ARMMCCodeEmitter:: 1637getShiftRight8Imm(const MCInst &MI, unsigned Op, 1638 SmallVectorImpl<MCFixup> &Fixups, 1639 const MCSubtargetInfo &STI) const { 1640 return 8 - MI.getOperand(Op).getImm(); 1641} 1642 1643unsigned ARMMCCodeEmitter:: 1644getShiftRight16Imm(const MCInst &MI, unsigned Op, 1645 SmallVectorImpl<MCFixup> &Fixups, 1646 const MCSubtargetInfo &STI) const { 1647 return 16 - MI.getOperand(Op).getImm(); 1648} 1649 1650unsigned ARMMCCodeEmitter:: 1651getShiftRight32Imm(const MCInst &MI, unsigned Op, 1652 SmallVectorImpl<MCFixup> &Fixups, 1653 const MCSubtargetInfo &STI) const { 1654 return 32 - MI.getOperand(Op).getImm(); 1655} 1656 1657unsigned ARMMCCodeEmitter:: 1658getShiftRight64Imm(const MCInst &MI, unsigned Op, 1659 SmallVectorImpl<MCFixup> &Fixups, 1660 const MCSubtargetInfo &STI) const { 1661 return 64 - MI.getOperand(Op).getImm(); 1662} 1663 1664void ARMMCCodeEmitter:: 1665encodeInstruction(const MCInst &MI, raw_ostream &OS, 1666 SmallVectorImpl<MCFixup> &Fixups, 1667 const MCSubtargetInfo &STI) const { 1668 // Pseudo instructions don't get encoded. 1669 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1670 uint64_t TSFlags = Desc.TSFlags; 1671 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) 1672 return; 1673 1674 int Size; 1675 if (Desc.getSize() == 2 || Desc.getSize() == 4) 1676 Size = Desc.getSize(); 1677 else 1678 llvm_unreachable("Unexpected instruction size!"); 1679 1680 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI); 1681 // Thumb 32-bit wide instructions need to emit the high order halfword 1682 // first. 1683 if (isThumb(STI) && Size == 4) { 1684 EmitConstant(Binary >> 16, 2, OS); 1685 EmitConstant(Binary & 0xffff, 2, OS); 1686 } else 1687 EmitConstant(Binary, Size, OS); 1688 ++MCNumEmitted; // Keep track of the # of mi's emitted. 1689} 1690 1691#include "ARMGenMCCodeEmitter.inc" 1692