Target/ARM/ARMFastISel.cpp

163     bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
476       Imm = ARM_AM::getFP64Imm(Val);
479       Imm = ARM_AM::getFP32Imm(Val);
531     bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
532       (ARM_AM::getSOImmVal(Imm) != -1);
1388       UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1389         (ARM_AM::getSOImmVal(Imm) != -1);
1643     UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1644       (ARM_AM::getSOImmVal(Imm) != -1);
2630         /*  1 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  31 },
2631         /*  1 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  31 } },
2632         /*  8 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  24 },
2633         /*  8 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  24 } },
2634         /* 16 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  16 },
2635         /* 16 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  16 } }
2638         /*  1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  31 },
2639         /*  1 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  31 } },
2640         /*  8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  24 },
2641         /*  8 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  24 } },
2642         /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  16 },
2643         /* 16 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  16 } }
2648         /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },
2649         /*  1 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift,   1 } },
2650         /*  8 bit sext */ { { ARM::SXTB   , 0, ARM_AM::no_shift,   0 },
2651         /*  8 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift, 255 } },
2652         /* 16 bit sext */ { { ARM::SXTH   , 0, ARM_AM::no_shift,   0 },
2653         /* 16 bit zext */   { ARM::UXTH   , 0, ARM_AM::no_shift,   0 } }
2656         /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },
2657         /*  1 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift,   1 } },
2658         /*  8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift,   0 },
2659         /*  8 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2660         /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift,   0 },
2661         /* 16 bit zext */   { ARM::t2UXTH , 0, ARM_AM::no_shift,   0 } }
2685   ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2686   assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2697   bool ImmIsSO = (Shift != ARM_AM::no_shift);
2712     ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2713     unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2756                               ARM_AM::ShiftOpc ShiftTy) {
2799     MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2802     MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2871       return SelectShift(I, ARM_AM::lsl);
2873       return SelectShift(I, ARM_AM::lsr);
2875       return SelectShift(I, ARM_AM::asr);