1//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This class prints an ARM MCInst to a .s file. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMInstPrinter.h" 15#include "MCTargetDesc/ARMAddressingModes.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "llvm/MC/MCAsmInfo.h" 18#include "llvm/MC/MCExpr.h" 19#include "llvm/MC/MCInst.h" 20#include "llvm/MC/MCInstrInfo.h" 21#include "llvm/MC/MCRegisterInfo.h" 22#include "llvm/MC/MCSubtargetInfo.h" 23#include "llvm/Support/raw_ostream.h" 24using namespace llvm; 25 26#define DEBUG_TYPE "asm-printer" 27 28#include "ARMGenAsmWriter.inc" 29 30/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing. 31/// 32/// getSORegOffset returns an integer from 0-31, representing '32' as 0. 33static unsigned translateShiftImm(unsigned imm) { 34 // lsr #32 and asr #32 exist, but should be encoded as a 0. 35 assert((imm & ~0x1f) == 0 && "Invalid shift encoding"); 36 37 if (imm == 0) 38 return 32; 39 return imm; 40} 41 42/// Prints the shift value with an immediate value. 43static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, 44 unsigned ShImm, bool UseMarkup) { 45 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) 46 return; 47 O << ", "; 48 49 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); 50 O << getShiftOpcStr(ShOpc); 51 52 if (ShOpc != ARM_AM::rrx) { 53 O << " "; 54 if (UseMarkup) 55 O << "<imm:"; 56 O << "#" << translateShiftImm(ShImm); 57 if (UseMarkup) 58 O << ">"; 59 } 60} 61 62ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, 63 const MCRegisterInfo &MRI) 64 : MCInstPrinter(MAI, MII, MRI) {} 65 66void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 67 OS << markup("<reg:") << getRegisterName(RegNo) << markup(">"); 68} 69 70void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, 71 StringRef Annot, const MCSubtargetInfo &STI) { 72 unsigned Opcode = MI->getOpcode(); 73 74 switch (Opcode) { 75 76 // Check for HINT instructions w/ canonical names. 77 case ARM::HINT: 78 case ARM::tHINT: 79 case ARM::t2HINT: 80 switch (MI->getOperand(0).getImm()) { 81 case 0: 82 O << "\tnop"; 83 break; 84 case 1: 85 O << "\tyield"; 86 break; 87 case 2: 88 O << "\twfe"; 89 break; 90 case 3: 91 O << "\twfi"; 92 break; 93 case 4: 94 O << "\tsev"; 95 break; 96 case 5: 97 if (STI.getFeatureBits()[ARM::HasV8Ops]) { 98 O << "\tsevl"; 99 break; 100 } // Fallthrough for non-v8 101 default: 102 // Anything else should just print normally. 103 printInstruction(MI, STI, O); 104 printAnnotation(O, Annot); 105 return; 106 } 107 printPredicateOperand(MI, 1, STI, O); 108 if (Opcode == ARM::t2HINT) 109 O << ".w"; 110 printAnnotation(O, Annot); 111 return; 112 113 // Check for MOVs and print canonical forms, instead. 114 case ARM::MOVsr: { 115 // FIXME: Thumb variants? 116 const MCOperand &Dst = MI->getOperand(0); 117 const MCOperand &MO1 = MI->getOperand(1); 118 const MCOperand &MO2 = MI->getOperand(2); 119 const MCOperand &MO3 = MI->getOperand(3); 120 121 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); 122 printSBitModifierOperand(MI, 6, STI, O); 123 printPredicateOperand(MI, 4, STI, O); 124 125 O << '\t'; 126 printRegName(O, Dst.getReg()); 127 O << ", "; 128 printRegName(O, MO1.getReg()); 129 130 O << ", "; 131 printRegName(O, MO2.getReg()); 132 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 133 printAnnotation(O, Annot); 134 return; 135 } 136 137 case ARM::MOVsi: { 138 // FIXME: Thumb variants? 139 const MCOperand &Dst = MI->getOperand(0); 140 const MCOperand &MO1 = MI->getOperand(1); 141 const MCOperand &MO2 = MI->getOperand(2); 142 143 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); 144 printSBitModifierOperand(MI, 5, STI, O); 145 printPredicateOperand(MI, 3, STI, O); 146 147 O << '\t'; 148 printRegName(O, Dst.getReg()); 149 O << ", "; 150 printRegName(O, MO1.getReg()); 151 152 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { 153 printAnnotation(O, Annot); 154 return; 155 } 156 157 O << ", " << markup("<imm:") << "#" 158 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); 159 printAnnotation(O, Annot); 160 return; 161 } 162 163 // A8.6.123 PUSH 164 case ARM::STMDB_UPD: 165 case ARM::t2STMDB_UPD: 166 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 167 // Should only print PUSH if there are at least two registers in the list. 168 O << '\t' << "push"; 169 printPredicateOperand(MI, 2, STI, O); 170 if (Opcode == ARM::t2STMDB_UPD) 171 O << ".w"; 172 O << '\t'; 173 printRegisterList(MI, 4, STI, O); 174 printAnnotation(O, Annot); 175 return; 176 } else 177 break; 178 179 case ARM::STR_PRE_IMM: 180 if (MI->getOperand(2).getReg() == ARM::SP && 181 MI->getOperand(3).getImm() == -4) { 182 O << '\t' << "push"; 183 printPredicateOperand(MI, 4, STI, O); 184 O << "\t{"; 185 printRegName(O, MI->getOperand(1).getReg()); 186 O << "}"; 187 printAnnotation(O, Annot); 188 return; 189 } else 190 break; 191 192 // A8.6.122 POP 193 case ARM::LDMIA_UPD: 194 case ARM::t2LDMIA_UPD: 195 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 196 // Should only print POP if there are at least two registers in the list. 197 O << '\t' << "pop"; 198 printPredicateOperand(MI, 2, STI, O); 199 if (Opcode == ARM::t2LDMIA_UPD) 200 O << ".w"; 201 O << '\t'; 202 printRegisterList(MI, 4, STI, O); 203 printAnnotation(O, Annot); 204 return; 205 } else 206 break; 207 208 case ARM::LDR_POST_IMM: 209 if (MI->getOperand(2).getReg() == ARM::SP && 210 MI->getOperand(4).getImm() == 4) { 211 O << '\t' << "pop"; 212 printPredicateOperand(MI, 5, STI, O); 213 O << "\t{"; 214 printRegName(O, MI->getOperand(0).getReg()); 215 O << "}"; 216 printAnnotation(O, Annot); 217 return; 218 } else 219 break; 220 221 // A8.6.355 VPUSH 222 case ARM::VSTMSDB_UPD: 223 case ARM::VSTMDDB_UPD: 224 if (MI->getOperand(0).getReg() == ARM::SP) { 225 O << '\t' << "vpush"; 226 printPredicateOperand(MI, 2, STI, O); 227 O << '\t'; 228 printRegisterList(MI, 4, STI, O); 229 printAnnotation(O, Annot); 230 return; 231 } else 232 break; 233 234 // A8.6.354 VPOP 235 case ARM::VLDMSIA_UPD: 236 case ARM::VLDMDIA_UPD: 237 if (MI->getOperand(0).getReg() == ARM::SP) { 238 O << '\t' << "vpop"; 239 printPredicateOperand(MI, 2, STI, O); 240 O << '\t'; 241 printRegisterList(MI, 4, STI, O); 242 printAnnotation(O, Annot); 243 return; 244 } else 245 break; 246 247 case ARM::tLDMIA: { 248 bool Writeback = true; 249 unsigned BaseReg = MI->getOperand(0).getReg(); 250 for (unsigned i = 3; i < MI->getNumOperands(); ++i) { 251 if (MI->getOperand(i).getReg() == BaseReg) 252 Writeback = false; 253 } 254 255 O << "\tldm"; 256 257 printPredicateOperand(MI, 1, STI, O); 258 O << '\t'; 259 printRegName(O, BaseReg); 260 if (Writeback) 261 O << "!"; 262 O << ", "; 263 printRegisterList(MI, 3, STI, O); 264 printAnnotation(O, Annot); 265 return; 266 } 267 268 // Combine 2 GPRs from disassember into a GPRPair to match with instr def. 269 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, 270 // a single GPRPair reg operand is used in the .td file to replace the two 271 // GPRs. However, when decoding them, the two GRPs cannot be automatically 272 // expressed as a GPRPair, so we have to manually merge them. 273 // FIXME: We would really like to be able to tablegen'erate this. 274 case ARM::LDREXD: 275 case ARM::STREXD: 276 case ARM::LDAEXD: 277 case ARM::STLEXD: { 278 const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID); 279 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD; 280 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg(); 281 if (MRC.contains(Reg)) { 282 MCInst NewMI; 283 MCOperand NewReg; 284 NewMI.setOpcode(Opcode); 285 286 if (isStore) 287 NewMI.addOperand(MI->getOperand(0)); 288 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg( 289 Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID))); 290 NewMI.addOperand(NewReg); 291 292 // Copy the rest operands into NewMI. 293 for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i) 294 NewMI.addOperand(MI->getOperand(i)); 295 printInstruction(&NewMI, STI, O); 296 return; 297 } 298 break; 299 } 300 // B9.3.3 ERET (Thumb) 301 // For a target that has Virtualization Extensions, ERET is the preferred 302 // disassembly of SUBS PC, LR, #0 303 case ARM::t2SUBS_PC_LR: { 304 if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() && 305 MI->getOperand(0).getImm() == 0 && 306 STI.getFeatureBits()[ARM::FeatureVirtualization]) { 307 O << "\teret"; 308 printPredicateOperand(MI, 1, STI, O); 309 printAnnotation(O, Annot); 310 return; 311 } 312 break; 313 } 314 } 315 316 printInstruction(MI, STI, O); 317 printAnnotation(O, Annot); 318} 319 320void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 321 const MCSubtargetInfo &STI, raw_ostream &O) { 322 const MCOperand &Op = MI->getOperand(OpNo); 323 if (Op.isReg()) { 324 unsigned Reg = Op.getReg(); 325 printRegName(O, Reg); 326 } else if (Op.isImm()) { 327 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">"); 328 } else { 329 assert(Op.isExpr() && "unknown operand kind in printOperand"); 330 const MCExpr *Expr = Op.getExpr(); 331 switch (Expr->getKind()) { 332 case MCExpr::Binary: 333 O << '#'; 334 Expr->print(O, &MAI); 335 break; 336 case MCExpr::Constant: { 337 // If a symbolic branch target was added as a constant expression then 338 // print that address in hex. And only print 32 unsigned bits for the 339 // address. 340 const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr); 341 int64_t TargetAddress; 342 if (!Constant->evaluateAsAbsolute(TargetAddress)) { 343 O << '#'; 344 Expr->print(O, &MAI); 345 } else { 346 O << "0x"; 347 O.write_hex(static_cast<uint32_t>(TargetAddress)); 348 } 349 break; 350 } 351 default: 352 // FIXME: Should we always treat this as if it is a constant literal and 353 // prefix it with '#'? 354 Expr->print(O, &MAI); 355 break; 356 } 357 } 358} 359 360void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, 361 const MCSubtargetInfo &STI, 362 raw_ostream &O) { 363 const MCOperand &MO1 = MI->getOperand(OpNum); 364 if (MO1.isExpr()) { 365 MO1.getExpr()->print(O, &MAI); 366 return; 367 } 368 369 O << markup("<mem:") << "[pc, "; 370 371 int32_t OffImm = (int32_t)MO1.getImm(); 372 bool isSub = OffImm < 0; 373 374 // Special value for #-0. All others are normal. 375 if (OffImm == INT32_MIN) 376 OffImm = 0; 377 if (isSub) { 378 O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">"); 379 } else { 380 O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">"); 381 } 382 O << "]" << markup(">"); 383} 384 385// so_reg is a 4-operand unit corresponding to register forms of the A5.1 386// "Addressing Mode 1 - Data-processing operands" forms. This includes: 387// REG 0 0 - e.g. R5 388// REG REG 0,SH_OPC - e.g. R5, ROR R3 389// REG 0 IMM,SH_OPC - e.g. R5, LSL #3 390void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum, 391 const MCSubtargetInfo &STI, 392 raw_ostream &O) { 393 const MCOperand &MO1 = MI->getOperand(OpNum); 394 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 395 const MCOperand &MO3 = MI->getOperand(OpNum + 2); 396 397 printRegName(O, MO1.getReg()); 398 399 // Print the shift opc. 400 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); 401 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); 402 if (ShOpc == ARM_AM::rrx) 403 return; 404 405 O << ' '; 406 printRegName(O, MO2.getReg()); 407 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 408} 409 410void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, 411 const MCSubtargetInfo &STI, 412 raw_ostream &O) { 413 const MCOperand &MO1 = MI->getOperand(OpNum); 414 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 415 416 printRegName(O, MO1.getReg()); 417 418 // Print the shift opc. 419 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), 420 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup); 421} 422 423//===--------------------------------------------------------------------===// 424// Addressing Mode #2 425//===--------------------------------------------------------------------===// 426 427void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, 428 const MCSubtargetInfo &STI, 429 raw_ostream &O) { 430 const MCOperand &MO1 = MI->getOperand(Op); 431 const MCOperand &MO2 = MI->getOperand(Op + 1); 432 const MCOperand &MO3 = MI->getOperand(Op + 2); 433 434 O << markup("<mem:") << "["; 435 printRegName(O, MO1.getReg()); 436 437 if (!MO2.getReg()) { 438 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0. 439 O << ", " << markup("<imm:") << "#" 440 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) 441 << ARM_AM::getAM2Offset(MO3.getImm()) << markup(">"); 442 } 443 O << "]" << markup(">"); 444 return; 445 } 446 447 O << ", "; 448 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())); 449 printRegName(O, MO2.getReg()); 450 451 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()), 452 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup); 453 O << "]" << markup(">"); 454} 455 456void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op, 457 const MCSubtargetInfo &STI, 458 raw_ostream &O) { 459 const MCOperand &MO1 = MI->getOperand(Op); 460 const MCOperand &MO2 = MI->getOperand(Op + 1); 461 O << markup("<mem:") << "["; 462 printRegName(O, MO1.getReg()); 463 O << ", "; 464 printRegName(O, MO2.getReg()); 465 O << "]" << markup(">"); 466} 467 468void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op, 469 const MCSubtargetInfo &STI, 470 raw_ostream &O) { 471 const MCOperand &MO1 = MI->getOperand(Op); 472 const MCOperand &MO2 = MI->getOperand(Op + 1); 473 O << markup("<mem:") << "["; 474 printRegName(O, MO1.getReg()); 475 O << ", "; 476 printRegName(O, MO2.getReg()); 477 O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">"); 478} 479 480void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op, 481 const MCSubtargetInfo &STI, 482 raw_ostream &O) { 483 const MCOperand &MO1 = MI->getOperand(Op); 484 485 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 486 printOperand(MI, Op, STI, O); 487 return; 488 } 489 490#ifndef NDEBUG 491 const MCOperand &MO3 = MI->getOperand(Op + 2); 492 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm()); 493 assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op"); 494#endif 495 496 printAM2PreOrOffsetIndexOp(MI, Op, STI, O); 497} 498 499void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, 500 unsigned OpNum, 501 const MCSubtargetInfo &STI, 502 raw_ostream &O) { 503 const MCOperand &MO1 = MI->getOperand(OpNum); 504 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 505 506 if (!MO1.getReg()) { 507 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm()); 508 O << markup("<imm:") << '#' 509 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << ImmOffs 510 << markup(">"); 511 return; 512 } 513 514 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())); 515 printRegName(O, MO1.getReg()); 516 517 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()), 518 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup); 519} 520 521//===--------------------------------------------------------------------===// 522// Addressing Mode #3 523//===--------------------------------------------------------------------===// 524 525void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, 526 raw_ostream &O, 527 bool AlwaysPrintImm0) { 528 const MCOperand &MO1 = MI->getOperand(Op); 529 const MCOperand &MO2 = MI->getOperand(Op + 1); 530 const MCOperand &MO3 = MI->getOperand(Op + 2); 531 532 O << markup("<mem:") << '['; 533 printRegName(O, MO1.getReg()); 534 535 if (MO2.getReg()) { 536 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())); 537 printRegName(O, MO2.getReg()); 538 O << ']' << markup(">"); 539 return; 540 } 541 542 // If the op is sub we have to print the immediate even if it is 0 543 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()); 544 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm()); 545 546 if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) { 547 O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs 548 << markup(">"); 549 } 550 O << ']' << markup(">"); 551} 552 553template <bool AlwaysPrintImm0> 554void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op, 555 const MCSubtargetInfo &STI, 556 raw_ostream &O) { 557 const MCOperand &MO1 = MI->getOperand(Op); 558 if (!MO1.isReg()) { // For label symbolic references. 559 printOperand(MI, Op, STI, O); 560 return; 561 } 562 563 assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) != 564 ARMII::IndexModePost && 565 "unexpected idxmode"); 566 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0); 567} 568 569void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI, 570 unsigned OpNum, 571 const MCSubtargetInfo &STI, 572 raw_ostream &O) { 573 const MCOperand &MO1 = MI->getOperand(OpNum); 574 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 575 576 if (MO1.getReg()) { 577 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())); 578 printRegName(O, MO1.getReg()); 579 return; 580 } 581 582 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm()); 583 O << markup("<imm:") << '#' 584 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs 585 << markup(">"); 586} 587 588void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, 589 const MCSubtargetInfo &STI, 590 raw_ostream &O) { 591 const MCOperand &MO = MI->getOperand(OpNum); 592 unsigned Imm = MO.getImm(); 593 O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff) 594 << markup(">"); 595} 596 597void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, 598 const MCSubtargetInfo &STI, 599 raw_ostream &O) { 600 const MCOperand &MO1 = MI->getOperand(OpNum); 601 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 602 603 O << (MO2.getImm() ? "" : "-"); 604 printRegName(O, MO1.getReg()); 605} 606 607void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, 608 const MCSubtargetInfo &STI, 609 raw_ostream &O) { 610 const MCOperand &MO = MI->getOperand(OpNum); 611 unsigned Imm = MO.getImm(); 612 O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2) 613 << markup(">"); 614} 615 616void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum, 617 const MCSubtargetInfo &STI, 618 raw_ostream &O) { 619 ARM_AM::AMSubMode Mode = 620 ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm()); 621 O << ARM_AM::getAMSubModeStr(Mode); 622} 623 624template <bool AlwaysPrintImm0> 625void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, 626 const MCSubtargetInfo &STI, 627 raw_ostream &O) { 628 const MCOperand &MO1 = MI->getOperand(OpNum); 629 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 630 631 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 632 printOperand(MI, OpNum, STI, O); 633 return; 634 } 635 636 O << markup("<mem:") << "["; 637 printRegName(O, MO1.getReg()); 638 639 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); 640 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm()); 641 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) { 642 O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op) 643 << ImmOffs * 4 << markup(">"); 644 } 645 O << "]" << markup(">"); 646} 647 648void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum, 649 const MCSubtargetInfo &STI, 650 raw_ostream &O) { 651 const MCOperand &MO1 = MI->getOperand(OpNum); 652 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 653 654 O << markup("<mem:") << "["; 655 printRegName(O, MO1.getReg()); 656 if (MO2.getImm()) { 657 O << ":" << (MO2.getImm() << 3); 658 } 659 O << "]" << markup(">"); 660} 661 662void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum, 663 const MCSubtargetInfo &STI, 664 raw_ostream &O) { 665 const MCOperand &MO1 = MI->getOperand(OpNum); 666 O << markup("<mem:") << "["; 667 printRegName(O, MO1.getReg()); 668 O << "]" << markup(">"); 669} 670 671void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI, 672 unsigned OpNum, 673 const MCSubtargetInfo &STI, 674 raw_ostream &O) { 675 const MCOperand &MO = MI->getOperand(OpNum); 676 if (MO.getReg() == 0) 677 O << "!"; 678 else { 679 O << ", "; 680 printRegName(O, MO.getReg()); 681 } 682} 683 684void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI, 685 unsigned OpNum, 686 const MCSubtargetInfo &STI, 687 raw_ostream &O) { 688 const MCOperand &MO = MI->getOperand(OpNum); 689 uint32_t v = ~MO.getImm(); 690 int32_t lsb = countTrailingZeros(v); 691 int32_t width = (32 - countLeadingZeros(v)) - lsb; 692 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); 693 O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:") 694 << '#' << width << markup(">"); 695} 696 697void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum, 698 const MCSubtargetInfo &STI, 699 raw_ostream &O) { 700 unsigned val = MI->getOperand(OpNum).getImm(); 701 O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]); 702} 703 704void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum, 705 const MCSubtargetInfo &STI, 706 raw_ostream &O) { 707 unsigned val = MI->getOperand(OpNum).getImm(); 708 O << ARM_ISB::InstSyncBOptToString(val); 709} 710 711void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum, 712 const MCSubtargetInfo &STI, 713 raw_ostream &O) { 714 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); 715 bool isASR = (ShiftOp & (1 << 5)) != 0; 716 unsigned Amt = ShiftOp & 0x1f; 717 if (isASR) { 718 O << ", asr " << markup("<imm:") << "#" << (Amt == 0 ? 32 : Amt) 719 << markup(">"); 720 } else if (Amt) { 721 O << ", lsl " << markup("<imm:") << "#" << Amt << markup(">"); 722 } 723} 724 725void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, 726 const MCSubtargetInfo &STI, 727 raw_ostream &O) { 728 unsigned Imm = MI->getOperand(OpNum).getImm(); 729 if (Imm == 0) 730 return; 731 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); 732 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">"); 733} 734 735void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, 736 const MCSubtargetInfo &STI, 737 raw_ostream &O) { 738 unsigned Imm = MI->getOperand(OpNum).getImm(); 739 // A shift amount of 32 is encoded as 0. 740 if (Imm == 0) 741 Imm = 32; 742 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); 743 O << ", asr " << markup("<imm:") << "#" << Imm << markup(">"); 744} 745 746void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, 747 const MCSubtargetInfo &STI, 748 raw_ostream &O) { 749 O << "{"; 750 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { 751 if (i != OpNum) 752 O << ", "; 753 printRegName(O, MI->getOperand(i).getReg()); 754 } 755 O << "}"; 756} 757 758void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum, 759 const MCSubtargetInfo &STI, 760 raw_ostream &O) { 761 unsigned Reg = MI->getOperand(OpNum).getReg(); 762 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0)); 763 O << ", "; 764 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1)); 765} 766 767void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum, 768 const MCSubtargetInfo &STI, 769 raw_ostream &O) { 770 const MCOperand &Op = MI->getOperand(OpNum); 771 if (Op.getImm()) 772 O << "be"; 773 else 774 O << "le"; 775} 776 777void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum, 778 const MCSubtargetInfo &STI, raw_ostream &O) { 779 const MCOperand &Op = MI->getOperand(OpNum); 780 O << ARM_PROC::IModToString(Op.getImm()); 781} 782 783void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum, 784 const MCSubtargetInfo &STI, raw_ostream &O) { 785 const MCOperand &Op = MI->getOperand(OpNum); 786 unsigned IFlags = Op.getImm(); 787 for (int i = 2; i >= 0; --i) 788 if (IFlags & (1 << i)) 789 O << ARM_PROC::IFlagsToString(1 << i); 790 791 if (IFlags == 0) 792 O << "none"; 793} 794 795void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, 796 const MCSubtargetInfo &STI, 797 raw_ostream &O) { 798 const MCOperand &Op = MI->getOperand(OpNum); 799 unsigned SpecRegRBit = Op.getImm() >> 4; 800 unsigned Mask = Op.getImm() & 0xf; 801 const FeatureBitset &FeatureBits = STI.getFeatureBits(); 802 803 if (FeatureBits[ARM::FeatureMClass]) { 804 unsigned SYSm = Op.getImm(); 805 unsigned Opcode = MI->getOpcode(); 806 807 // For writes, handle extended mask bits if the DSP extension is present. 808 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) { 809 switch (SYSm) { 810 case 0x400: 811 O << "apsr_g"; 812 return; 813 case 0xc00: 814 O << "apsr_nzcvqg"; 815 return; 816 case 0x401: 817 O << "iapsr_g"; 818 return; 819 case 0xc01: 820 O << "iapsr_nzcvqg"; 821 return; 822 case 0x402: 823 O << "eapsr_g"; 824 return; 825 case 0xc02: 826 O << "eapsr_nzcvqg"; 827 return; 828 case 0x403: 829 O << "xpsr_g"; 830 return; 831 case 0xc03: 832 O << "xpsr_nzcvqg"; 833 return; 834 } 835 } 836 837 // Handle the basic 8-bit mask. 838 SYSm &= 0xff; 839 840 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { 841 // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an 842 // alias for MSR APSR_nzcvq. 843 switch (SYSm) { 844 case 0: 845 O << "apsr_nzcvq"; 846 return; 847 case 1: 848 O << "iapsr_nzcvq"; 849 return; 850 case 2: 851 O << "eapsr_nzcvq"; 852 return; 853 case 3: 854 O << "xpsr_nzcvq"; 855 return; 856 } 857 } 858 859 switch (SYSm) { 860 default: 861 llvm_unreachable("Unexpected mask value!"); 862 case 0: 863 O << "apsr"; 864 return; 865 case 1: 866 O << "iapsr"; 867 return; 868 case 2: 869 O << "eapsr"; 870 return; 871 case 3: 872 O << "xpsr"; 873 return; 874 case 5: 875 O << "ipsr"; 876 return; 877 case 6: 878 O << "epsr"; 879 return; 880 case 7: 881 O << "iepsr"; 882 return; 883 case 8: 884 O << "msp"; 885 return; 886 case 9: 887 O << "psp"; 888 return; 889 case 16: 890 O << "primask"; 891 return; 892 case 17: 893 O << "basepri"; 894 return; 895 case 18: 896 O << "basepri_max"; 897 return; 898 case 19: 899 O << "faultmask"; 900 return; 901 case 20: 902 O << "control"; 903 return; 904 } 905 } 906 907 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as 908 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. 909 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { 910 O << "APSR_"; 911 switch (Mask) { 912 default: 913 llvm_unreachable("Unexpected mask value!"); 914 case 4: 915 O << "g"; 916 return; 917 case 8: 918 O << "nzcvq"; 919 return; 920 case 12: 921 O << "nzcvqg"; 922 return; 923 } 924 } 925 926 if (SpecRegRBit) 927 O << "SPSR"; 928 else 929 O << "CPSR"; 930 931 if (Mask) { 932 O << '_'; 933 if (Mask & 8) 934 O << 'f'; 935 if (Mask & 4) 936 O << 's'; 937 if (Mask & 2) 938 O << 'x'; 939 if (Mask & 1) 940 O << 'c'; 941 } 942} 943 944void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum, 945 const MCSubtargetInfo &STI, 946 raw_ostream &O) { 947 uint32_t Banked = MI->getOperand(OpNum).getImm(); 948 uint32_t R = (Banked & 0x20) >> 5; 949 uint32_t SysM = Banked & 0x1f; 950 951 // Nothing much we can do about this, the encodings are specified in B9.2.3 of 952 // the ARM ARM v7C, and are all over the shop. 953 if (R) { 954 O << "SPSR_"; 955 956 switch (SysM) { 957 case 0x0e: 958 O << "fiq"; 959 return; 960 case 0x10: 961 O << "irq"; 962 return; 963 case 0x12: 964 O << "svc"; 965 return; 966 case 0x14: 967 O << "abt"; 968 return; 969 case 0x16: 970 O << "und"; 971 return; 972 case 0x1c: 973 O << "mon"; 974 return; 975 case 0x1e: 976 O << "hyp"; 977 return; 978 default: 979 llvm_unreachable("Invalid banked SPSR register"); 980 } 981 } 982 983 assert(!R && "should have dealt with SPSR regs"); 984 const char *RegNames[] = { 985 "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr", 986 "", "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", 987 "lr_fiq", "", "lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt", 988 "sp_abt", "lr_und", "sp_und", "", "", "", "", 989 "lr_mon", "sp_mon", "elr_hyp", "sp_hyp"}; 990 const char *Name = RegNames[SysM]; 991 assert(Name[0] && "invalid banked register operand"); 992 993 O << Name; 994} 995 996void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum, 997 const MCSubtargetInfo &STI, 998 raw_ostream &O) { 999 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); 1000 // Handle the undefined 15 CC value here for printing so we don't abort(). 1001 if ((unsigned)CC == 15) 1002 O << "<und>"; 1003 else if (CC != ARMCC::AL) 1004 O << ARMCondCodeToString(CC); 1005} 1006 1007void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI, 1008 unsigned OpNum, 1009 const MCSubtargetInfo &STI, 1010 raw_ostream &O) { 1011 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); 1012 O << ARMCondCodeToString(CC); 1013} 1014 1015void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum, 1016 const MCSubtargetInfo &STI, 1017 raw_ostream &O) { 1018 if (MI->getOperand(OpNum).getReg()) { 1019 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR && 1020 "Expect ARM CPSR register!"); 1021 O << 's'; 1022 } 1023} 1024 1025void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum, 1026 const MCSubtargetInfo &STI, 1027 raw_ostream &O) { 1028 O << MI->getOperand(OpNum).getImm(); 1029} 1030 1031void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum, 1032 const MCSubtargetInfo &STI, 1033 raw_ostream &O) { 1034 O << "p" << MI->getOperand(OpNum).getImm(); 1035} 1036 1037void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum, 1038 const MCSubtargetInfo &STI, 1039 raw_ostream &O) { 1040 O << "c" << MI->getOperand(OpNum).getImm(); 1041} 1042 1043void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum, 1044 const MCSubtargetInfo &STI, 1045 raw_ostream &O) { 1046 O << "{" << MI->getOperand(OpNum).getImm() << "}"; 1047} 1048 1049void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum, 1050 const MCSubtargetInfo &STI, raw_ostream &O) { 1051 llvm_unreachable("Unhandled PC-relative pseudo-instruction!"); 1052} 1053 1054template <unsigned scale> 1055void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum, 1056 const MCSubtargetInfo &STI, 1057 raw_ostream &O) { 1058 const MCOperand &MO = MI->getOperand(OpNum); 1059 1060 if (MO.isExpr()) { 1061 MO.getExpr()->print(O, &MAI); 1062 return; 1063 } 1064 1065 int32_t OffImm = (int32_t)MO.getImm() << scale; 1066 1067 O << markup("<imm:"); 1068 if (OffImm == INT32_MIN) 1069 O << "#-0"; 1070 else if (OffImm < 0) 1071 O << "#-" << -OffImm; 1072 else 1073 O << "#" << OffImm; 1074 O << markup(">"); 1075} 1076 1077void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, 1078 const MCSubtargetInfo &STI, 1079 raw_ostream &O) { 1080 O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4) 1081 << markup(">"); 1082} 1083 1084void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum, 1085 const MCSubtargetInfo &STI, 1086 raw_ostream &O) { 1087 unsigned Imm = MI->getOperand(OpNum).getImm(); 1088 O << markup("<imm:") << "#" << formatImm((Imm == 0 ? 32 : Imm)) 1089 << markup(">"); 1090} 1091 1092void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum, 1093 const MCSubtargetInfo &STI, 1094 raw_ostream &O) { 1095 // (3 - the number of trailing zeros) is the number of then / else. 1096 unsigned Mask = MI->getOperand(OpNum).getImm(); 1097 unsigned Firstcond = MI->getOperand(OpNum - 1).getImm(); 1098 unsigned CondBit0 = Firstcond & 1; 1099 unsigned NumTZ = countTrailingZeros(Mask); 1100 assert(NumTZ <= 3 && "Invalid IT mask!"); 1101 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 1102 bool T = ((Mask >> Pos) & 1) == CondBit0; 1103 if (T) 1104 O << 't'; 1105 else 1106 O << 'e'; 1107 } 1108} 1109 1110void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op, 1111 const MCSubtargetInfo &STI, 1112 raw_ostream &O) { 1113 const MCOperand &MO1 = MI->getOperand(Op); 1114 const MCOperand &MO2 = MI->getOperand(Op + 1); 1115 1116 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 1117 printOperand(MI, Op, STI, O); 1118 return; 1119 } 1120 1121 O << markup("<mem:") << "["; 1122 printRegName(O, MO1.getReg()); 1123 if (unsigned RegNum = MO2.getReg()) { 1124 O << ", "; 1125 printRegName(O, RegNum); 1126 } 1127 O << "]" << markup(">"); 1128} 1129 1130void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI, 1131 unsigned Op, 1132 const MCSubtargetInfo &STI, 1133 raw_ostream &O, 1134 unsigned Scale) { 1135 const MCOperand &MO1 = MI->getOperand(Op); 1136 const MCOperand &MO2 = MI->getOperand(Op + 1); 1137 1138 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 1139 printOperand(MI, Op, STI, O); 1140 return; 1141 } 1142 1143 O << markup("<mem:") << "["; 1144 printRegName(O, MO1.getReg()); 1145 if (unsigned ImmOffs = MO2.getImm()) { 1146 O << ", " << markup("<imm:") << "#" << formatImm(ImmOffs * Scale) 1147 << markup(">"); 1148 } 1149 O << "]" << markup(">"); 1150} 1151 1152void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI, 1153 unsigned Op, 1154 const MCSubtargetInfo &STI, 1155 raw_ostream &O) { 1156 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1); 1157} 1158 1159void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI, 1160 unsigned Op, 1161 const MCSubtargetInfo &STI, 1162 raw_ostream &O) { 1163 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2); 1164} 1165 1166void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI, 1167 unsigned Op, 1168 const MCSubtargetInfo &STI, 1169 raw_ostream &O) { 1170 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4); 1171} 1172 1173void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op, 1174 const MCSubtargetInfo &STI, 1175 raw_ostream &O) { 1176 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4); 1177} 1178 1179// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2 1180// register with shift forms. 1181// REG 0 0 - e.g. R5 1182// REG IMM, SH_OPC - e.g. R5, LSL #3 1183void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum, 1184 const MCSubtargetInfo &STI, 1185 raw_ostream &O) { 1186 const MCOperand &MO1 = MI->getOperand(OpNum); 1187 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 1188 1189 unsigned Reg = MO1.getReg(); 1190 printRegName(O, Reg); 1191 1192 // Print the shift opc. 1193 assert(MO2.isImm() && "Not a valid t2_so_reg value!"); 1194 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), 1195 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup); 1196} 1197 1198template <bool AlwaysPrintImm0> 1199void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, 1200 const MCSubtargetInfo &STI, 1201 raw_ostream &O) { 1202 const MCOperand &MO1 = MI->getOperand(OpNum); 1203 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 1204 1205 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 1206 printOperand(MI, OpNum, STI, O); 1207 return; 1208 } 1209 1210 O << markup("<mem:") << "["; 1211 printRegName(O, MO1.getReg()); 1212 1213 int32_t OffImm = (int32_t)MO2.getImm(); 1214 bool isSub = OffImm < 0; 1215 // Special value for #-0. All others are normal. 1216 if (OffImm == INT32_MIN) 1217 OffImm = 0; 1218 if (isSub) { 1219 O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">"); 1220 } else if (AlwaysPrintImm0 || OffImm > 0) { 1221 O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">"); 1222 } 1223 O << "]" << markup(">"); 1224} 1225 1226template <bool AlwaysPrintImm0> 1227void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, 1228 unsigned OpNum, 1229 const MCSubtargetInfo &STI, 1230 raw_ostream &O) { 1231 const MCOperand &MO1 = MI->getOperand(OpNum); 1232 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 1233 1234 O << markup("<mem:") << "["; 1235 printRegName(O, MO1.getReg()); 1236 1237 int32_t OffImm = (int32_t)MO2.getImm(); 1238 bool isSub = OffImm < 0; 1239 // Don't print +0. 1240 if (OffImm == INT32_MIN) 1241 OffImm = 0; 1242 if (isSub) { 1243 O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">"); 1244 } else if (AlwaysPrintImm0 || OffImm > 0) { 1245 O << ", " << markup("<imm:") << "#" << OffImm << markup(">"); 1246 } 1247 O << "]" << markup(">"); 1248} 1249 1250template <bool AlwaysPrintImm0> 1251void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, 1252 unsigned OpNum, 1253 const MCSubtargetInfo &STI, 1254 raw_ostream &O) { 1255 const MCOperand &MO1 = MI->getOperand(OpNum); 1256 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 1257 1258 if (!MO1.isReg()) { // For label symbolic references. 1259 printOperand(MI, OpNum, STI, O); 1260 return; 1261 } 1262 1263 O << markup("<mem:") << "["; 1264 printRegName(O, MO1.getReg()); 1265 1266 int32_t OffImm = (int32_t)MO2.getImm(); 1267 bool isSub = OffImm < 0; 1268 1269 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); 1270 1271 // Don't print +0. 1272 if (OffImm == INT32_MIN) 1273 OffImm = 0; 1274 if (isSub) { 1275 O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">"); 1276 } else if (AlwaysPrintImm0 || OffImm > 0) { 1277 O << ", " << markup("<imm:") << "#" << OffImm << markup(">"); 1278 } 1279 O << "]" << markup(">"); 1280} 1281 1282void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand( 1283 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, 1284 raw_ostream &O) { 1285 const MCOperand &MO1 = MI->getOperand(OpNum); 1286 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 1287 1288 O << markup("<mem:") << "["; 1289 printRegName(O, MO1.getReg()); 1290 if (MO2.getImm()) { 1291 O << ", " << markup("<imm:") << "#" << formatImm(MO2.getImm() * 4) 1292 << markup(">"); 1293 } 1294 O << "]" << markup(">"); 1295} 1296 1297void ARMInstPrinter::printT2AddrModeImm8OffsetOperand( 1298 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, 1299 raw_ostream &O) { 1300 const MCOperand &MO1 = MI->getOperand(OpNum); 1301 int32_t OffImm = (int32_t)MO1.getImm(); 1302 O << ", " << markup("<imm:"); 1303 if (OffImm == INT32_MIN) 1304 O << "#-0"; 1305 else if (OffImm < 0) 1306 O << "#-" << -OffImm; 1307 else 1308 O << "#" << OffImm; 1309 O << markup(">"); 1310} 1311 1312void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand( 1313 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, 1314 raw_ostream &O) { 1315 const MCOperand &MO1 = MI->getOperand(OpNum); 1316 int32_t OffImm = (int32_t)MO1.getImm(); 1317 1318 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); 1319 1320 O << ", " << markup("<imm:"); 1321 if (OffImm == INT32_MIN) 1322 O << "#-0"; 1323 else if (OffImm < 0) 1324 O << "#-" << -OffImm; 1325 else 1326 O << "#" << OffImm; 1327 O << markup(">"); 1328} 1329 1330void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI, 1331 unsigned OpNum, 1332 const MCSubtargetInfo &STI, 1333 raw_ostream &O) { 1334 const MCOperand &MO1 = MI->getOperand(OpNum); 1335 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 1336 const MCOperand &MO3 = MI->getOperand(OpNum + 2); 1337 1338 O << markup("<mem:") << "["; 1339 printRegName(O, MO1.getReg()); 1340 1341 assert(MO2.getReg() && "Invalid so_reg load / store address!"); 1342 O << ", "; 1343 printRegName(O, MO2.getReg()); 1344 1345 unsigned ShAmt = MO3.getImm(); 1346 if (ShAmt) { 1347 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!"); 1348 O << ", lsl " << markup("<imm:") << "#" << ShAmt << markup(">"); 1349 } 1350 O << "]" << markup(">"); 1351} 1352 1353void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum, 1354 const MCSubtargetInfo &STI, 1355 raw_ostream &O) { 1356 const MCOperand &MO = MI->getOperand(OpNum); 1357 O << markup("<imm:") << '#' << ARM_AM::getFPImmFloat(MO.getImm()) 1358 << markup(">"); 1359} 1360 1361void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum, 1362 const MCSubtargetInfo &STI, 1363 raw_ostream &O) { 1364 unsigned EncodedImm = MI->getOperand(OpNum).getImm(); 1365 unsigned EltBits; 1366 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits); 1367 O << markup("<imm:") << "#0x"; 1368 O.write_hex(Val); 1369 O << markup(">"); 1370} 1371 1372void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, 1373 const MCSubtargetInfo &STI, 1374 raw_ostream &O) { 1375 unsigned Imm = MI->getOperand(OpNum).getImm(); 1376 O << markup("<imm:") << "#" << formatImm(Imm + 1) << markup(">"); 1377} 1378 1379void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum, 1380 const MCSubtargetInfo &STI, 1381 raw_ostream &O) { 1382 unsigned Imm = MI->getOperand(OpNum).getImm(); 1383 if (Imm == 0) 1384 return; 1385 assert(Imm <= 3 && "illegal ror immediate!"); 1386 O << ", ror " << markup("<imm:") << "#" << 8 * Imm << markup(">"); 1387} 1388 1389void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum, 1390 const MCSubtargetInfo &STI, 1391 raw_ostream &O) { 1392 MCOperand Op = MI->getOperand(OpNum); 1393 1394 // Support for fixups (MCFixup) 1395 if (Op.isExpr()) 1396 return printOperand(MI, OpNum, STI, O); 1397 1398 unsigned Bits = Op.getImm() & 0xFF; 1399 unsigned Rot = (Op.getImm() & 0xF00) >> 7; 1400 1401 bool PrintUnsigned = false; 1402 switch (MI->getOpcode()) { 1403 case ARM::MOVi: 1404 // Movs to PC should be treated unsigned 1405 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC); 1406 break; 1407 case ARM::MSRi: 1408 // Movs to special registers should be treated unsigned 1409 PrintUnsigned = true; 1410 break; 1411 } 1412 1413 int32_t Rotated = ARM_AM::rotr32(Bits, Rot); 1414 if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) { 1415 // #rot has the least possible value 1416 O << "#" << markup("<imm:"); 1417 if (PrintUnsigned) 1418 O << static_cast<uint32_t>(Rotated); 1419 else 1420 O << Rotated; 1421 O << markup(">"); 1422 return; 1423 } 1424 1425 // Explicit #bits, #rot implied 1426 O << "#" << markup("<imm:") << Bits << markup(">") << ", #" << markup("<imm:") 1427 << Rot << markup(">"); 1428} 1429 1430void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum, 1431 const MCSubtargetInfo &STI, raw_ostream &O) { 1432 O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm() 1433 << markup(">"); 1434} 1435 1436void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum, 1437 const MCSubtargetInfo &STI, raw_ostream &O) { 1438 O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm() 1439 << markup(">"); 1440} 1441 1442void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum, 1443 const MCSubtargetInfo &STI, 1444 raw_ostream &O) { 1445 O << "[" << MI->getOperand(OpNum).getImm() << "]"; 1446} 1447 1448void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum, 1449 const MCSubtargetInfo &STI, 1450 raw_ostream &O) { 1451 O << "{"; 1452 printRegName(O, MI->getOperand(OpNum).getReg()); 1453 O << "}"; 1454} 1455 1456void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum, 1457 const MCSubtargetInfo &STI, 1458 raw_ostream &O) { 1459 unsigned Reg = MI->getOperand(OpNum).getReg(); 1460 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1461 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); 1462 O << "{"; 1463 printRegName(O, Reg0); 1464 O << ", "; 1465 printRegName(O, Reg1); 1466 O << "}"; 1467} 1468 1469void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, 1470 const MCSubtargetInfo &STI, 1471 raw_ostream &O) { 1472 unsigned Reg = MI->getOperand(OpNum).getReg(); 1473 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1474 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); 1475 O << "{"; 1476 printRegName(O, Reg0); 1477 O << ", "; 1478 printRegName(O, Reg1); 1479 O << "}"; 1480} 1481 1482void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum, 1483 const MCSubtargetInfo &STI, 1484 raw_ostream &O) { 1485 // Normally, it's not safe to use register enum values directly with 1486 // addition to get the next register, but for VFP registers, the 1487 // sort order is guaranteed because they're all of the form D<n>. 1488 O << "{"; 1489 printRegName(O, MI->getOperand(OpNum).getReg()); 1490 O << ", "; 1491 printRegName(O, MI->getOperand(OpNum).getReg() + 1); 1492 O << ", "; 1493 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1494 O << "}"; 1495} 1496 1497void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum, 1498 const MCSubtargetInfo &STI, 1499 raw_ostream &O) { 1500 // Normally, it's not safe to use register enum values directly with 1501 // addition to get the next register, but for VFP registers, the 1502 // sort order is guaranteed because they're all of the form D<n>. 1503 O << "{"; 1504 printRegName(O, MI->getOperand(OpNum).getReg()); 1505 O << ", "; 1506 printRegName(O, MI->getOperand(OpNum).getReg() + 1); 1507 O << ", "; 1508 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1509 O << ", "; 1510 printRegName(O, MI->getOperand(OpNum).getReg() + 3); 1511 O << "}"; 1512} 1513 1514void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI, 1515 unsigned OpNum, 1516 const MCSubtargetInfo &STI, 1517 raw_ostream &O) { 1518 O << "{"; 1519 printRegName(O, MI->getOperand(OpNum).getReg()); 1520 O << "[]}"; 1521} 1522 1523void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI, 1524 unsigned OpNum, 1525 const MCSubtargetInfo &STI, 1526 raw_ostream &O) { 1527 unsigned Reg = MI->getOperand(OpNum).getReg(); 1528 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1529 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); 1530 O << "{"; 1531 printRegName(O, Reg0); 1532 O << "[], "; 1533 printRegName(O, Reg1); 1534 O << "[]}"; 1535} 1536 1537void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI, 1538 unsigned OpNum, 1539 const MCSubtargetInfo &STI, 1540 raw_ostream &O) { 1541 // Normally, it's not safe to use register enum values directly with 1542 // addition to get the next register, but for VFP registers, the 1543 // sort order is guaranteed because they're all of the form D<n>. 1544 O << "{"; 1545 printRegName(O, MI->getOperand(OpNum).getReg()); 1546 O << "[], "; 1547 printRegName(O, MI->getOperand(OpNum).getReg() + 1); 1548 O << "[], "; 1549 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1550 O << "[]}"; 1551} 1552 1553void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI, 1554 unsigned OpNum, 1555 const MCSubtargetInfo &STI, 1556 raw_ostream &O) { 1557 // Normally, it's not safe to use register enum values directly with 1558 // addition to get the next register, but for VFP registers, the 1559 // sort order is guaranteed because they're all of the form D<n>. 1560 O << "{"; 1561 printRegName(O, MI->getOperand(OpNum).getReg()); 1562 O << "[], "; 1563 printRegName(O, MI->getOperand(OpNum).getReg() + 1); 1564 O << "[], "; 1565 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1566 O << "[], "; 1567 printRegName(O, MI->getOperand(OpNum).getReg() + 3); 1568 O << "[]}"; 1569} 1570 1571void ARMInstPrinter::printVectorListTwoSpacedAllLanes( 1572 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, 1573 raw_ostream &O) { 1574 unsigned Reg = MI->getOperand(OpNum).getReg(); 1575 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1576 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); 1577 O << "{"; 1578 printRegName(O, Reg0); 1579 O << "[], "; 1580 printRegName(O, Reg1); 1581 O << "[]}"; 1582} 1583 1584void ARMInstPrinter::printVectorListThreeSpacedAllLanes( 1585 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, 1586 raw_ostream &O) { 1587 // Normally, it's not safe to use register enum values directly with 1588 // addition to get the next register, but for VFP registers, the 1589 // sort order is guaranteed because they're all of the form D<n>. 1590 O << "{"; 1591 printRegName(O, MI->getOperand(OpNum).getReg()); 1592 O << "[], "; 1593 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1594 O << "[], "; 1595 printRegName(O, MI->getOperand(OpNum).getReg() + 4); 1596 O << "[]}"; 1597} 1598 1599void ARMInstPrinter::printVectorListFourSpacedAllLanes( 1600 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, 1601 raw_ostream &O) { 1602 // Normally, it's not safe to use register enum values directly with 1603 // addition to get the next register, but for VFP registers, the 1604 // sort order is guaranteed because they're all of the form D<n>. 1605 O << "{"; 1606 printRegName(O, MI->getOperand(OpNum).getReg()); 1607 O << "[], "; 1608 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1609 O << "[], "; 1610 printRegName(O, MI->getOperand(OpNum).getReg() + 4); 1611 O << "[], "; 1612 printRegName(O, MI->getOperand(OpNum).getReg() + 6); 1613 O << "[]}"; 1614} 1615 1616void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI, 1617 unsigned OpNum, 1618 const MCSubtargetInfo &STI, 1619 raw_ostream &O) { 1620 // Normally, it's not safe to use register enum values directly with 1621 // addition to get the next register, but for VFP registers, the 1622 // sort order is guaranteed because they're all of the form D<n>. 1623 O << "{"; 1624 printRegName(O, MI->getOperand(OpNum).getReg()); 1625 O << ", "; 1626 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1627 O << ", "; 1628 printRegName(O, MI->getOperand(OpNum).getReg() + 4); 1629 O << "}"; 1630} 1631 1632void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum, 1633 const MCSubtargetInfo &STI, 1634 raw_ostream &O) { 1635 // Normally, it's not safe to use register enum values directly with 1636 // addition to get the next register, but for VFP registers, the 1637 // sort order is guaranteed because they're all of the form D<n>. 1638 O << "{"; 1639 printRegName(O, MI->getOperand(OpNum).getReg()); 1640 O << ", "; 1641 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1642 O << ", "; 1643 printRegName(O, MI->getOperand(OpNum).getReg() + 4); 1644 O << ", "; 1645 printRegName(O, MI->getOperand(OpNum).getReg() + 6); 1646 O << "}"; 1647} 1648