1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "MCTargetDesc/ARMMCTargetDesc.h" 11#include "MCTargetDesc/ARMAddressingModes.h" 12#include "MCTargetDesc/ARMAsmBackend.h" 13#include "MCTargetDesc/ARMAsmBackendDarwin.h" 14#include "MCTargetDesc/ARMAsmBackendELF.h" 15#include "MCTargetDesc/ARMAsmBackendWinCOFF.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "MCTargetDesc/ARMFixupKinds.h" 18#include "llvm/ADT/StringSwitch.h" 19#include "llvm/MC/MCAsmBackend.h" 20#include "llvm/MC/MCAssembler.h" 21#include "llvm/MC/MCContext.h" 22#include "llvm/MC/MCDirectives.h" 23#include "llvm/MC/MCELFObjectWriter.h" 24#include "llvm/MC/MCExpr.h" 25#include "llvm/MC/MCFixupKindInfo.h" 26#include "llvm/MC/MCMachObjectWriter.h" 27#include "llvm/MC/MCObjectWriter.h" 28#include "llvm/MC/MCRegisterInfo.h" 29#include "llvm/MC/MCSectionELF.h" 30#include "llvm/MC/MCSectionMachO.h" 31#include "llvm/MC/MCSubtargetInfo.h" 32#include "llvm/MC/MCValue.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ELF.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/Format.h" 37#include "llvm/Support/MachO.h" 38#include "llvm/Support/TargetParser.h" 39#include "llvm/Support/raw_ostream.h" 40using namespace llvm; 41 42namespace { 43class ARMELFObjectWriter : public MCELFObjectTargetWriter { 44public: 45 ARMELFObjectWriter(uint8_t OSABI) 46 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 47 /*HasRelocationAddend*/ false) {} 48}; 49 50const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { 51 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { 52 // This table *must* be in the order that the fixup_* kinds are defined in 53 // ARMFixupKinds.h. 54 // 55 // Name Offset (bits) Size (bits) Flags 56 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 57 {"fixup_t2_ldst_pcrel_12", 0, 32, 58 MCFixupKindInfo::FKF_IsPCRel | 59 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 60 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 61 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 62 {"fixup_t2_pcrel_10", 0, 32, 63 MCFixupKindInfo::FKF_IsPCRel | 64 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 65 {"fixup_thumb_adr_pcrel_10", 0, 8, 66 MCFixupKindInfo::FKF_IsPCRel | 67 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 68 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 69 {"fixup_t2_adr_pcrel_12", 0, 32, 70 MCFixupKindInfo::FKF_IsPCRel | 71 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 72 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 73 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 74 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 75 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 76 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 77 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 78 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 79 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 80 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 81 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 82 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 83 {"fixup_arm_thumb_cp", 0, 8, 84 MCFixupKindInfo::FKF_IsPCRel | 85 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 86 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel}, 87 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 88 // - 19. 89 {"fixup_arm_movt_hi16", 0, 20, 0}, 90 {"fixup_arm_movw_lo16", 0, 20, 0}, 91 {"fixup_t2_movt_hi16", 0, 20, 0}, 92 {"fixup_t2_movw_lo16", 0, 20, 0}, 93 {"fixup_arm_mod_imm", 0, 12, 0}, 94 }; 95 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { 96 // This table *must* be in the order that the fixup_* kinds are defined in 97 // ARMFixupKinds.h. 98 // 99 // Name Offset (bits) Size (bits) Flags 100 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 101 {"fixup_t2_ldst_pcrel_12", 0, 32, 102 MCFixupKindInfo::FKF_IsPCRel | 103 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 104 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 105 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 106 {"fixup_t2_pcrel_10", 0, 32, 107 MCFixupKindInfo::FKF_IsPCRel | 108 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 109 {"fixup_thumb_adr_pcrel_10", 8, 8, 110 MCFixupKindInfo::FKF_IsPCRel | 111 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 112 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 113 {"fixup_t2_adr_pcrel_12", 0, 32, 114 MCFixupKindInfo::FKF_IsPCRel | 115 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 116 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 117 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 118 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 119 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 120 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 121 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 122 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 123 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 124 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 125 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 126 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 127 {"fixup_arm_thumb_cp", 8, 8, 128 MCFixupKindInfo::FKF_IsPCRel | 129 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 130 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel}, 131 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 132 // - 19. 133 {"fixup_arm_movt_hi16", 12, 20, 0}, 134 {"fixup_arm_movw_lo16", 12, 20, 0}, 135 {"fixup_t2_movt_hi16", 12, 20, 0}, 136 {"fixup_t2_movw_lo16", 12, 20, 0}, 137 {"fixup_arm_mod_imm", 20, 12, 0}, 138 }; 139 140 if (Kind < FirstTargetFixupKind) 141 return MCAsmBackend::getFixupKindInfo(Kind); 142 143 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 144 "Invalid kind!"); 145 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind]; 146} 147 148void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) { 149 switch (Flag) { 150 default: 151 break; 152 case MCAF_Code16: 153 setIsThumb(true); 154 break; 155 case MCAF_Code32: 156 setIsThumb(false); 157 break; 158 } 159} 160} // end anonymous namespace 161 162unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const { 163 bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2]; 164 165 switch (Op) { 166 default: 167 return Op; 168 case ARM::tBcc: 169 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; 170 case ARM::tLDRpci: 171 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; 172 case ARM::tADR: 173 return HasThumb2 ? (unsigned)ARM::t2ADR : Op; 174 case ARM::tB: 175 return HasThumb2 ? (unsigned)ARM::t2B : Op; 176 case ARM::tCBZ: 177 return ARM::tHINT; 178 case ARM::tCBNZ: 179 return ARM::tHINT; 180 } 181} 182 183bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 184 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 185 return true; 186 return false; 187} 188 189const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup, 190 uint64_t Value) const { 191 switch ((unsigned)Fixup.getKind()) { 192 case ARM::fixup_arm_thumb_br: { 193 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the 194 // low bit being an implied zero. There's an implied +4 offset for the 195 // branch, so we adjust the other way here to determine what's 196 // encodable. 197 // 198 // Relax if the value is too big for a (signed) i8. 199 int64_t Offset = int64_t(Value) - 4; 200 if (Offset > 2046 || Offset < -2048) 201 return "out of range pc-relative fixup value"; 202 break; 203 } 204 case ARM::fixup_arm_thumb_bcc: { 205 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 206 // low bit being an implied zero. There's an implied +4 offset for the 207 // branch, so we adjust the other way here to determine what's 208 // encodable. 209 // 210 // Relax if the value is too big for a (signed) i8. 211 int64_t Offset = int64_t(Value) - 4; 212 if (Offset > 254 || Offset < -256) 213 return "out of range pc-relative fixup value"; 214 break; 215 } 216 case ARM::fixup_thumb_adr_pcrel_10: 217 case ARM::fixup_arm_thumb_cp: { 218 // If the immediate is negative, greater than 1020, or not a multiple 219 // of four, the wide version of the instruction must be used. 220 int64_t Offset = int64_t(Value) - 4; 221 if (Offset & 3) 222 return "misaligned pc-relative fixup value"; 223 else if (Offset > 1020 || Offset < 0) 224 return "out of range pc-relative fixup value"; 225 break; 226 } 227 case ARM::fixup_arm_thumb_cb: { 228 // If we have a Thumb CBZ or CBNZ instruction and its target is the next 229 // instruction it is is actually out of range for the instruction. 230 // It will be changed to a NOP. 231 int64_t Offset = (Value & ~1); 232 if (Offset == 2) 233 return "will be converted to nop"; 234 break; 235 } 236 default: 237 llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!"); 238 } 239 return nullptr; 240} 241 242bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 243 const MCRelaxableFragment *DF, 244 const MCAsmLayout &Layout) const { 245 return reasonForFixupRelaxation(Fixup, Value); 246} 247 248void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 249 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 250 251 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 252 if (RelaxedOp == Inst.getOpcode()) { 253 SmallString<256> Tmp; 254 raw_svector_ostream OS(Tmp); 255 Inst.dump_pretty(OS); 256 OS << "\n"; 257 report_fatal_error("unexpected instruction to relax: " + OS.str()); 258 } 259 260 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we 261 // have to change the operands too. 262 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) && 263 RelaxedOp == ARM::tHINT) { 264 Res.setOpcode(RelaxedOp); 265 Res.addOperand(MCOperand::createImm(0)); 266 Res.addOperand(MCOperand::createImm(14)); 267 Res.addOperand(MCOperand::createReg(0)); 268 return; 269 } 270 271 // The rest of instructions we're relaxing have the same operands. 272 // We just need to update to the proper opcode. 273 Res = Inst; 274 Res.setOpcode(RelaxedOp); 275} 276 277bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 278 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 279 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 280 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0 281 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 282 if (isThumb()) { 283 const uint16_t nopEncoding = 284 hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding; 285 uint64_t NumNops = Count / 2; 286 for (uint64_t i = 0; i != NumNops; ++i) 287 OW->write16(nopEncoding); 288 if (Count & 1) 289 OW->write8(0); 290 return true; 291 } 292 // ARM mode 293 const uint32_t nopEncoding = 294 hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding; 295 uint64_t NumNops = Count / 4; 296 for (uint64_t i = 0; i != NumNops; ++i) 297 OW->write32(nopEncoding); 298 // FIXME: should this function return false when unable to write exactly 299 // 'Count' bytes with NOP encodings? 300 switch (Count % 4) { 301 default: 302 break; // No leftover bytes to write 303 case 1: 304 OW->write8(0); 305 break; 306 case 2: 307 OW->write16(0); 308 break; 309 case 3: 310 OW->write16(0); 311 OW->write8(0xa0); 312 break; 313 } 314 315 return true; 316} 317 318static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) { 319 if (IsLittleEndian) { 320 // Note that the halfwords are stored high first and low second in thumb; 321 // so we need to swap the fixup value here to map properly. 322 uint32_t Swapped = (Value & 0xFFFF0000) >> 16; 323 Swapped |= (Value & 0x0000FFFF) << 16; 324 return Swapped; 325 } else 326 return Value; 327} 328 329static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, 330 bool IsLittleEndian) { 331 uint32_t Value; 332 333 if (IsLittleEndian) { 334 Value = (SecondHalf & 0xFFFF) << 16; 335 Value |= (FirstHalf & 0xFFFF); 336 } else { 337 Value = (SecondHalf & 0xFFFF); 338 Value |= (FirstHalf & 0xFFFF) << 16; 339 } 340 341 return Value; 342} 343 344unsigned ARMAsmBackend::adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 345 bool IsPCRel, MCContext *Ctx, 346 bool IsLittleEndian, 347 bool IsResolved) const { 348 unsigned Kind = Fixup.getKind(); 349 switch (Kind) { 350 default: 351 llvm_unreachable("Unknown fixup kind!"); 352 case FK_Data_1: 353 case FK_Data_2: 354 case FK_Data_4: 355 return Value; 356 case FK_SecRel_2: 357 return Value; 358 case FK_SecRel_4: 359 return Value; 360 case ARM::fixup_arm_movt_hi16: 361 if (!IsPCRel) 362 Value >>= 16; 363 // Fallthrough 364 case ARM::fixup_arm_movw_lo16: { 365 unsigned Hi4 = (Value & 0xF000) >> 12; 366 unsigned Lo12 = Value & 0x0FFF; 367 // inst{19-16} = Hi4; 368 // inst{11-0} = Lo12; 369 Value = (Hi4 << 16) | (Lo12); 370 return Value; 371 } 372 case ARM::fixup_t2_movt_hi16: 373 if (!IsPCRel) 374 Value >>= 16; 375 // Fallthrough 376 case ARM::fixup_t2_movw_lo16: { 377 unsigned Hi4 = (Value & 0xF000) >> 12; 378 unsigned i = (Value & 0x800) >> 11; 379 unsigned Mid3 = (Value & 0x700) >> 8; 380 unsigned Lo8 = Value & 0x0FF; 381 // inst{19-16} = Hi4; 382 // inst{26} = i; 383 // inst{14-12} = Mid3; 384 // inst{7-0} = Lo8; 385 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 386 return swapHalfWords(Value, IsLittleEndian); 387 } 388 case ARM::fixup_arm_ldst_pcrel_12: 389 // ARM PC-relative values are offset by 8. 390 Value -= 4; 391 // FALLTHROUGH 392 case ARM::fixup_t2_ldst_pcrel_12: { 393 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 394 Value -= 4; 395 bool isAdd = true; 396 if ((int64_t)Value < 0) { 397 Value = -Value; 398 isAdd = false; 399 } 400 if (Ctx && Value >= 4096) { 401 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 402 return 0; 403 } 404 Value |= isAdd << 23; 405 406 // Same addressing mode as fixup_arm_pcrel_10, 407 // but with 16-bit halfwords swapped. 408 if (Kind == ARM::fixup_t2_ldst_pcrel_12) 409 return swapHalfWords(Value, IsLittleEndian); 410 411 return Value; 412 } 413 case ARM::fixup_arm_adr_pcrel_12: { 414 // ARM PC-relative values are offset by 8. 415 Value -= 8; 416 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 417 if ((int64_t)Value < 0) { 418 Value = -Value; 419 opc = 2; // 0b0010 420 } 421 if (Ctx && ARM_AM::getSOImmVal(Value) == -1) { 422 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 423 return 0; 424 } 425 // Encode the immediate and shift the opcode into place. 426 return ARM_AM::getSOImmVal(Value) | (opc << 21); 427 } 428 429 case ARM::fixup_t2_adr_pcrel_12: { 430 Value -= 4; 431 unsigned opc = 0; 432 if ((int64_t)Value < 0) { 433 Value = -Value; 434 opc = 5; 435 } 436 437 uint32_t out = (opc << 21); 438 out |= (Value & 0x800) << 15; 439 out |= (Value & 0x700) << 4; 440 out |= (Value & 0x0FF); 441 442 return swapHalfWords(out, IsLittleEndian); 443 } 444 445 case ARM::fixup_arm_condbranch: 446 case ARM::fixup_arm_uncondbranch: 447 case ARM::fixup_arm_uncondbl: 448 case ARM::fixup_arm_condbl: 449 case ARM::fixup_arm_blx: 450 // These values don't encode the low two bits since they're always zero. 451 // Offset by 8 just as above. 452 if (const MCSymbolRefExpr *SRE = 453 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 454 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL) 455 return 0; 456 return 0xffffff & ((Value - 8) >> 2); 457 case ARM::fixup_t2_uncondbranch: { 458 Value = Value - 4; 459 Value >>= 1; // Low bit is not encoded. 460 461 uint32_t out = 0; 462 bool I = Value & 0x800000; 463 bool J1 = Value & 0x400000; 464 bool J2 = Value & 0x200000; 465 J1 ^= I; 466 J2 ^= I; 467 468 out |= I << 26; // S bit 469 out |= !J1 << 13; // J1 bit 470 out |= !J2 << 11; // J2 bit 471 out |= (Value & 0x1FF800) << 5; // imm6 field 472 out |= (Value & 0x0007FF); // imm11 field 473 474 return swapHalfWords(out, IsLittleEndian); 475 } 476 case ARM::fixup_t2_condbranch: { 477 Value = Value - 4; 478 Value >>= 1; // Low bit is not encoded. 479 480 uint64_t out = 0; 481 out |= (Value & 0x80000) << 7; // S bit 482 out |= (Value & 0x40000) >> 7; // J2 bit 483 out |= (Value & 0x20000) >> 4; // J1 bit 484 out |= (Value & 0x1F800) << 5; // imm6 field 485 out |= (Value & 0x007FF); // imm11 field 486 487 return swapHalfWords(out, IsLittleEndian); 488 } 489 case ARM::fixup_arm_thumb_bl: { 490 // The value doesn't encode the low bit (always zero) and is offset by 491 // four. The 32-bit immediate value is encoded as 492 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0) 493 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 494 // The value is encoded into disjoint bit positions in the destination 495 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 496 // J = either J1 or J2 bit 497 // 498 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII 499 // 500 // Note that the halfwords are stored high first, low second; so we need 501 // to transpose the fixup value here to map properly. 502 uint32_t offset = (Value - 4) >> 1; 503 uint32_t signBit = (offset & 0x800000) >> 23; 504 uint32_t I1Bit = (offset & 0x400000) >> 22; 505 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 506 uint32_t I2Bit = (offset & 0x200000) >> 21; 507 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 508 uint32_t imm10Bits = (offset & 0x1FF800) >> 11; 509 uint32_t imm11Bits = (offset & 0x000007FF); 510 511 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits); 512 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 513 (uint16_t)imm11Bits); 514 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 515 } 516 case ARM::fixup_arm_thumb_blx: { 517 // The value doesn't encode the low two bits (always zero) and is offset by 518 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as 519 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00) 520 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 521 // The value is encoded into disjoint bit positions in the destination 522 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 523 // J = either J1 or J2 bit, 0 = zero. 524 // 525 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0 526 // 527 // Note that the halfwords are stored high first, low second; so we need 528 // to transpose the fixup value here to map properly. 529 uint32_t offset = (Value - 2) >> 2; 530 if (const MCSymbolRefExpr *SRE = 531 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 532 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL) 533 offset = 0; 534 uint32_t signBit = (offset & 0x400000) >> 22; 535 uint32_t I1Bit = (offset & 0x200000) >> 21; 536 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 537 uint32_t I2Bit = (offset & 0x100000) >> 20; 538 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 539 uint32_t imm10HBits = (offset & 0xFFC00) >> 10; 540 uint32_t imm10LBits = (offset & 0x3FF); 541 542 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits); 543 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 544 ((uint16_t)imm10LBits) << 1); 545 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 546 } 547 case ARM::fixup_thumb_adr_pcrel_10: 548 case ARM::fixup_arm_thumb_cp: 549 // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we 550 // could have an error on our hands. 551 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2] && IsResolved) { 552 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 553 if (FixupDiagnostic) { 554 Ctx->reportError(Fixup.getLoc(), FixupDiagnostic); 555 return 0; 556 } 557 } 558 // Offset by 4, and don't encode the low two bits. 559 return ((Value - 4) >> 2) & 0xff; 560 case ARM::fixup_arm_thumb_cb: { 561 // Offset by 4 and don't encode the lower bit, which is always 0. 562 // FIXME: diagnose if no Thumb2 563 uint32_t Binary = (Value - 4) >> 1; 564 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 565 } 566 case ARM::fixup_arm_thumb_br: 567 // Offset by 4 and don't encode the lower bit, which is always 0. 568 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2]) { 569 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 570 if (FixupDiagnostic) { 571 Ctx->reportError(Fixup.getLoc(), FixupDiagnostic); 572 return 0; 573 } 574 } 575 return ((Value - 4) >> 1) & 0x7ff; 576 case ARM::fixup_arm_thumb_bcc: 577 // Offset by 4 and don't encode the lower bit, which is always 0. 578 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2]) { 579 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 580 if (FixupDiagnostic) { 581 Ctx->reportError(Fixup.getLoc(), FixupDiagnostic); 582 return 0; 583 } 584 } 585 return ((Value - 4) >> 1) & 0xff; 586 case ARM::fixup_arm_pcrel_10_unscaled: { 587 Value = Value - 8; // ARM fixups offset by an additional word and don't 588 // need to adjust for the half-word ordering. 589 bool isAdd = true; 590 if ((int64_t)Value < 0) { 591 Value = -Value; 592 isAdd = false; 593 } 594 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8]. 595 if (Ctx && Value >= 256) { 596 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 597 return 0; 598 } 599 Value = (Value & 0xf) | ((Value & 0xf0) << 4); 600 return Value | (isAdd << 23); 601 } 602 case ARM::fixup_arm_pcrel_10: 603 Value = Value - 4; // ARM fixups offset by an additional word and don't 604 // need to adjust for the half-word ordering. 605 // Fall through. 606 case ARM::fixup_t2_pcrel_10: { 607 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 608 Value = Value - 4; 609 bool isAdd = true; 610 if ((int64_t)Value < 0) { 611 Value = -Value; 612 isAdd = false; 613 } 614 // These values don't encode the low two bits since they're always zero. 615 Value >>= 2; 616 if (Ctx && Value >= 256) { 617 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 618 return 0; 619 } 620 Value |= isAdd << 23; 621 622 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 623 // swapped. 624 if (Kind == ARM::fixup_t2_pcrel_10) 625 return swapHalfWords(Value, IsLittleEndian); 626 627 return Value; 628 } 629 case ARM::fixup_arm_mod_imm: 630 Value = ARM_AM::getSOImmVal(Value); 631 if (Ctx && Value >> 12) { 632 Ctx->reportError(Fixup.getLoc(), "out of range immediate fixup value"); 633 return 0; 634 } 635 return Value; 636 } 637} 638 639void ARMAsmBackend::processFixupValue(const MCAssembler &Asm, 640 const MCAsmLayout &Layout, 641 const MCFixup &Fixup, 642 const MCFragment *DF, 643 const MCValue &Target, uint64_t &Value, 644 bool &IsResolved) { 645 const MCSymbolRefExpr *A = Target.getSymA(); 646 const MCSymbol *Sym = A ? &A->getSymbol() : nullptr; 647 // Some fixups to thumb function symbols need the low bit (thumb bit) 648 // twiddled. 649 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 && 650 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 && 651 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 && 652 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 && 653 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 && 654 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) { 655 if (Sym) { 656 if (Asm.isThumbFunc(Sym)) 657 Value |= 1; 658 } 659 } 660 if (IsResolved && (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) { 661 assert(Sym && "How did we resolve this?"); 662 663 // If the symbol is external the linker will handle it. 664 // FIXME: Should we handle it as an optimization? 665 666 // If the symbol is out of range, produce a relocation and hope the 667 // linker can handle it. GNU AS produces an error in this case. 668 if (Sym->isExternal() || Value >= 0x400004) 669 IsResolved = false; 670 } 671 // We must always generate a relocation for BL/BLX instructions if we have 672 // a symbol to reference, as the linker relies on knowing the destination 673 // symbol's thumb-ness to get interworking right. 674 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx || 675 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx || 676 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl || 677 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl)) 678 IsResolved = false; 679 680 // Try to get the encoded value for the fixup as-if we're mapping it into 681 // the instruction. This allows adjustFixupValue() to issue a diagnostic 682 // if the value aren't invalid. 683 (void)adjustFixupValue(Fixup, Value, false, &Asm.getContext(), 684 IsLittleEndian, IsResolved); 685} 686 687/// getFixupKindNumBytes - The number of bytes the fixup may change. 688static unsigned getFixupKindNumBytes(unsigned Kind) { 689 switch (Kind) { 690 default: 691 llvm_unreachable("Unknown fixup kind!"); 692 693 case FK_Data_1: 694 case ARM::fixup_arm_thumb_bcc: 695 case ARM::fixup_arm_thumb_cp: 696 case ARM::fixup_thumb_adr_pcrel_10: 697 return 1; 698 699 case FK_Data_2: 700 case ARM::fixup_arm_thumb_br: 701 case ARM::fixup_arm_thumb_cb: 702 case ARM::fixup_arm_mod_imm: 703 return 2; 704 705 case ARM::fixup_arm_pcrel_10_unscaled: 706 case ARM::fixup_arm_ldst_pcrel_12: 707 case ARM::fixup_arm_pcrel_10: 708 case ARM::fixup_arm_adr_pcrel_12: 709 case ARM::fixup_arm_uncondbl: 710 case ARM::fixup_arm_condbl: 711 case ARM::fixup_arm_blx: 712 case ARM::fixup_arm_condbranch: 713 case ARM::fixup_arm_uncondbranch: 714 return 3; 715 716 case FK_Data_4: 717 case ARM::fixup_t2_ldst_pcrel_12: 718 case ARM::fixup_t2_condbranch: 719 case ARM::fixup_t2_uncondbranch: 720 case ARM::fixup_t2_pcrel_10: 721 case ARM::fixup_t2_adr_pcrel_12: 722 case ARM::fixup_arm_thumb_bl: 723 case ARM::fixup_arm_thumb_blx: 724 case ARM::fixup_arm_movt_hi16: 725 case ARM::fixup_arm_movw_lo16: 726 case ARM::fixup_t2_movt_hi16: 727 case ARM::fixup_t2_movw_lo16: 728 return 4; 729 730 case FK_SecRel_2: 731 return 2; 732 case FK_SecRel_4: 733 return 4; 734 } 735} 736 737/// getFixupKindContainerSizeBytes - The number of bytes of the 738/// container involved in big endian. 739static unsigned getFixupKindContainerSizeBytes(unsigned Kind) { 740 switch (Kind) { 741 default: 742 llvm_unreachable("Unknown fixup kind!"); 743 744 case FK_Data_1: 745 return 1; 746 case FK_Data_2: 747 return 2; 748 case FK_Data_4: 749 return 4; 750 751 case ARM::fixup_arm_thumb_bcc: 752 case ARM::fixup_arm_thumb_cp: 753 case ARM::fixup_thumb_adr_pcrel_10: 754 case ARM::fixup_arm_thumb_br: 755 case ARM::fixup_arm_thumb_cb: 756 // Instruction size is 2 bytes. 757 return 2; 758 759 case ARM::fixup_arm_pcrel_10_unscaled: 760 case ARM::fixup_arm_ldst_pcrel_12: 761 case ARM::fixup_arm_pcrel_10: 762 case ARM::fixup_arm_adr_pcrel_12: 763 case ARM::fixup_arm_uncondbl: 764 case ARM::fixup_arm_condbl: 765 case ARM::fixup_arm_blx: 766 case ARM::fixup_arm_condbranch: 767 case ARM::fixup_arm_uncondbranch: 768 case ARM::fixup_t2_ldst_pcrel_12: 769 case ARM::fixup_t2_condbranch: 770 case ARM::fixup_t2_uncondbranch: 771 case ARM::fixup_t2_pcrel_10: 772 case ARM::fixup_t2_adr_pcrel_12: 773 case ARM::fixup_arm_thumb_bl: 774 case ARM::fixup_arm_thumb_blx: 775 case ARM::fixup_arm_movt_hi16: 776 case ARM::fixup_arm_movw_lo16: 777 case ARM::fixup_t2_movt_hi16: 778 case ARM::fixup_t2_movw_lo16: 779 case ARM::fixup_arm_mod_imm: 780 // Instruction size is 4 bytes. 781 return 4; 782 } 783} 784 785void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 786 unsigned DataSize, uint64_t Value, 787 bool IsPCRel) const { 788 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 789 Value = 790 adjustFixupValue(Fixup, Value, IsPCRel, nullptr, IsLittleEndian, true); 791 if (!Value) 792 return; // Doesn't change encoding. 793 794 unsigned Offset = Fixup.getOffset(); 795 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 796 797 // Used to point to big endian bytes. 798 unsigned FullSizeBytes; 799 if (!IsLittleEndian) { 800 FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind()); 801 assert((Offset + FullSizeBytes) <= DataSize && "Invalid fixup size!"); 802 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!"); 803 } 804 805 // For each byte of the fragment that the fixup touches, mask in the bits from 806 // the fixup value. The Value has been "split up" into the appropriate 807 // bitfields above. 808 for (unsigned i = 0; i != NumBytes; ++i) { 809 unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i); 810 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 811 } 812} 813 814namespace CU { 815 816/// \brief Compact unwind encoding values. 817enum CompactUnwindEncodings { 818 UNWIND_ARM_MODE_MASK = 0x0F000000, 819 UNWIND_ARM_MODE_FRAME = 0x01000000, 820 UNWIND_ARM_MODE_FRAME_D = 0x02000000, 821 UNWIND_ARM_MODE_DWARF = 0x04000000, 822 823 UNWIND_ARM_FRAME_STACK_ADJUST_MASK = 0x00C00000, 824 825 UNWIND_ARM_FRAME_FIRST_PUSH_R4 = 0x00000001, 826 UNWIND_ARM_FRAME_FIRST_PUSH_R5 = 0x00000002, 827 UNWIND_ARM_FRAME_FIRST_PUSH_R6 = 0x00000004, 828 829 UNWIND_ARM_FRAME_SECOND_PUSH_R8 = 0x00000008, 830 UNWIND_ARM_FRAME_SECOND_PUSH_R9 = 0x00000010, 831 UNWIND_ARM_FRAME_SECOND_PUSH_R10 = 0x00000020, 832 UNWIND_ARM_FRAME_SECOND_PUSH_R11 = 0x00000040, 833 UNWIND_ARM_FRAME_SECOND_PUSH_R12 = 0x00000080, 834 835 UNWIND_ARM_FRAME_D_REG_COUNT_MASK = 0x00000F00, 836 837 UNWIND_ARM_DWARF_SECTION_OFFSET = 0x00FFFFFF 838}; 839 840} // end CU namespace 841 842/// Generate compact unwind encoding for the function based on the CFI 843/// instructions. If the CFI instructions describe a frame that cannot be 844/// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which 845/// tells the runtime to fallback and unwind using dwarf. 846uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding( 847 ArrayRef<MCCFIInstruction> Instrs) const { 848 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n"); 849 // Only armv7k uses CFI based unwinding. 850 if (Subtype != MachO::CPU_SUBTYPE_ARM_V7K) 851 return 0; 852 // No .cfi directives means no frame. 853 if (Instrs.empty()) 854 return 0; 855 // Start off assuming CFA is at SP+0. 856 int CFARegister = ARM::SP; 857 int CFARegisterOffset = 0; 858 // Mark savable registers as initially unsaved 859 DenseMap<unsigned, int> RegOffsets; 860 int FloatRegCount = 0; 861 // Process each .cfi directive and build up compact unwind info. 862 for (size_t i = 0, e = Instrs.size(); i != e; ++i) { 863 int Reg; 864 const MCCFIInstruction &Inst = Instrs[i]; 865 switch (Inst.getOperation()) { 866 case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa 867 CFARegisterOffset = -Inst.getOffset(); 868 CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true); 869 break; 870 case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset 871 CFARegisterOffset = -Inst.getOffset(); 872 break; 873 case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register 874 CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true); 875 break; 876 case MCCFIInstruction::OpOffset: // DW_CFA_offset 877 Reg = MRI.getLLVMRegNum(Inst.getRegister(), true); 878 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 879 RegOffsets[Reg] = Inst.getOffset(); 880 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 881 RegOffsets[Reg] = Inst.getOffset(); 882 ++FloatRegCount; 883 } else { 884 DEBUG_WITH_TYPE("compact-unwind", 885 llvm::dbgs() << ".cfi_offset on unknown register=" 886 << Inst.getRegister() << "\n"); 887 return CU::UNWIND_ARM_MODE_DWARF; 888 } 889 break; 890 case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc 891 // Ignore 892 break; 893 default: 894 // Directive not convertable to compact unwind, bail out. 895 DEBUG_WITH_TYPE("compact-unwind", 896 llvm::dbgs() 897 << "CFI directive not compatiable with comact " 898 "unwind encoding, opcode=" << Inst.getOperation() 899 << "\n"); 900 return CU::UNWIND_ARM_MODE_DWARF; 901 break; 902 } 903 } 904 905 // If no frame set up, return no unwind info. 906 if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0)) 907 return 0; 908 909 // Verify standard frame (lr/r7) was used. 910 if (CFARegister != ARM::R7) { 911 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is " 912 << CFARegister 913 << " instead of r7\n"); 914 return CU::UNWIND_ARM_MODE_DWARF; 915 } 916 int StackAdjust = CFARegisterOffset - 8; 917 if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) { 918 DEBUG_WITH_TYPE("compact-unwind", 919 llvm::dbgs() 920 << "LR not saved as standard frame, StackAdjust=" 921 << StackAdjust 922 << ", CFARegisterOffset=" << CFARegisterOffset 923 << ", lr save at offset=" << RegOffsets[14] << "\n"); 924 return CU::UNWIND_ARM_MODE_DWARF; 925 } 926 if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) { 927 DEBUG_WITH_TYPE("compact-unwind", 928 llvm::dbgs() << "r7 not saved as standard frame\n"); 929 return CU::UNWIND_ARM_MODE_DWARF; 930 } 931 uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME; 932 933 // If var-args are used, there may be a stack adjust required. 934 switch (StackAdjust) { 935 case 0: 936 break; 937 case 4: 938 CompactUnwindEncoding |= 0x00400000; 939 break; 940 case 8: 941 CompactUnwindEncoding |= 0x00800000; 942 break; 943 case 12: 944 CompactUnwindEncoding |= 0x00C00000; 945 break; 946 default: 947 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() 948 << ".cfi_def_cfa stack adjust (" 949 << StackAdjust << ") out of range\n"); 950 return CU::UNWIND_ARM_MODE_DWARF; 951 } 952 953 // If r6 is saved, it must be right below r7. 954 static struct { 955 unsigned Reg; 956 unsigned Encoding; 957 } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6}, 958 {ARM::R5, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R5}, 959 {ARM::R4, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R4}, 960 {ARM::R12, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R12}, 961 {ARM::R11, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R11}, 962 {ARM::R10, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R10}, 963 {ARM::R9, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R9}, 964 {ARM::R8, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R8}}; 965 966 int CurOffset = -8 - StackAdjust; 967 for (auto CSReg : GPRCSRegs) { 968 auto Offset = RegOffsets.find(CSReg.Reg); 969 if (Offset == RegOffsets.end()) 970 continue; 971 972 int RegOffset = Offset->second; 973 if (RegOffset != CurOffset - 4) { 974 DEBUG_WITH_TYPE("compact-unwind", 975 llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at " 976 << RegOffset << " but only supported at " 977 << CurOffset << "\n"); 978 return CU::UNWIND_ARM_MODE_DWARF; 979 } 980 CompactUnwindEncoding |= CSReg.Encoding; 981 CurOffset -= 4; 982 } 983 984 // If no floats saved, we are done. 985 if (FloatRegCount == 0) 986 return CompactUnwindEncoding; 987 988 // Switch mode to include D register saving. 989 CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK; 990 CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D; 991 992 // FIXME: supporting more than 4 saved D-registers compactly would be trivial, 993 // but needs coordination with the linker and libunwind. 994 if (FloatRegCount > 4) { 995 DEBUG_WITH_TYPE("compact-unwind", 996 llvm::dbgs() << "unsupported number of D registers saved (" 997 << FloatRegCount << ")\n"); 998 return CU::UNWIND_ARM_MODE_DWARF; 999 } 1000 1001 // Floating point registers must either be saved sequentially, or we defer to 1002 // DWARF. No gaps allowed here so check that each saved d-register is 1003 // precisely where it should be. 1004 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 }; 1005 for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) { 1006 auto Offset = RegOffsets.find(FPRCSRegs[Idx]); 1007 if (Offset == RegOffsets.end()) { 1008 DEBUG_WITH_TYPE("compact-unwind", 1009 llvm::dbgs() << FloatRegCount << " D-regs saved, but " 1010 << MRI.getName(FPRCSRegs[Idx]) 1011 << " not saved\n"); 1012 return CU::UNWIND_ARM_MODE_DWARF; 1013 } else if (Offset->second != CurOffset - 8) { 1014 DEBUG_WITH_TYPE("compact-unwind", 1015 llvm::dbgs() << FloatRegCount << " D-regs saved, but " 1016 << MRI.getName(FPRCSRegs[Idx]) 1017 << " saved at " << Offset->second 1018 << ", expected at " << CurOffset - 8 1019 << "\n"); 1020 return CU::UNWIND_ARM_MODE_DWARF; 1021 } 1022 CurOffset -= 8; 1023 } 1024 1025 return CompactUnwindEncoding | ((FloatRegCount - 1) << 8); 1026} 1027 1028static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) { 1029 unsigned AK = ARM::parseArch(Arch); 1030 switch (AK) { 1031 default: 1032 return MachO::CPU_SUBTYPE_ARM_V7; 1033 case ARM::AK_ARMV4T: 1034 return MachO::CPU_SUBTYPE_ARM_V4T; 1035 case ARM::AK_ARMV5T: 1036 case ARM::AK_ARMV5TE: 1037 case ARM::AK_ARMV5TEJ: 1038 return MachO::CPU_SUBTYPE_ARM_V5; 1039 case ARM::AK_ARMV6: 1040 case ARM::AK_ARMV6K: 1041 return MachO::CPU_SUBTYPE_ARM_V6; 1042 case ARM::AK_ARMV7A: 1043 return MachO::CPU_SUBTYPE_ARM_V7; 1044 case ARM::AK_ARMV7S: 1045 return MachO::CPU_SUBTYPE_ARM_V7S; 1046 case ARM::AK_ARMV7K: 1047 return MachO::CPU_SUBTYPE_ARM_V7K; 1048 case ARM::AK_ARMV6M: 1049 return MachO::CPU_SUBTYPE_ARM_V6M; 1050 case ARM::AK_ARMV7M: 1051 return MachO::CPU_SUBTYPE_ARM_V7M; 1052 case ARM::AK_ARMV7EM: 1053 return MachO::CPU_SUBTYPE_ARM_V7EM; 1054 } 1055} 1056 1057MCAsmBackend *llvm::createARMAsmBackend(const Target &T, 1058 const MCRegisterInfo &MRI, 1059 const Triple &TheTriple, StringRef CPU, 1060 bool isLittle) { 1061 switch (TheTriple.getObjectFormat()) { 1062 default: 1063 llvm_unreachable("unsupported object format"); 1064 case Triple::MachO: { 1065 MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName()); 1066 return new ARMAsmBackendDarwin(T, TheTriple, MRI, CS); 1067 } 1068 case Triple::COFF: 1069 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); 1070 return new ARMAsmBackendWinCOFF(T, TheTriple); 1071 case Triple::ELF: 1072 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target"); 1073 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 1074 return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle); 1075 } 1076} 1077 1078MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, 1079 const MCRegisterInfo &MRI, 1080 const Triple &TT, StringRef CPU) { 1081 return createARMAsmBackend(T, MRI, TT, CPU, true); 1082} 1083 1084MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, 1085 const MCRegisterInfo &MRI, 1086 const Triple &TT, StringRef CPU) { 1087 return createARMAsmBackend(T, MRI, TT, CPU, false); 1088} 1089 1090MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T, 1091 const MCRegisterInfo &MRI, 1092 const Triple &TT, StringRef CPU) { 1093 return createARMAsmBackend(T, MRI, TT, CPU, true); 1094} 1095 1096MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T, 1097 const MCRegisterInfo &MRI, 1098 const Triple &TT, StringRef CPU) { 1099 return createARMAsmBackend(T, MRI, TT, CPU, false); 1100} 1101