1//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMBaseRegisterInfo.h" 15#include "ARM.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMFrameLowering.h" 18#include "ARMMachineFunctionInfo.h" 19#include "ARMSubtarget.h" 20#include "MCTargetDesc/ARMAddressingModes.h" 21#include "llvm/ADT/BitVector.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/RegisterScavenging.h" 29#include "llvm/CodeGen/VirtRegMap.h" 30#include "llvm/IR/Constants.h" 31#include "llvm/IR/DerivedTypes.h" 32#include "llvm/IR/Function.h" 33#include "llvm/IR/LLVMContext.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/Target/TargetFrameLowering.h" 38#include "llvm/Target/TargetMachine.h" 39#include "llvm/Target/TargetOptions.h" 40 41#define DEBUG_TYPE "arm-register-info" 42 43#define GET_REGINFO_TARGET_DESC 44#include "ARMGenRegisterInfo.inc" 45 46using namespace llvm; 47 48ARMBaseRegisterInfo::ARMBaseRegisterInfo() 49 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), BasePtr(ARM::R6) {} 50 51static unsigned getFramePointerReg(const ARMSubtarget &STI) { 52 if (STI.isTargetMachO()) { 53 if (STI.isTargetDarwin() || STI.isThumb1Only()) 54 return ARM::R7; 55 else 56 return ARM::R11; 57 } else if (STI.isTargetWindows()) 58 return ARM::R11; 59 else // ARM EABI 60 return STI.isThumb() ? ARM::R7 : ARM::R11; 61} 62 63const MCPhysReg* 64ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 65 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>(); 66 const MCPhysReg *RegList = 67 STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; 68 69 const Function *F = MF->getFunction(); 70 if (F->getCallingConv() == CallingConv::GHC) { 71 // GHC set of callee saved regs is empty as all those regs are 72 // used for passing STG regs around 73 return CSR_NoRegs_SaveList; 74 } else if (F->hasFnAttribute("interrupt")) { 75 if (STI.isMClass()) { 76 // M-class CPUs have hardware which saves the registers needed to allow a 77 // function conforming to the AAPCS to function as a handler. 78 return CSR_AAPCS_SaveList; 79 } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") { 80 // Fast interrupt mode gives the handler a private copy of R8-R14, so less 81 // need to be saved to restore user-mode state. 82 return CSR_FIQ_SaveList; 83 } else { 84 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by 85 // exception handling. 86 return CSR_GenericInt_SaveList; 87 } 88 } 89 90 if (STI.isTargetDarwin() && F->getCallingConv() == CallingConv::CXX_FAST_TLS) 91 return MF->getInfo<ARMFunctionInfo>()->isSplitCSR() 92 ? CSR_iOS_CXX_TLS_PE_SaveList 93 : CSR_iOS_CXX_TLS_SaveList; 94 return RegList; 95} 96 97const MCPhysReg *ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy( 98 const MachineFunction *MF) const { 99 assert(MF && "Invalid MachineFunction pointer."); 100 if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS && 101 MF->getInfo<ARMFunctionInfo>()->isSplitCSR()) 102 return CSR_iOS_CXX_TLS_ViaCopy_SaveList; 103 return nullptr; 104} 105 106const uint32_t * 107ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF, 108 CallingConv::ID CC) const { 109 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 110 if (CC == CallingConv::GHC) 111 // This is academic becase all GHC calls are (supposed to be) tail calls 112 return CSR_NoRegs_RegMask; 113 if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS) 114 return CSR_iOS_CXX_TLS_RegMask; 115 return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 116} 117 118const uint32_t* 119ARMBaseRegisterInfo::getNoPreservedMask() const { 120 return CSR_NoRegs_RegMask; 121} 122 123const uint32_t * 124ARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction &MF) const { 125 assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() && 126 "only know about special TLS call on Darwin"); 127 return CSR_iOS_TLSCall_RegMask; 128} 129 130 131const uint32_t * 132ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF, 133 CallingConv::ID CC) const { 134 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 135 // This should return a register mask that is the same as that returned by 136 // getCallPreservedMask but that additionally preserves the register used for 137 // the first i32 argument (which must also be the register used to return a 138 // single i32 return value) 139 // 140 // In case that the calling convention does not use the same register for 141 // both or otherwise does not want to enable this optimization, the function 142 // should return NULL 143 if (CC == CallingConv::GHC) 144 // This is academic becase all GHC calls are (supposed to be) tail calls 145 return nullptr; 146 return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask 147 : CSR_AAPCS_ThisReturn_RegMask; 148} 149 150BitVector ARMBaseRegisterInfo:: 151getReservedRegs(const MachineFunction &MF) const { 152 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 153 const ARMFrameLowering *TFI = getFrameLowering(MF); 154 155 // FIXME: avoid re-calculating this every time. 156 BitVector Reserved(getNumRegs()); 157 Reserved.set(ARM::SP); 158 Reserved.set(ARM::PC); 159 Reserved.set(ARM::FPSCR); 160 Reserved.set(ARM::APSR_NZCV); 161 if (TFI->hasFP(MF)) 162 Reserved.set(getFramePointerReg(STI)); 163 if (hasBasePointer(MF)) 164 Reserved.set(BasePtr); 165 // Some targets reserve R9. 166 if (STI.isR9Reserved()) 167 Reserved.set(ARM::R9); 168 // Reserve D16-D31 if the subtarget doesn't support them. 169 if (!STI.hasVFP3() || STI.hasD16()) { 170 assert(ARM::D31 == ARM::D16 + 15); 171 for (unsigned i = 0; i != 16; ++i) 172 Reserved.set(ARM::D16 + i); 173 } 174 const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 175 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 176 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 177 if (Reserved.test(*SI)) Reserved.set(*I); 178 179 return Reserved; 180} 181 182const TargetRegisterClass * 183ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, 184 const MachineFunction &) const { 185 const TargetRegisterClass *Super = RC; 186 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 187 do { 188 switch (Super->getID()) { 189 case ARM::GPRRegClassID: 190 case ARM::SPRRegClassID: 191 case ARM::DPRRegClassID: 192 case ARM::QPRRegClassID: 193 case ARM::QQPRRegClassID: 194 case ARM::QQQQPRRegClassID: 195 case ARM::GPRPairRegClassID: 196 return Super; 197 } 198 Super = *I++; 199 } while (Super); 200 return RC; 201} 202 203const TargetRegisterClass * 204ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 205 const { 206 return &ARM::GPRRegClass; 207} 208 209const TargetRegisterClass * 210ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 211 if (RC == &ARM::CCRRegClass) 212 return &ARM::rGPRRegClass; // Can't copy CCR registers. 213 return RC; 214} 215 216unsigned 217ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 218 MachineFunction &MF) const { 219 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 220 const ARMFrameLowering *TFI = getFrameLowering(MF); 221 222 switch (RC->getID()) { 223 default: 224 return 0; 225 case ARM::tGPRRegClassID: 226 return TFI->hasFP(MF) ? 4 : 5; 227 case ARM::GPRRegClassID: { 228 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 229 return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 230 } 231 case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 232 case ARM::DPRRegClassID: 233 return 32 - 10; 234 } 235} 236 237// Get the other register in a GPRPair. 238static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 239 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 240 if (ARM::GPRPairRegClass.contains(*Supers)) 241 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 242 return 0; 243} 244 245// Resolve the RegPairEven / RegPairOdd register allocator hints. 246void 247ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 248 ArrayRef<MCPhysReg> Order, 249 SmallVectorImpl<MCPhysReg> &Hints, 250 const MachineFunction &MF, 251 const VirtRegMap *VRM, 252 const LiveRegMatrix *Matrix) const { 253 const MachineRegisterInfo &MRI = MF.getRegInfo(); 254 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 255 256 unsigned Odd; 257 switch (Hint.first) { 258 case ARMRI::RegPairEven: 259 Odd = 0; 260 break; 261 case ARMRI::RegPairOdd: 262 Odd = 1; 263 break; 264 default: 265 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 266 return; 267 } 268 269 // This register should preferably be even (Odd == 0) or odd (Odd == 1). 270 // Check if the other part of the pair has already been assigned, and provide 271 // the paired register as the first hint. 272 unsigned Paired = Hint.second; 273 if (Paired == 0) 274 return; 275 276 unsigned PairedPhys = 0; 277 if (TargetRegisterInfo::isPhysicalRegister(Paired)) { 278 PairedPhys = Paired; 279 } else if (VRM && VRM->hasPhys(Paired)) { 280 PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this); 281 } 282 283 // First prefer the paired physreg. 284 if (PairedPhys && 285 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 286 Hints.push_back(PairedPhys); 287 288 // Then prefer even or odd registers. 289 for (unsigned I = 0, E = Order.size(); I != E; ++I) { 290 unsigned Reg = Order[I]; 291 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 292 continue; 293 // Don't provide hints that are paired to a reserved register. 294 unsigned Paired = getPairedGPR(Reg, !Odd, this); 295 if (!Paired || MRI.isReserved(Paired)) 296 continue; 297 Hints.push_back(Reg); 298 } 299} 300 301void 302ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg, 303 MachineFunction &MF) const { 304 MachineRegisterInfo *MRI = &MF.getRegInfo(); 305 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 306 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 307 Hint.first == (unsigned)ARMRI::RegPairEven) && 308 TargetRegisterInfo::isVirtualRegister(Hint.second)) { 309 // If 'Reg' is one of the even / odd register pair and it's now changed 310 // (e.g. coalesced) into a different register. The other register of the 311 // pair allocation hint must be updated to reflect the relationship 312 // change. 313 unsigned OtherReg = Hint.second; 314 Hint = MRI->getRegAllocationHint(OtherReg); 315 // Make sure the pair has not already divorced. 316 if (Hint.second == Reg) { 317 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 318 if (TargetRegisterInfo::isVirtualRegister(NewReg)) 319 MRI->setRegAllocationHint(NewReg, 320 Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven 321 : ARMRI::RegPairOdd, OtherReg); 322 } 323 } 324} 325 326bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 327 const MachineFrameInfo *MFI = MF.getFrameInfo(); 328 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 329 const ARMFrameLowering *TFI = getFrameLowering(MF); 330 331 // When outgoing call frames are so large that we adjust the stack pointer 332 // around the call, we can no longer use the stack pointer to reach the 333 // emergency spill slot. 334 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 335 return true; 336 337 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 338 // negative range for ldr/str (255), and thumb1 is positive offsets only. 339 // It's going to be better to use the SP or Base Pointer instead. When there 340 // are variable sized objects, we can't reference off of the SP, so we 341 // reserve a Base Pointer. 342 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 343 // Conservatively estimate whether the negative offset from the frame 344 // pointer will be sufficient to reach. If a function has a smallish 345 // frame, it's less likely to have lots of spills and callee saved 346 // space, so it's all more likely to be within range of the frame pointer. 347 // If it's wrong, the scavenger will still enable access to work, it just 348 // won't be optimal. 349 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 350 return false; 351 return true; 352 } 353 354 return false; 355} 356 357bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 358 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 359 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 360 const ARMFrameLowering *TFI = getFrameLowering(MF); 361 // We can't realign the stack if: 362 // 1. Dynamic stack realignment is explicitly disabled, 363 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 364 // 3. There are VLAs in the function and the base pointer is disabled. 365 if (!TargetRegisterInfo::canRealignStack(MF)) 366 return false; 367 if (AFI->isThumb1OnlyFunction()) 368 return false; 369 // Stack realignment requires a frame pointer. If we already started 370 // register allocation with frame pointer elimination, it is too late now. 371 if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>()))) 372 return false; 373 // We may also need a base pointer if there are dynamic allocas or stack 374 // pointer adjustments around calls. 375 if (TFI->hasReservedCallFrame(MF)) 376 return true; 377 // A base pointer is required and allowed. Check that it isn't too late to 378 // reserve it. 379 return MRI->canReserveReg(BasePtr); 380} 381 382bool ARMBaseRegisterInfo:: 383cannotEliminateFrame(const MachineFunction &MF) const { 384 const MachineFrameInfo *MFI = MF.getFrameInfo(); 385 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 386 return true; 387 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 388 || needsStackRealignment(MF); 389} 390 391unsigned 392ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 393 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 394 const ARMFrameLowering *TFI = getFrameLowering(MF); 395 396 if (TFI->hasFP(MF)) 397 return getFramePointerReg(STI); 398 return ARM::SP; 399} 400 401/// emitLoadConstPool - Emits a load from constpool to materialize the 402/// specified immediate. 403void ARMBaseRegisterInfo:: 404emitLoadConstPool(MachineBasicBlock &MBB, 405 MachineBasicBlock::iterator &MBBI, 406 DebugLoc dl, 407 unsigned DestReg, unsigned SubIdx, int Val, 408 ARMCC::CondCodes Pred, 409 unsigned PredReg, unsigned MIFlags) const { 410 MachineFunction &MF = *MBB.getParent(); 411 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 412 MachineConstantPool *ConstantPool = MF.getConstantPool(); 413 const Constant *C = 414 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 415 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 416 417 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 418 .addReg(DestReg, getDefRegState(true), SubIdx) 419 .addConstantPoolIndex(Idx) 420 .addImm(0).addImm(Pred).addReg(PredReg) 421 .setMIFlags(MIFlags); 422} 423 424bool ARMBaseRegisterInfo:: 425requiresRegisterScavenging(const MachineFunction &MF) const { 426 return true; 427} 428 429bool ARMBaseRegisterInfo:: 430trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 431 return true; 432} 433 434bool ARMBaseRegisterInfo:: 435requiresFrameIndexScavenging(const MachineFunction &MF) const { 436 return true; 437} 438 439bool ARMBaseRegisterInfo:: 440requiresVirtualBaseRegisters(const MachineFunction &MF) const { 441 return true; 442} 443 444int64_t ARMBaseRegisterInfo:: 445getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 446 const MCInstrDesc &Desc = MI->getDesc(); 447 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 448 int64_t InstrOffs = 0; 449 int Scale = 1; 450 unsigned ImmIdx = 0; 451 switch (AddrMode) { 452 case ARMII::AddrModeT2_i8: 453 case ARMII::AddrModeT2_i12: 454 case ARMII::AddrMode_i12: 455 InstrOffs = MI->getOperand(Idx+1).getImm(); 456 Scale = 1; 457 break; 458 case ARMII::AddrMode5: { 459 // VFP address mode. 460 const MachineOperand &OffOp = MI->getOperand(Idx+1); 461 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 462 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 463 InstrOffs = -InstrOffs; 464 Scale = 4; 465 break; 466 } 467 case ARMII::AddrMode2: { 468 ImmIdx = Idx+2; 469 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 470 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 471 InstrOffs = -InstrOffs; 472 break; 473 } 474 case ARMII::AddrMode3: { 475 ImmIdx = Idx+2; 476 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 477 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 478 InstrOffs = -InstrOffs; 479 break; 480 } 481 case ARMII::AddrModeT1_s: { 482 ImmIdx = Idx+1; 483 InstrOffs = MI->getOperand(ImmIdx).getImm(); 484 Scale = 4; 485 break; 486 } 487 default: 488 llvm_unreachable("Unsupported addressing mode!"); 489 } 490 491 return InstrOffs * Scale; 492} 493 494/// needsFrameBaseReg - Returns true if the instruction's frame index 495/// reference would be better served by a base register other than FP 496/// or SP. Used by LocalStackFrameAllocation to determine which frame index 497/// references it should create new base registers for. 498bool ARMBaseRegisterInfo:: 499needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 500 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 501 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 502 } 503 504 // It's the load/store FI references that cause issues, as it can be difficult 505 // to materialize the offset if it won't fit in the literal field. Estimate 506 // based on the size of the local frame and some conservative assumptions 507 // about the rest of the stack frame (note, this is pre-regalloc, so 508 // we don't know everything for certain yet) whether this offset is likely 509 // to be out of range of the immediate. Return true if so. 510 511 // We only generate virtual base registers for loads and stores, so 512 // return false for everything else. 513 unsigned Opc = MI->getOpcode(); 514 switch (Opc) { 515 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 516 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 517 case ARM::t2LDRi12: case ARM::t2LDRi8: 518 case ARM::t2STRi12: case ARM::t2STRi8: 519 case ARM::VLDRS: case ARM::VLDRD: 520 case ARM::VSTRS: case ARM::VSTRD: 521 case ARM::tSTRspi: case ARM::tLDRspi: 522 break; 523 default: 524 return false; 525 } 526 527 // Without a virtual base register, if the function has variable sized 528 // objects, all fixed-size local references will be via the frame pointer, 529 // Approximate the offset and see if it's legal for the instruction. 530 // Note that the incoming offset is based on the SP value at function entry, 531 // so it'll be negative. 532 MachineFunction &MF = *MI->getParent()->getParent(); 533 const ARMFrameLowering *TFI = getFrameLowering(MF); 534 MachineFrameInfo *MFI = MF.getFrameInfo(); 535 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 536 537 // Estimate an offset from the frame pointer. 538 // Conservatively assume all callee-saved registers get pushed. R4-R6 539 // will be earlier than the FP, so we ignore those. 540 // R7, LR 541 int64_t FPOffset = Offset - 8; 542 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 543 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 544 FPOffset -= 80; 545 // Estimate an offset from the stack pointer. 546 // The incoming offset is relating to the SP at the start of the function, 547 // but when we access the local it'll be relative to the SP after local 548 // allocation, so adjust our SP-relative offset by that allocation size. 549 Offset += MFI->getLocalFrameSize(); 550 // Assume that we'll have at least some spill slots allocated. 551 // FIXME: This is a total SWAG number. We should run some statistics 552 // and pick a real one. 553 Offset += 128; // 128 bytes of spill slots 554 555 // If there's a frame pointer and the addressing mode allows it, try using it. 556 // The FP is only available if there is no dynamic realignment. We 557 // don't know for sure yet whether we'll need that, so we guess based 558 // on whether there are any local variables that would trigger it. 559 unsigned StackAlign = TFI->getStackAlignment(); 560 if (TFI->hasFP(MF) && 561 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 562 if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset)) 563 return false; 564 } 565 // If we can reference via the stack pointer, try that. 566 // FIXME: This (and the code that resolves the references) can be improved 567 // to only disallow SP relative references in the live range of 568 // the VLA(s). In practice, it's unclear how much difference that 569 // would make, but it may be worth doing. 570 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset)) 571 return false; 572 573 // The offset likely isn't legal, we want to allocate a virtual base register. 574 return true; 575} 576 577/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 578/// be a pointer to FrameIdx at the beginning of the basic block. 579void ARMBaseRegisterInfo:: 580materializeFrameBaseRegister(MachineBasicBlock *MBB, 581 unsigned BaseReg, int FrameIdx, 582 int64_t Offset) const { 583 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 584 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 585 (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri); 586 587 MachineBasicBlock::iterator Ins = MBB->begin(); 588 DebugLoc DL; // Defaults to "unknown" 589 if (Ins != MBB->end()) 590 DL = Ins->getDebugLoc(); 591 592 const MachineFunction &MF = *MBB->getParent(); 593 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 594 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 595 const MCInstrDesc &MCID = TII.get(ADDriOpc); 596 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 597 598 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) 599 .addFrameIndex(FrameIdx).addImm(Offset); 600 601 if (!AFI->isThumb1OnlyFunction()) 602 AddDefaultCC(AddDefaultPred(MIB)); 603} 604 605void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 606 int64_t Offset) const { 607 MachineBasicBlock &MBB = *MI.getParent(); 608 MachineFunction &MF = *MBB.getParent(); 609 const ARMBaseInstrInfo &TII = 610 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 611 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 612 int Off = Offset; // ARM doesn't need the general 64-bit offsets 613 unsigned i = 0; 614 615 assert(!AFI->isThumb1OnlyFunction() && 616 "This resolveFrameIndex does not support Thumb1!"); 617 618 while (!MI.getOperand(i).isFI()) { 619 ++i; 620 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 621 } 622 bool Done = false; 623 if (!AFI->isThumbFunction()) 624 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 625 else { 626 assert(AFI->isThumb2Function()); 627 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 628 } 629 assert (Done && "Unable to resolve frame index!"); 630 (void)Done; 631} 632 633bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, 634 int64_t Offset) const { 635 const MCInstrDesc &Desc = MI->getDesc(); 636 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 637 unsigned i = 0; 638 639 while (!MI->getOperand(i).isFI()) { 640 ++i; 641 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 642 } 643 644 // AddrMode4 and AddrMode6 cannot handle any offset. 645 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 646 return Offset == 0; 647 648 unsigned NumBits = 0; 649 unsigned Scale = 1; 650 bool isSigned = true; 651 switch (AddrMode) { 652 case ARMII::AddrModeT2_i8: 653 case ARMII::AddrModeT2_i12: 654 // i8 supports only negative, and i12 supports only positive, so 655 // based on Offset sign, consider the appropriate instruction 656 Scale = 1; 657 if (Offset < 0) { 658 NumBits = 8; 659 Offset = -Offset; 660 } else { 661 NumBits = 12; 662 } 663 break; 664 case ARMII::AddrMode5: 665 // VFP address mode. 666 NumBits = 8; 667 Scale = 4; 668 break; 669 case ARMII::AddrMode_i12: 670 case ARMII::AddrMode2: 671 NumBits = 12; 672 break; 673 case ARMII::AddrMode3: 674 NumBits = 8; 675 break; 676 case ARMII::AddrModeT1_s: 677 NumBits = (BaseReg == ARM::SP ? 8 : 5); 678 Scale = 4; 679 isSigned = false; 680 break; 681 default: 682 llvm_unreachable("Unsupported addressing mode!"); 683 } 684 685 Offset += getFrameIndexInstrOffset(MI, i); 686 // Make sure the offset is encodable for instructions that scale the 687 // immediate. 688 if ((Offset & (Scale-1)) != 0) 689 return false; 690 691 if (isSigned && Offset < 0) 692 Offset = -Offset; 693 694 unsigned Mask = (1 << NumBits) - 1; 695 if ((unsigned)Offset <= Mask * Scale) 696 return true; 697 698 return false; 699} 700 701void 702ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 703 int SPAdj, unsigned FIOperandNum, 704 RegScavenger *RS) const { 705 MachineInstr &MI = *II; 706 MachineBasicBlock &MBB = *MI.getParent(); 707 MachineFunction &MF = *MBB.getParent(); 708 const ARMBaseInstrInfo &TII = 709 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 710 const ARMFrameLowering *TFI = getFrameLowering(MF); 711 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 712 assert(!AFI->isThumb1OnlyFunction() && 713 "This eliminateFrameIndex does not support Thumb1!"); 714 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 715 unsigned FrameReg; 716 717 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 718 719 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 720 // call frame setup/destroy instructions have already been eliminated. That 721 // means the stack pointer cannot be used to access the emergency spill slot 722 // when !hasReservedCallFrame(). 723#ifndef NDEBUG 724 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 725 assert(TFI->hasReservedCallFrame(MF) && 726 "Cannot use SP to access the emergency spill slot in " 727 "functions without a reserved call frame"); 728 assert(!MF.getFrameInfo()->hasVarSizedObjects() && 729 "Cannot use SP to access the emergency spill slot in " 730 "functions with variable sized frame objects"); 731 } 732#endif // NDEBUG 733 734 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); 735 736 // Modify MI as necessary to handle as much of 'Offset' as possible 737 bool Done = false; 738 if (!AFI->isThumbFunction()) 739 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 740 else { 741 assert(AFI->isThumb2Function()); 742 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 743 } 744 if (Done) 745 return; 746 747 // If we get here, the immediate doesn't fit into the instruction. We folded 748 // as much as possible above, handle the rest, providing a register that is 749 // SP+LargeImm. 750 assert((Offset || 751 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 752 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 753 "This code isn't needed if offset already handled!"); 754 755 unsigned ScratchReg = 0; 756 int PIdx = MI.findFirstPredOperandIdx(); 757 ARMCC::CondCodes Pred = (PIdx == -1) 758 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 759 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 760 if (Offset == 0) 761 // Must be addrmode4/6. 762 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 763 else { 764 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 765 if (!AFI->isThumbFunction()) 766 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 767 Offset, Pred, PredReg, TII); 768 else { 769 assert(AFI->isThumb2Function()); 770 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 771 Offset, Pred, PredReg, TII); 772 } 773 // Update the original instruction to use the scratch register. 774 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 775 } 776} 777 778bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI, 779 const TargetRegisterClass *SrcRC, 780 unsigned SubReg, 781 const TargetRegisterClass *DstRC, 782 unsigned DstSubReg, 783 const TargetRegisterClass *NewRC) const { 784 auto MBB = MI->getParent(); 785 auto MF = MBB->getParent(); 786 const MachineRegisterInfo &MRI = MF->getRegInfo(); 787 // If not copying into a sub-register this should be ok because we shouldn't 788 // need to split the reg. 789 if (!DstSubReg) 790 return true; 791 // Small registers don't frequently cause a problem, so we can coalesce them. 792 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32) 793 return true; 794 795 auto NewRCWeight = 796 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); 797 auto SrcRCWeight = 798 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); 799 auto DstRCWeight = 800 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC); 801 // If the source register class is more expensive than the destination, the 802 // coalescing is probably profitable. 803 if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight) 804 return true; 805 if (DstRCWeight.RegWeight > NewRCWeight.RegWeight) 806 return true; 807 808 // If the register allocator isn't constrained, we can always allow coalescing 809 // unfortunately we don't know yet if we will be constrained. 810 // The goal of this heuristic is to restrict how many expensive registers 811 // we allow to coalesce in a given basic block. 812 auto AFI = MF->getInfo<ARMFunctionInfo>(); 813 auto It = AFI->getCoalescedWeight(MBB); 814 815 DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: " 816 << It->second << "\n"); 817 DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: " 818 << NewRCWeight.RegWeight << "\n"); 819 820 // This number is the largest round number that which meets the criteria: 821 // (1) addresses PR18825 822 // (2) generates better code in some test cases (like vldm-shed-a9.ll) 823 // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC) 824 // In practice the SizeMultiplier will only factor in for straight line code 825 // that uses a lot of NEON vectors, which isn't terribly common. 826 unsigned SizeMultiplier = MBB->size()/100; 827 SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1; 828 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) { 829 It->second += NewRCWeight.RegWeight; 830 return true; 831 } 832 return false; 833} 834