1198090Srdivacky//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2198090Srdivacky// 3198090Srdivacky// The LLVM Compiler Infrastructure 4198090Srdivacky// 5198090Srdivacky// This file is distributed under the University of Illinois Open Source 6198090Srdivacky// License. See LICENSE.TXT for details. 7198090Srdivacky// 8198090Srdivacky//===----------------------------------------------------------------------===// 9198090Srdivacky 10261991Sdim#include "ARMFeatures.h" 11249423Sdim#include "MCTargetDesc/ARMAddressingModes.h" 12226633Sdim#include "MCTargetDesc/ARMBaseInfo.h" 13226633Sdim#include "MCTargetDesc/ARMMCExpr.h" 14249423Sdim#include "llvm/ADT/STLExtras.h" 15249423Sdim#include "llvm/ADT/SmallVector.h" 16276479Sdim#include "llvm/ADT/StringExtras.h" 17249423Sdim#include "llvm/ADT/StringSwitch.h" 18292735Sdim#include "llvm/ADT/Triple.h" 19249423Sdim#include "llvm/ADT/Twine.h" 20223017Sdim#include "llvm/MC/MCAsmInfo.h" 21249423Sdim#include "llvm/MC/MCAssembler.h" 22218893Sdim#include "llvm/MC/MCContext.h" 23276479Sdim#include "llvm/MC/MCDisassembler.h" 24249423Sdim#include "llvm/MC/MCELFStreamer.h" 25198090Srdivacky#include "llvm/MC/MCExpr.h" 26198090Srdivacky#include "llvm/MC/MCInst.h" 27226633Sdim#include "llvm/MC/MCInstrDesc.h" 28261991Sdim#include "llvm/MC/MCInstrInfo.h" 29276479Sdim#include "llvm/MC/MCObjectFileInfo.h" 30249423Sdim#include "llvm/MC/MCParser/MCAsmLexer.h" 31249423Sdim#include "llvm/MC/MCParser/MCAsmParser.h" 32288943Sdim#include "llvm/MC/MCParser/MCAsmParserUtils.h" 33249423Sdim#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 34226633Sdim#include "llvm/MC/MCRegisterInfo.h" 35276479Sdim#include "llvm/MC/MCSection.h" 36249423Sdim#include "llvm/MC/MCStreamer.h" 37224145Sdim#include "llvm/MC/MCSubtargetInfo.h" 38276479Sdim#include "llvm/MC/MCSymbol.h" 39276479Sdim#include "llvm/MC/MCTargetAsmParser.h" 40276479Sdim#include "llvm/Support/ARMBuildAttributes.h" 41276479Sdim#include "llvm/Support/ARMEHABI.h" 42288943Sdim#include "llvm/Support/TargetParser.h" 43276479Sdim#include "llvm/Support/COFF.h" 44276479Sdim#include "llvm/Support/Debug.h" 45249423Sdim#include "llvm/Support/ELF.h" 46226633Sdim#include "llvm/Support/MathExtras.h" 47198090Srdivacky#include "llvm/Support/SourceMgr.h" 48226633Sdim#include "llvm/Support/TargetRegistry.h" 49212904Sdim#include "llvm/Support/raw_ostream.h" 50224145Sdim 51198090Srdivackyusing namespace llvm; 52198090Srdivacky 53218893Sdimnamespace { 54218893Sdim 55218893Sdimclass ARMOperand; 56218893Sdim 57234353Sdimenum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 58234353Sdim 59276479Sdimclass UnwindContext { 60276479Sdim MCAsmParser &Parser; 61276479Sdim 62276479Sdim typedef SmallVector<SMLoc, 4> Locs; 63276479Sdim 64276479Sdim Locs FnStartLocs; 65276479Sdim Locs CantUnwindLocs; 66276479Sdim Locs PersonalityLocs; 67276479Sdim Locs PersonalityIndexLocs; 68276479Sdim Locs HandlerDataLocs; 69276479Sdim int FPReg; 70276479Sdim 71276479Sdimpublic: 72276479Sdim UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} 73276479Sdim 74276479Sdim bool hasFnStart() const { return !FnStartLocs.empty(); } 75276479Sdim bool cantUnwind() const { return !CantUnwindLocs.empty(); } 76276479Sdim bool hasHandlerData() const { return !HandlerDataLocs.empty(); } 77276479Sdim bool hasPersonality() const { 78276479Sdim return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty()); 79276479Sdim } 80276479Sdim 81276479Sdim void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); } 82276479Sdim void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); } 83276479Sdim void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); } 84276479Sdim void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); } 85276479Sdim void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); } 86276479Sdim 87276479Sdim void saveFPReg(int Reg) { FPReg = Reg; } 88276479Sdim int getFPReg() const { return FPReg; } 89276479Sdim 90276479Sdim void emitFnStartLocNotes() const { 91276479Sdim for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end(); 92276479Sdim FI != FE; ++FI) 93276479Sdim Parser.Note(*FI, ".fnstart was specified here"); 94276479Sdim } 95276479Sdim void emitCantUnwindLocNotes() const { 96276479Sdim for (Locs::const_iterator UI = CantUnwindLocs.begin(), 97276479Sdim UE = CantUnwindLocs.end(); UI != UE; ++UI) 98276479Sdim Parser.Note(*UI, ".cantunwind was specified here"); 99276479Sdim } 100276479Sdim void emitHandlerDataLocNotes() const { 101276479Sdim for (Locs::const_iterator HI = HandlerDataLocs.begin(), 102276479Sdim HE = HandlerDataLocs.end(); HI != HE; ++HI) 103276479Sdim Parser.Note(*HI, ".handlerdata was specified here"); 104276479Sdim } 105276479Sdim void emitPersonalityLocNotes() const { 106276479Sdim for (Locs::const_iterator PI = PersonalityLocs.begin(), 107276479Sdim PE = PersonalityLocs.end(), 108276479Sdim PII = PersonalityIndexLocs.begin(), 109276479Sdim PIE = PersonalityIndexLocs.end(); 110276479Sdim PI != PE || PII != PIE;) { 111276479Sdim if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer())) 112276479Sdim Parser.Note(*PI++, ".personality was specified here"); 113276479Sdim else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer())) 114276479Sdim Parser.Note(*PII++, ".personalityindex was specified here"); 115276479Sdim else 116276479Sdim llvm_unreachable(".personality and .personalityindex cannot be " 117276479Sdim "at the same location"); 118276479Sdim } 119276479Sdim } 120276479Sdim 121276479Sdim void reset() { 122276479Sdim FnStartLocs = Locs(); 123276479Sdim CantUnwindLocs = Locs(); 124276479Sdim PersonalityLocs = Locs(); 125276479Sdim HandlerDataLocs = Locs(); 126276479Sdim PersonalityIndexLocs = Locs(); 127276479Sdim FPReg = ARM::SP; 128276479Sdim } 129276479Sdim}; 130276479Sdim 131226633Sdimclass ARMAsmParser : public MCTargetAsmParser { 132261991Sdim const MCInstrInfo &MII; 133234353Sdim const MCRegisterInfo *MRI; 134276479Sdim UnwindContext UC; 135198090Srdivacky 136261991Sdim ARMTargetStreamer &getTargetStreamer() { 137280031Sdim assert(getParser().getStreamer().getTargetStreamer() && 138280031Sdim "do not have a target streamer"); 139276479Sdim MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); 140261991Sdim return static_cast<ARMTargetStreamer &>(TS); 141261991Sdim } 142261991Sdim 143234353Sdim // Map of register aliases registers via the .req directive. 144234353Sdim StringMap<unsigned> RegisterReqs; 145234353Sdim 146261991Sdim bool NextSymbolIsThumb; 147261991Sdim 148226633Sdim struct { 149226633Sdim ARMCC::CondCodes Cond; // Condition for IT block. 150226633Sdim unsigned Mask:4; // Condition mask for instructions. 151226633Sdim // Starting at first 1 (from lsb). 152226633Sdim // '1' condition as indicated in IT. 153226633Sdim // '0' inverse of condition (else). 154226633Sdim // Count of instructions in IT block is 155226633Sdim // 4 - trailingzeroes(mask) 156226633Sdim 157226633Sdim bool FirstCond; // Explicit flag for when we're parsing the 158226633Sdim // First instruction in the IT block. It's 159226633Sdim // implied in the mask, so needs special 160226633Sdim // handling. 161226633Sdim 162226633Sdim unsigned CurPosition; // Current position in parsing of IT 163226633Sdim // block. In range [0,3]. Initialized 164226633Sdim // according to count of instructions in block. 165226633Sdim // ~0U if no active IT block. 166226633Sdim } ITState; 167280031Sdim bool inITBlock() { return ITState.CurPosition != ~0U; } 168280031Sdim bool lastInITBlock() { 169280031Sdim return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask); 170280031Sdim } 171226633Sdim void forwardITPosition() { 172226633Sdim if (!inITBlock()) return; 173226633Sdim // Move to the next instruction in the IT block, if there is one. If not, 174226633Sdim // mark the block as done. 175261991Sdim unsigned TZ = countTrailingZeros(ITState.Mask); 176226633Sdim if (++ITState.CurPosition == 5 - TZ) 177226633Sdim ITState.CurPosition = ~0U; // Done with the IT block after this. 178226633Sdim } 179226633Sdim 180276479Sdim void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) { 181280031Sdim return getParser().Note(L, Msg, Ranges); 182276479Sdim } 183234982Sdim bool Warning(SMLoc L, const Twine &Msg, 184251662Sdim ArrayRef<SMRange> Ranges = None) { 185280031Sdim return getParser().Warning(L, Msg, Ranges); 186234982Sdim } 187234982Sdim bool Error(SMLoc L, const Twine &Msg, 188251662Sdim ArrayRef<SMRange> Ranges = None) { 189280031Sdim return getParser().Error(L, Msg, Ranges); 190234982Sdim } 191198090Srdivacky 192288943Sdim bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands, 193280031Sdim unsigned ListNo, bool IsARPop = false); 194288943Sdim bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands, 195280031Sdim unsigned ListNo); 196280031Sdim 197226633Sdim int tryParseRegister(); 198276479Sdim bool tryParseRegisterWithWriteBack(OperandVector &); 199276479Sdim int tryParseShiftRegister(OperandVector &); 200276479Sdim bool parseRegisterList(OperandVector &); 201276479Sdim bool parseMemory(OperandVector &); 202276479Sdim bool parseOperand(OperandVector &, StringRef Mnemonic); 203226633Sdim bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 204226633Sdim bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 205226633Sdim unsigned &ShiftAmount); 206276479Sdim bool parseLiteralValues(unsigned Size, SMLoc L); 207226633Sdim bool parseDirectiveThumb(SMLoc L); 208234353Sdim bool parseDirectiveARM(SMLoc L); 209226633Sdim bool parseDirectiveThumbFunc(SMLoc L); 210226633Sdim bool parseDirectiveCode(SMLoc L); 211226633Sdim bool parseDirectiveSyntax(SMLoc L); 212234353Sdim bool parseDirectiveReq(StringRef Name, SMLoc L); 213234353Sdim bool parseDirectiveUnreq(SMLoc L); 214234353Sdim bool parseDirectiveArch(SMLoc L); 215234353Sdim bool parseDirectiveEabiAttr(SMLoc L); 216261991Sdim bool parseDirectiveCPU(SMLoc L); 217261991Sdim bool parseDirectiveFPU(SMLoc L); 218261991Sdim bool parseDirectiveFnStart(SMLoc L); 219261991Sdim bool parseDirectiveFnEnd(SMLoc L); 220261991Sdim bool parseDirectiveCantUnwind(SMLoc L); 221261991Sdim bool parseDirectivePersonality(SMLoc L); 222261991Sdim bool parseDirectiveHandlerData(SMLoc L); 223261991Sdim bool parseDirectiveSetFP(SMLoc L); 224261991Sdim bool parseDirectivePad(SMLoc L); 225261991Sdim bool parseDirectiveRegSave(SMLoc L, bool IsVector); 226276479Sdim bool parseDirectiveInst(SMLoc L, char Suffix = '\0'); 227276479Sdim bool parseDirectiveLtorg(SMLoc L); 228276479Sdim bool parseDirectiveEven(SMLoc L); 229276479Sdim bool parseDirectivePersonalityIndex(SMLoc L); 230276479Sdim bool parseDirectiveUnwindRaw(SMLoc L); 231276479Sdim bool parseDirectiveTLSDescSeq(SMLoc L); 232276479Sdim bool parseDirectiveMovSP(SMLoc L); 233276479Sdim bool parseDirectiveObjectArch(SMLoc L); 234276479Sdim bool parseDirectiveArchExtension(SMLoc L); 235276479Sdim bool parseDirectiveAlign(SMLoc L); 236276479Sdim bool parseDirectiveThumbSet(SMLoc L); 237198090Srdivacky 238226633Sdim StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 239226633Sdim bool &CarrySetting, unsigned &ProcessorIMod, 240226633Sdim StringRef &ITMask); 241261991Sdim void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, 242261991Sdim bool &CanAcceptCarrySet, 243218893Sdim bool &CanAcceptPredicationCode); 244198090Srdivacky 245288943Sdim void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting, 246288943Sdim OperandVector &Operands); 247224145Sdim bool isThumb() const { 248224145Sdim // FIXME: Can tablegen auto-generate this? 249296417Sdim return getSTI().getFeatureBits()[ARM::ModeThumb]; 250224145Sdim } 251224145Sdim bool isThumbOne() const { 252296417Sdim return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2]; 253224145Sdim } 254226633Sdim bool isThumbTwo() const { 255296417Sdim return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2]; 256226633Sdim } 257261991Sdim bool hasThumb() const { 258296417Sdim return getSTI().getFeatureBits()[ARM::HasV4TOps]; 259261991Sdim } 260226633Sdim bool hasV6Ops() const { 261296417Sdim return getSTI().getFeatureBits()[ARM::HasV6Ops]; 262226633Sdim } 263261991Sdim bool hasV6MOps() const { 264296417Sdim return getSTI().getFeatureBits()[ARM::HasV6MOps]; 265261991Sdim } 266226633Sdim bool hasV7Ops() const { 267296417Sdim return getSTI().getFeatureBits()[ARM::HasV7Ops]; 268226633Sdim } 269261991Sdim bool hasV8Ops() const { 270296417Sdim return getSTI().getFeatureBits()[ARM::HasV8Ops]; 271261991Sdim } 272261991Sdim bool hasARM() const { 273296417Sdim return !getSTI().getFeatureBits()[ARM::FeatureNoARM]; 274261991Sdim } 275296417Sdim bool hasDSP() const { 276296417Sdim return getSTI().getFeatureBits()[ARM::FeatureDSP]; 277280031Sdim } 278280031Sdim bool hasD16() const { 279296417Sdim return getSTI().getFeatureBits()[ARM::FeatureD16]; 280280031Sdim } 281288943Sdim bool hasV8_1aOps() const { 282296417Sdim return getSTI().getFeatureBits()[ARM::HasV8_1aOps]; 283288943Sdim } 284261991Sdim 285224145Sdim void SwitchMode() { 286296417Sdim MCSubtargetInfo &STI = copySTI(); 287280031Sdim uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 288224145Sdim setAvailableFeatures(FB); 289224145Sdim } 290226633Sdim bool isMClass() const { 291296417Sdim return getSTI().getFeatureBits()[ARM::FeatureMClass]; 292226633Sdim } 293224145Sdim 294198090Srdivacky /// @name Auto-generated Match Functions 295198090Srdivacky /// { 296198090Srdivacky 297218893Sdim#define GET_ASSEMBLER_HEADER 298218893Sdim#include "ARMGenAsmMatcher.inc" 299198090Srdivacky 300198090Srdivacky /// } 301198090Srdivacky 302276479Sdim OperandMatchResultTy parseITCondCode(OperandVector &); 303276479Sdim OperandMatchResultTy parseCoprocNumOperand(OperandVector &); 304276479Sdim OperandMatchResultTy parseCoprocRegOperand(OperandVector &); 305276479Sdim OperandMatchResultTy parseCoprocOptionOperand(OperandVector &); 306276479Sdim OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &); 307276479Sdim OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &); 308276479Sdim OperandMatchResultTy parseProcIFlagsOperand(OperandVector &); 309276479Sdim OperandMatchResultTy parseMSRMaskOperand(OperandVector &); 310280031Sdim OperandMatchResultTy parseBankedRegOperand(OperandVector &); 311276479Sdim OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low, 312276479Sdim int High); 313276479Sdim OperandMatchResultTy parsePKHLSLImm(OperandVector &O) { 314226633Sdim return parsePKHImm(O, "lsl", 0, 31); 315226633Sdim } 316276479Sdim OperandMatchResultTy parsePKHASRImm(OperandVector &O) { 317226633Sdim return parsePKHImm(O, "asr", 1, 32); 318226633Sdim } 319276479Sdim OperandMatchResultTy parseSetEndImm(OperandVector &); 320276479Sdim OperandMatchResultTy parseShifterImm(OperandVector &); 321276479Sdim OperandMatchResultTy parseRotImm(OperandVector &); 322280031Sdim OperandMatchResultTy parseModImm(OperandVector &); 323276479Sdim OperandMatchResultTy parseBitfield(OperandVector &); 324276479Sdim OperandMatchResultTy parsePostIdxReg(OperandVector &); 325276479Sdim OperandMatchResultTy parseAM3Offset(OperandVector &); 326276479Sdim OperandMatchResultTy parseFPImm(OperandVector &); 327276479Sdim OperandMatchResultTy parseVectorList(OperandVector &); 328249423Sdim OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, 329249423Sdim SMLoc &EndLoc); 330198090Srdivacky 331221345Sdim // Asm Match Converter Methods 332276479Sdim void cvtThumbMultiply(MCInst &Inst, const OperandVector &); 333276479Sdim void cvtThumbBranches(MCInst &Inst, const OperandVector &); 334276479Sdim 335276479Sdim bool validateInstruction(MCInst &Inst, const OperandVector &Ops); 336276537Sdim bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out); 337276479Sdim bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands); 338276479Sdim bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands); 339276479Sdim 340198090Srdivackypublic: 341226633Sdim enum ARMMatchResultTy { 342226633Sdim Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 343226633Sdim Match_RequiresNotITBlock, 344226633Sdim Match_RequiresV6, 345239462Sdim Match_RequiresThumb2, 346296417Sdim Match_RequiresV8, 347239462Sdim#define GET_OPERAND_DIAGNOSTIC_TYPES 348239462Sdim#include "ARMGenAsmMatcher.inc" 349239462Sdim 350226633Sdim }; 351226633Sdim 352296417Sdim ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, 353280031Sdim const MCInstrInfo &MII, const MCTargetOptions &Options) 354296417Sdim : MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) { 355288943Sdim MCAsmParserExtension::Initialize(Parser); 356198090Srdivacky 357234353Sdim // Cache the MCRegisterInfo. 358261991Sdim MRI = getContext().getRegisterInfo(); 359234353Sdim 360224145Sdim // Initialize the set of available features. 361224145Sdim setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 362226633Sdim 363226633Sdim // Not in an ITBlock to start with. 364226633Sdim ITState.CurPosition = ~0U; 365249423Sdim 366261991Sdim NextSymbolIsThumb = false; 367224145Sdim } 368224145Sdim 369226633Sdim // Implementation of the MCTargetAsmParser interface: 370276479Sdim bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 371243830Sdim bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 372276479Sdim SMLoc NameLoc, OperandVector &Operands) override; 373276479Sdim bool ParseDirective(AsmToken DirectiveID) override; 374226633Sdim 375276479Sdim unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 376276479Sdim unsigned Kind) override; 377276479Sdim unsigned checkTargetMatchPredicate(MCInst &Inst) override; 378226633Sdim 379243830Sdim bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 380276479Sdim OperandVector &Operands, MCStreamer &Out, 381280031Sdim uint64_t &ErrorInfo, 382276479Sdim bool MatchingInlineAsm) override; 383276479Sdim void onLabelParsed(MCSymbol *Symbol) override; 384198090Srdivacky}; 385218893Sdim} // end anonymous namespace 386218893Sdim 387218893Sdimnamespace { 388218893Sdim 389198090Srdivacky/// ARMOperand - Instances of this class represent a parsed ARM machine 390249423Sdim/// operand. 391218893Sdimclass ARMOperand : public MCParsedAsmOperand { 392206124Srdivacky enum KindTy { 393226633Sdim k_CondCode, 394226633Sdim k_CCOut, 395226633Sdim k_ITCondMask, 396226633Sdim k_CoprocNum, 397226633Sdim k_CoprocReg, 398226633Sdim k_CoprocOption, 399226633Sdim k_Immediate, 400226633Sdim k_MemBarrierOpt, 401261991Sdim k_InstSyncBarrierOpt, 402226633Sdim k_Memory, 403226633Sdim k_PostIndexRegister, 404226633Sdim k_MSRMask, 405280031Sdim k_BankedReg, 406226633Sdim k_ProcIFlags, 407226633Sdim k_VectorIndex, 408226633Sdim k_Register, 409226633Sdim k_RegisterList, 410226633Sdim k_DPRRegisterList, 411226633Sdim k_SPRRegisterList, 412234353Sdim k_VectorList, 413234353Sdim k_VectorListAllLanes, 414234353Sdim k_VectorListIndexed, 415226633Sdim k_ShiftedRegister, 416226633Sdim k_ShiftedImmediate, 417226633Sdim k_ShifterImmediate, 418226633Sdim k_RotateImmediate, 419280031Sdim k_ModifiedImmediate, 420226633Sdim k_BitfieldDescriptor, 421226633Sdim k_Token 422198090Srdivacky } Kind; 423198090Srdivacky 424276479Sdim SMLoc StartLoc, EndLoc, AlignmentLoc; 425218893Sdim SmallVector<unsigned, 8> Registers; 426198090Srdivacky 427249423Sdim struct CCOp { 428249423Sdim ARMCC::CondCodes Val; 429249423Sdim }; 430212904Sdim 431249423Sdim struct CopOp { 432249423Sdim unsigned Val; 433249423Sdim }; 434218893Sdim 435249423Sdim struct CoprocOptionOp { 436249423Sdim unsigned Val; 437249423Sdim }; 438218893Sdim 439249423Sdim struct ITMaskOp { 440249423Sdim unsigned Mask:4; 441249423Sdim }; 442226633Sdim 443249423Sdim struct MBOptOp { 444249423Sdim ARM_MB::MemBOpt Val; 445249423Sdim }; 446226633Sdim 447261991Sdim struct ISBOptOp { 448261991Sdim ARM_ISB::InstSyncBOpt Val; 449261991Sdim }; 450261991Sdim 451249423Sdim struct IFlagsOp { 452249423Sdim ARM_PROC::IFlags Val; 453249423Sdim }; 454218893Sdim 455249423Sdim struct MMaskOp { 456249423Sdim unsigned Val; 457249423Sdim }; 458218893Sdim 459280031Sdim struct BankedRegOp { 460280031Sdim unsigned Val; 461280031Sdim }; 462280031Sdim 463249423Sdim struct TokOp { 464249423Sdim const char *Data; 465249423Sdim unsigned Length; 466249423Sdim }; 467198090Srdivacky 468249423Sdim struct RegOp { 469249423Sdim unsigned RegNum; 470249423Sdim }; 471198090Srdivacky 472249423Sdim // A vector register list is a sequential list of 1 to 4 registers. 473249423Sdim struct VectorListOp { 474249423Sdim unsigned RegNum; 475249423Sdim unsigned Count; 476249423Sdim unsigned LaneIndex; 477249423Sdim bool isDoubleSpaced; 478249423Sdim }; 479234353Sdim 480249423Sdim struct VectorIndexOp { 481249423Sdim unsigned Val; 482249423Sdim }; 483226633Sdim 484249423Sdim struct ImmOp { 485249423Sdim const MCExpr *Val; 486249423Sdim }; 487218893Sdim 488249423Sdim /// Combined record for all forms of ARM address expressions. 489249423Sdim struct MemoryOp { 490249423Sdim unsigned BaseRegNum; 491249423Sdim // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 492249423Sdim // was specified. 493249423Sdim const MCConstantExpr *OffsetImm; // Offset immediate value 494249423Sdim unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 495249423Sdim ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 496249423Sdim unsigned ShiftImm; // shift for OffsetReg. 497249423Sdim unsigned Alignment; // 0 = no alignment specified 498249423Sdim // n = alignment in bytes (2, 4, 8, 16, or 32) 499249423Sdim unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 500249423Sdim }; 501221345Sdim 502249423Sdim struct PostIdxRegOp { 503249423Sdim unsigned RegNum; 504249423Sdim bool isAdd; 505249423Sdim ARM_AM::ShiftOpc ShiftTy; 506249423Sdim unsigned ShiftImm; 507249423Sdim }; 508226633Sdim 509249423Sdim struct ShifterImmOp { 510249423Sdim bool isASR; 511249423Sdim unsigned Imm; 512218893Sdim }; 513198090Srdivacky 514249423Sdim struct RegShiftedRegOp { 515249423Sdim ARM_AM::ShiftOpc ShiftTy; 516249423Sdim unsigned SrcReg; 517249423Sdim unsigned ShiftReg; 518249423Sdim unsigned ShiftImm; 519249423Sdim }; 520249423Sdim 521249423Sdim struct RegShiftedImmOp { 522249423Sdim ARM_AM::ShiftOpc ShiftTy; 523249423Sdim unsigned SrcReg; 524249423Sdim unsigned ShiftImm; 525249423Sdim }; 526249423Sdim 527249423Sdim struct RotImmOp { 528249423Sdim unsigned Imm; 529249423Sdim }; 530249423Sdim 531280031Sdim struct ModImmOp { 532280031Sdim unsigned Bits; 533280031Sdim unsigned Rot; 534280031Sdim }; 535280031Sdim 536249423Sdim struct BitfieldOp { 537249423Sdim unsigned LSB; 538249423Sdim unsigned Width; 539249423Sdim }; 540249423Sdim 541249423Sdim union { 542249423Sdim struct CCOp CC; 543249423Sdim struct CopOp Cop; 544249423Sdim struct CoprocOptionOp CoprocOption; 545249423Sdim struct MBOptOp MBOpt; 546261991Sdim struct ISBOptOp ISBOpt; 547249423Sdim struct ITMaskOp ITMask; 548249423Sdim struct IFlagsOp IFlags; 549249423Sdim struct MMaskOp MMask; 550280031Sdim struct BankedRegOp BankedReg; 551249423Sdim struct TokOp Tok; 552249423Sdim struct RegOp Reg; 553249423Sdim struct VectorListOp VectorList; 554249423Sdim struct VectorIndexOp VectorIndex; 555249423Sdim struct ImmOp Imm; 556249423Sdim struct MemoryOp Memory; 557249423Sdim struct PostIdxRegOp PostIdxReg; 558249423Sdim struct ShifterImmOp ShifterImm; 559249423Sdim struct RegShiftedRegOp RegShiftedReg; 560249423Sdim struct RegShiftedImmOp RegShiftedImm; 561249423Sdim struct RotImmOp RotImm; 562280031Sdim struct ModImmOp ModImm; 563249423Sdim struct BitfieldOp Bitfield; 564249423Sdim }; 565249423Sdim 566276479Sdimpublic: 567218893Sdim ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 568218893Sdim 569206124Srdivacky /// getStartLoc - Get the location of the first token of this operand. 570276479Sdim SMLoc getStartLoc() const override { return StartLoc; } 571206124Srdivacky /// getEndLoc - Get the location of the last token of this operand. 572276479Sdim SMLoc getEndLoc() const override { return EndLoc; } 573243830Sdim /// getLocRange - Get the range between the first and last token of this 574243830Sdim /// operand. 575234982Sdim SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 576234982Sdim 577276479Sdim /// getAlignmentLoc - Get the location of the Alignment token of this operand. 578276479Sdim SMLoc getAlignmentLoc() const { 579276479Sdim assert(Kind == k_Memory && "Invalid access!"); 580276479Sdim return AlignmentLoc; 581276479Sdim } 582276479Sdim 583212904Sdim ARMCC::CondCodes getCondCode() const { 584226633Sdim assert(Kind == k_CondCode && "Invalid access!"); 585212904Sdim return CC.Val; 586212904Sdim } 587212904Sdim 588218893Sdim unsigned getCoproc() const { 589226633Sdim assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 590218893Sdim return Cop.Val; 591218893Sdim } 592218893Sdim 593198090Srdivacky StringRef getToken() const { 594226633Sdim assert(Kind == k_Token && "Invalid access!"); 595198090Srdivacky return StringRef(Tok.Data, Tok.Length); 596198090Srdivacky } 597198090Srdivacky 598276479Sdim unsigned getReg() const override { 599226633Sdim assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 600198090Srdivacky return Reg.RegNum; 601198090Srdivacky } 602198090Srdivacky 603218893Sdim const SmallVectorImpl<unsigned> &getRegList() const { 604226633Sdim assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 605226633Sdim Kind == k_SPRRegisterList) && "Invalid access!"); 606218893Sdim return Registers; 607218893Sdim } 608218893Sdim 609198090Srdivacky const MCExpr *getImm() const { 610234353Sdim assert(isImm() && "Invalid access!"); 611198090Srdivacky return Imm.Val; 612198090Srdivacky } 613198090Srdivacky 614226633Sdim unsigned getVectorIndex() const { 615226633Sdim assert(Kind == k_VectorIndex && "Invalid access!"); 616226633Sdim return VectorIndex.Val; 617226633Sdim } 618226633Sdim 619218893Sdim ARM_MB::MemBOpt getMemBarrierOpt() const { 620226633Sdim assert(Kind == k_MemBarrierOpt && "Invalid access!"); 621218893Sdim return MBOpt.Val; 622218893Sdim } 623218893Sdim 624261991Sdim ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { 625261991Sdim assert(Kind == k_InstSyncBarrierOpt && "Invalid access!"); 626261991Sdim return ISBOpt.Val; 627261991Sdim } 628261991Sdim 629218893Sdim ARM_PROC::IFlags getProcIFlags() const { 630226633Sdim assert(Kind == k_ProcIFlags && "Invalid access!"); 631218893Sdim return IFlags.Val; 632218893Sdim } 633218893Sdim 634218893Sdim unsigned getMSRMask() const { 635226633Sdim assert(Kind == k_MSRMask && "Invalid access!"); 636218893Sdim return MMask.Val; 637218893Sdim } 638218893Sdim 639280031Sdim unsigned getBankedReg() const { 640280031Sdim assert(Kind == k_BankedReg && "Invalid access!"); 641280031Sdim return BankedReg.Val; 642280031Sdim } 643280031Sdim 644226633Sdim bool isCoprocNum() const { return Kind == k_CoprocNum; } 645226633Sdim bool isCoprocReg() const { return Kind == k_CoprocReg; } 646226633Sdim bool isCoprocOption() const { return Kind == k_CoprocOption; } 647226633Sdim bool isCondCode() const { return Kind == k_CondCode; } 648226633Sdim bool isCCOut() const { return Kind == k_CCOut; } 649226633Sdim bool isITMask() const { return Kind == k_ITCondMask; } 650226633Sdim bool isITCondCode() const { return Kind == k_CondCode; } 651276479Sdim bool isImm() const override { return Kind == k_Immediate; } 652261991Sdim // checks whether this operand is an unsigned offset which fits is a field 653261991Sdim // of specified width and scaled by a specific number of bits 654261991Sdim template<unsigned width, unsigned scale> 655261991Sdim bool isUnsignedOffset() const { 656261991Sdim if (!isImm()) return false; 657261991Sdim if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 658261991Sdim if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 659261991Sdim int64_t Val = CE->getValue(); 660261991Sdim int64_t Align = 1LL << scale; 661261991Sdim int64_t Max = Align * ((1LL << width) - 1); 662261991Sdim return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max); 663261991Sdim } 664261991Sdim return false; 665261991Sdim } 666261991Sdim // checks whether this operand is an signed offset which fits is a field 667261991Sdim // of specified width and scaled by a specific number of bits 668261991Sdim template<unsigned width, unsigned scale> 669261991Sdim bool isSignedOffset() const { 670261991Sdim if (!isImm()) return false; 671261991Sdim if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 672261991Sdim if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 673261991Sdim int64_t Val = CE->getValue(); 674261991Sdim int64_t Align = 1LL << scale; 675261991Sdim int64_t Max = Align * ((1LL << (width-1)) - 1); 676261991Sdim int64_t Min = -Align * (1LL << (width-1)); 677261991Sdim return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max); 678261991Sdim } 679261991Sdim return false; 680261991Sdim } 681261991Sdim 682261991Sdim // checks whether this operand is a memory operand computed as an offset 683261991Sdim // applied to PC. the offset may have 8 bits of magnitude and is represented 684261991Sdim // with two bits of shift. textually it may be either [pc, #imm], #imm or 685261991Sdim // relocable expression... 686261991Sdim bool isThumbMemPC() const { 687261991Sdim int64_t Val = 0; 688261991Sdim if (isImm()) { 689261991Sdim if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 690261991Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val); 691261991Sdim if (!CE) return false; 692261991Sdim Val = CE->getValue(); 693261991Sdim } 694261991Sdim else if (isMem()) { 695261991Sdim if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; 696261991Sdim if(Memory.BaseRegNum != ARM::PC) return false; 697261991Sdim Val = Memory.OffsetImm->getValue(); 698261991Sdim } 699261991Sdim else return false; 700261991Sdim return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020); 701261991Sdim } 702234353Sdim bool isFPImm() const { 703234353Sdim if (!isImm()) return false; 704234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 705234353Sdim if (!CE) return false; 706234353Sdim int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 707234353Sdim return Val != -1; 708234353Sdim } 709234353Sdim bool isFBits16() const { 710234353Sdim if (!isImm()) return false; 711234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 712234353Sdim if (!CE) return false; 713234353Sdim int64_t Value = CE->getValue(); 714234353Sdim return Value >= 0 && Value <= 16; 715234353Sdim } 716234353Sdim bool isFBits32() const { 717234353Sdim if (!isImm()) return false; 718234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 719234353Sdim if (!CE) return false; 720234353Sdim int64_t Value = CE->getValue(); 721234353Sdim return Value >= 1 && Value <= 32; 722234353Sdim } 723226633Sdim bool isImm8s4() const { 724234353Sdim if (!isImm()) return false; 725226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 726226633Sdim if (!CE) return false; 727226633Sdim int64_t Value = CE->getValue(); 728226633Sdim return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 729221345Sdim } 730226633Sdim bool isImm0_1020s4() const { 731234353Sdim if (!isImm()) return false; 732226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 733226633Sdim if (!CE) return false; 734226633Sdim int64_t Value = CE->getValue(); 735226633Sdim return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 736218893Sdim } 737226633Sdim bool isImm0_508s4() const { 738234353Sdim if (!isImm()) return false; 739226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 740226633Sdim if (!CE) return false; 741226633Sdim int64_t Value = CE->getValue(); 742226633Sdim return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 743218893Sdim } 744234353Sdim bool isImm0_508s4Neg() const { 745234353Sdim if (!isImm()) return false; 746234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 747234353Sdim if (!CE) return false; 748234353Sdim int64_t Value = -CE->getValue(); 749234353Sdim // explicitly exclude zero. we want that to use the normal 0_508 version. 750234353Sdim return ((Value & 3) == 0) && Value > 0 && Value <= 508; 751234353Sdim } 752261991Sdim bool isImm0_239() const { 753261991Sdim if (!isImm()) return false; 754261991Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 755261991Sdim if (!CE) return false; 756261991Sdim int64_t Value = CE->getValue(); 757261991Sdim return Value >= 0 && Value < 240; 758261991Sdim } 759224145Sdim bool isImm0_255() const { 760234353Sdim if (!isImm()) return false; 761224145Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 762224145Sdim if (!CE) return false; 763224145Sdim int64_t Value = CE->getValue(); 764224145Sdim return Value >= 0 && Value < 256; 765224145Sdim } 766234353Sdim bool isImm0_4095() const { 767234353Sdim if (!isImm()) return false; 768234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 769234353Sdim if (!CE) return false; 770234353Sdim int64_t Value = CE->getValue(); 771234353Sdim return Value >= 0 && Value < 4096; 772234353Sdim } 773234353Sdim bool isImm0_4095Neg() const { 774234353Sdim if (!isImm()) return false; 775234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 776234353Sdim if (!CE) return false; 777234353Sdim int64_t Value = -CE->getValue(); 778234353Sdim return Value > 0 && Value < 4096; 779234353Sdim } 780234353Sdim bool isImm0_1() const { 781234353Sdim if (!isImm()) return false; 782234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 783234353Sdim if (!CE) return false; 784234353Sdim int64_t Value = CE->getValue(); 785234353Sdim return Value >= 0 && Value < 2; 786234353Sdim } 787234353Sdim bool isImm0_3() const { 788234353Sdim if (!isImm()) return false; 789234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 790234353Sdim if (!CE) return false; 791234353Sdim int64_t Value = CE->getValue(); 792234353Sdim return Value >= 0 && Value < 4; 793234353Sdim } 794224145Sdim bool isImm0_7() const { 795234353Sdim if (!isImm()) return false; 796224145Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 797224145Sdim if (!CE) return false; 798224145Sdim int64_t Value = CE->getValue(); 799224145Sdim return Value >= 0 && Value < 8; 800224145Sdim } 801224145Sdim bool isImm0_15() const { 802234353Sdim if (!isImm()) return false; 803224145Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 804224145Sdim if (!CE) return false; 805224145Sdim int64_t Value = CE->getValue(); 806224145Sdim return Value >= 0 && Value < 16; 807224145Sdim } 808226633Sdim bool isImm0_31() const { 809234353Sdim if (!isImm()) return false; 810226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 811226633Sdim if (!CE) return false; 812226633Sdim int64_t Value = CE->getValue(); 813226633Sdim return Value >= 0 && Value < 32; 814226633Sdim } 815234353Sdim bool isImm0_63() const { 816234353Sdim if (!isImm()) return false; 817234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 818234353Sdim if (!CE) return false; 819234353Sdim int64_t Value = CE->getValue(); 820234353Sdim return Value >= 0 && Value < 64; 821234353Sdim } 822234353Sdim bool isImm8() const { 823234353Sdim if (!isImm()) return false; 824234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 825234353Sdim if (!CE) return false; 826234353Sdim int64_t Value = CE->getValue(); 827234353Sdim return Value == 8; 828234353Sdim } 829234353Sdim bool isImm16() const { 830234353Sdim if (!isImm()) return false; 831234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 832234353Sdim if (!CE) return false; 833234353Sdim int64_t Value = CE->getValue(); 834234353Sdim return Value == 16; 835234353Sdim } 836234353Sdim bool isImm32() const { 837234353Sdim if (!isImm()) return false; 838234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 839234353Sdim if (!CE) return false; 840234353Sdim int64_t Value = CE->getValue(); 841234353Sdim return Value == 32; 842234353Sdim } 843234353Sdim bool isShrImm8() const { 844234353Sdim if (!isImm()) return false; 845234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 846234353Sdim if (!CE) return false; 847234353Sdim int64_t Value = CE->getValue(); 848234353Sdim return Value > 0 && Value <= 8; 849234353Sdim } 850234353Sdim bool isShrImm16() const { 851234353Sdim if (!isImm()) return false; 852234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 853234353Sdim if (!CE) return false; 854234353Sdim int64_t Value = CE->getValue(); 855234353Sdim return Value > 0 && Value <= 16; 856234353Sdim } 857234353Sdim bool isShrImm32() const { 858234353Sdim if (!isImm()) return false; 859234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 860234353Sdim if (!CE) return false; 861234353Sdim int64_t Value = CE->getValue(); 862234353Sdim return Value > 0 && Value <= 32; 863234353Sdim } 864234353Sdim bool isShrImm64() const { 865234353Sdim if (!isImm()) return false; 866234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 867234353Sdim if (!CE) return false; 868234353Sdim int64_t Value = CE->getValue(); 869234353Sdim return Value > 0 && Value <= 64; 870234353Sdim } 871234353Sdim bool isImm1_7() const { 872234353Sdim if (!isImm()) return false; 873234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 874234353Sdim if (!CE) return false; 875234353Sdim int64_t Value = CE->getValue(); 876234353Sdim return Value > 0 && Value < 8; 877234353Sdim } 878234353Sdim bool isImm1_15() const { 879234353Sdim if (!isImm()) return false; 880234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 881234353Sdim if (!CE) return false; 882234353Sdim int64_t Value = CE->getValue(); 883234353Sdim return Value > 0 && Value < 16; 884234353Sdim } 885234353Sdim bool isImm1_31() const { 886234353Sdim if (!isImm()) return false; 887234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 888234353Sdim if (!CE) return false; 889234353Sdim int64_t Value = CE->getValue(); 890234353Sdim return Value > 0 && Value < 32; 891234353Sdim } 892226633Sdim bool isImm1_16() const { 893234353Sdim if (!isImm()) return false; 894226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 895226633Sdim if (!CE) return false; 896226633Sdim int64_t Value = CE->getValue(); 897226633Sdim return Value > 0 && Value < 17; 898226633Sdim } 899226633Sdim bool isImm1_32() const { 900234353Sdim if (!isImm()) return false; 901226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 902226633Sdim if (!CE) return false; 903226633Sdim int64_t Value = CE->getValue(); 904226633Sdim return Value > 0 && Value < 33; 905226633Sdim } 906234353Sdim bool isImm0_32() const { 907234353Sdim if (!isImm()) return false; 908234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 909234353Sdim if (!CE) return false; 910234353Sdim int64_t Value = CE->getValue(); 911234353Sdim return Value >= 0 && Value < 33; 912234353Sdim } 913224145Sdim bool isImm0_65535() const { 914234353Sdim if (!isImm()) return false; 915224145Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 916224145Sdim if (!CE) return false; 917224145Sdim int64_t Value = CE->getValue(); 918224145Sdim return Value >= 0 && Value < 65536; 919224145Sdim } 920261991Sdim bool isImm256_65535Expr() const { 921261991Sdim if (!isImm()) return false; 922261991Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 923261991Sdim // If it's not a constant expression, it'll generate a fixup and be 924261991Sdim // handled later. 925261991Sdim if (!CE) return true; 926261991Sdim int64_t Value = CE->getValue(); 927261991Sdim return Value >= 256 && Value < 65536; 928261991Sdim } 929226633Sdim bool isImm0_65535Expr() const { 930234353Sdim if (!isImm()) return false; 931224145Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 932226633Sdim // If it's not a constant expression, it'll generate a fixup and be 933226633Sdim // handled later. 934226633Sdim if (!CE) return true; 935226633Sdim int64_t Value = CE->getValue(); 936226633Sdim return Value >= 0 && Value < 65536; 937226633Sdim } 938226633Sdim bool isImm24bit() const { 939234353Sdim if (!isImm()) return false; 940226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 941224145Sdim if (!CE) return false; 942224145Sdim int64_t Value = CE->getValue(); 943226633Sdim return Value >= 0 && Value <= 0xffffff; 944224145Sdim } 945226633Sdim bool isImmThumbSR() const { 946234353Sdim if (!isImm()) return false; 947226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 948226633Sdim if (!CE) return false; 949226633Sdim int64_t Value = CE->getValue(); 950226633Sdim return Value > 0 && Value < 33; 951226633Sdim } 952226633Sdim bool isPKHLSLImm() const { 953234353Sdim if (!isImm()) return false; 954226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 955221345Sdim if (!CE) return false; 956221345Sdim int64_t Value = CE->getValue(); 957226633Sdim return Value >= 0 && Value < 32; 958226633Sdim } 959226633Sdim bool isPKHASRImm() const { 960234353Sdim if (!isImm()) return false; 961226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 962226633Sdim if (!CE) return false; 963226633Sdim int64_t Value = CE->getValue(); 964226633Sdim return Value > 0 && Value <= 32; 965221345Sdim } 966239462Sdim bool isAdrLabel() const { 967239462Sdim // If we have an immediate that's not a constant, treat it as a label 968280031Sdim // reference needing a fixup. 969280031Sdim if (isImm() && !isa<MCConstantExpr>(getImm())) 970280031Sdim return true; 971280031Sdim 972280031Sdim // If it is a constant, it must fit into a modified immediate encoding. 973234353Sdim if (!isImm()) return false; 974226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 975226633Sdim if (!CE) return false; 976226633Sdim int64_t Value = CE->getValue(); 977280031Sdim return (ARM_AM::getSOImmVal(Value) != -1 || 978288943Sdim ARM_AM::getSOImmVal(-Value) != -1); 979226633Sdim } 980226633Sdim bool isT2SOImm() const { 981234353Sdim if (!isImm()) return false; 982226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 983221345Sdim if (!CE) return false; 984221345Sdim int64_t Value = CE->getValue(); 985226633Sdim return ARM_AM::getT2SOImmVal(Value) != -1; 986221345Sdim } 987234353Sdim bool isT2SOImmNot() const { 988234353Sdim if (!isImm()) return false; 989234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 990234353Sdim if (!CE) return false; 991234353Sdim int64_t Value = CE->getValue(); 992261991Sdim return ARM_AM::getT2SOImmVal(Value) == -1 && 993261991Sdim ARM_AM::getT2SOImmVal(~Value) != -1; 994234353Sdim } 995234353Sdim bool isT2SOImmNeg() const { 996234353Sdim if (!isImm()) return false; 997234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 998234353Sdim if (!CE) return false; 999234353Sdim int64_t Value = CE->getValue(); 1000234353Sdim // Only use this when not representable as a plain so_imm. 1001234353Sdim return ARM_AM::getT2SOImmVal(Value) == -1 && 1002234353Sdim ARM_AM::getT2SOImmVal(-Value) != -1; 1003234353Sdim } 1004226633Sdim bool isSetEndImm() const { 1005234353Sdim if (!isImm()) return false; 1006226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1007218893Sdim if (!CE) return false; 1008218893Sdim int64_t Value = CE->getValue(); 1009226633Sdim return Value == 1 || Value == 0; 1010218893Sdim } 1011276479Sdim bool isReg() const override { return Kind == k_Register; } 1012226633Sdim bool isRegList() const { return Kind == k_RegisterList; } 1013226633Sdim bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 1014226633Sdim bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 1015276479Sdim bool isToken() const override { return Kind == k_Token; } 1016226633Sdim bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 1017261991Sdim bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } 1018276479Sdim bool isMem() const override { return Kind == k_Memory; } 1019226633Sdim bool isShifterImm() const { return Kind == k_ShifterImmediate; } 1020226633Sdim bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 1021226633Sdim bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 1022226633Sdim bool isRotImm() const { return Kind == k_RotateImmediate; } 1023280031Sdim bool isModImm() const { return Kind == k_ModifiedImmediate; } 1024280031Sdim bool isModImmNot() const { 1025280031Sdim if (!isImm()) return false; 1026280031Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1027280031Sdim if (!CE) return false; 1028280031Sdim int64_t Value = CE->getValue(); 1029280031Sdim return ARM_AM::getSOImmVal(~Value) != -1; 1030280031Sdim } 1031280031Sdim bool isModImmNeg() const { 1032280031Sdim if (!isImm()) return false; 1033280031Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1034280031Sdim if (!CE) return false; 1035280031Sdim int64_t Value = CE->getValue(); 1036280031Sdim return ARM_AM::getSOImmVal(Value) == -1 && 1037280031Sdim ARM_AM::getSOImmVal(-Value) != -1; 1038280031Sdim } 1039226633Sdim bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 1040226633Sdim bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 1041226633Sdim bool isPostIdxReg() const { 1042234353Sdim return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 1043226633Sdim } 1044276479Sdim bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const { 1045243830Sdim if (!isMem()) 1046221345Sdim return false; 1047226633Sdim // No offset of any kind. 1048276479Sdim return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && 1049276479Sdim (alignOK || Memory.Alignment == Alignment); 1050226633Sdim } 1051234353Sdim bool isMemPCRelImm12() const { 1052243830Sdim if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1053234353Sdim return false; 1054234353Sdim // Base register must be PC. 1055234353Sdim if (Memory.BaseRegNum != ARM::PC) 1056234353Sdim return false; 1057234353Sdim // Immediate offset in range [-4095, 4095]. 1058234353Sdim if (!Memory.OffsetImm) return true; 1059234353Sdim int64_t Val = Memory.OffsetImm->getValue(); 1060234353Sdim return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1061234353Sdim } 1062226633Sdim bool isAlignedMemory() const { 1063226633Sdim return isMemNoOffset(true); 1064226633Sdim } 1065276479Sdim bool isAlignedMemoryNone() const { 1066276479Sdim return isMemNoOffset(false, 0); 1067276479Sdim } 1068276479Sdim bool isDupAlignedMemoryNone() const { 1069276479Sdim return isMemNoOffset(false, 0); 1070276479Sdim } 1071276479Sdim bool isAlignedMemory16() const { 1072276479Sdim if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. 1073276479Sdim return true; 1074276479Sdim return isMemNoOffset(false, 0); 1075276479Sdim } 1076276479Sdim bool isDupAlignedMemory16() const { 1077276479Sdim if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. 1078276479Sdim return true; 1079276479Sdim return isMemNoOffset(false, 0); 1080276479Sdim } 1081276479Sdim bool isAlignedMemory32() const { 1082276479Sdim if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. 1083276479Sdim return true; 1084276479Sdim return isMemNoOffset(false, 0); 1085276479Sdim } 1086276479Sdim bool isDupAlignedMemory32() const { 1087276479Sdim if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. 1088276479Sdim return true; 1089276479Sdim return isMemNoOffset(false, 0); 1090276479Sdim } 1091276479Sdim bool isAlignedMemory64() const { 1092276479Sdim if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1093276479Sdim return true; 1094276479Sdim return isMemNoOffset(false, 0); 1095276479Sdim } 1096276479Sdim bool isDupAlignedMemory64() const { 1097276479Sdim if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1098276479Sdim return true; 1099276479Sdim return isMemNoOffset(false, 0); 1100276479Sdim } 1101276479Sdim bool isAlignedMemory64or128() const { 1102276479Sdim if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1103276479Sdim return true; 1104276479Sdim if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1105276479Sdim return true; 1106276479Sdim return isMemNoOffset(false, 0); 1107276479Sdim } 1108276479Sdim bool isDupAlignedMemory64or128() const { 1109276479Sdim if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1110276479Sdim return true; 1111276479Sdim if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1112276479Sdim return true; 1113276479Sdim return isMemNoOffset(false, 0); 1114276479Sdim } 1115276479Sdim bool isAlignedMemory64or128or256() const { 1116276479Sdim if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1117276479Sdim return true; 1118276479Sdim if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1119276479Sdim return true; 1120276479Sdim if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32. 1121276479Sdim return true; 1122276479Sdim return isMemNoOffset(false, 0); 1123276479Sdim } 1124226633Sdim bool isAddrMode2() const { 1125243830Sdim if (!isMem() || Memory.Alignment != 0) return false; 1126226633Sdim // Check for register offset. 1127226633Sdim if (Memory.OffsetRegNum) return true; 1128226633Sdim // Immediate offset in range [-4095, 4095]. 1129226633Sdim if (!Memory.OffsetImm) return true; 1130226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1131226633Sdim return Val > -4096 && Val < 4096; 1132226633Sdim } 1133226633Sdim bool isAM2OffsetImm() const { 1134234353Sdim if (!isImm()) return false; 1135226633Sdim // Immediate offset in range [-4095, 4095]. 1136226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1137221345Sdim if (!CE) return false; 1138226633Sdim int64_t Val = CE->getValue(); 1139261991Sdim return (Val == INT32_MIN) || (Val > -4096 && Val < 4096); 1140226633Sdim } 1141226633Sdim bool isAddrMode3() const { 1142234353Sdim // If we have an immediate that's not a constant, treat it as a label 1143234353Sdim // reference needing a fixup. If it is a constant, it's something else 1144234353Sdim // and we reject it. 1145234353Sdim if (isImm() && !isa<MCConstantExpr>(getImm())) 1146234353Sdim return true; 1147243830Sdim if (!isMem() || Memory.Alignment != 0) return false; 1148226633Sdim // No shifts are legal for AM3. 1149226633Sdim if (Memory.ShiftType != ARM_AM::no_shift) return false; 1150226633Sdim // Check for register offset. 1151226633Sdim if (Memory.OffsetRegNum) return true; 1152226633Sdim // Immediate offset in range [-255, 255]. 1153226633Sdim if (!Memory.OffsetImm) return true; 1154226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1155239462Sdim // The #-0 offset is encoded as INT32_MIN, and we have to check 1156239462Sdim // for this too. 1157239462Sdim return (Val > -256 && Val < 256) || Val == INT32_MIN; 1158226633Sdim } 1159226633Sdim bool isAM3Offset() const { 1160226633Sdim if (Kind != k_Immediate && Kind != k_PostIndexRegister) 1161221345Sdim return false; 1162226633Sdim if (Kind == k_PostIndexRegister) 1163226633Sdim return PostIdxReg.ShiftTy == ARM_AM::no_shift; 1164226633Sdim // Immediate offset in range [-255, 255]. 1165226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1166226633Sdim if (!CE) return false; 1167226633Sdim int64_t Val = CE->getValue(); 1168226633Sdim // Special case, #-0 is INT32_MIN. 1169226633Sdim return (Val > -256 && Val < 256) || Val == INT32_MIN; 1170226633Sdim } 1171226633Sdim bool isAddrMode5() const { 1172234353Sdim // If we have an immediate that's not a constant, treat it as a label 1173234353Sdim // reference needing a fixup. If it is a constant, it's something else 1174234353Sdim // and we reject it. 1175234353Sdim if (isImm() && !isa<MCConstantExpr>(getImm())) 1176234353Sdim return true; 1177243830Sdim if (!isMem() || Memory.Alignment != 0) return false; 1178226633Sdim // Check for register offset. 1179226633Sdim if (Memory.OffsetRegNum) return false; 1180226633Sdim // Immediate offset in range [-1020, 1020] and a multiple of 4. 1181226633Sdim if (!Memory.OffsetImm) return true; 1182226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1183226633Sdim return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 1184234353Sdim Val == INT32_MIN; 1185226633Sdim } 1186226633Sdim bool isMemTBB() const { 1187243830Sdim if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1188226633Sdim Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1189226633Sdim return false; 1190221345Sdim return true; 1191221345Sdim } 1192226633Sdim bool isMemTBH() const { 1193243830Sdim if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1194226633Sdim Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 1195226633Sdim Memory.Alignment != 0 ) 1196218893Sdim return false; 1197218893Sdim return true; 1198218893Sdim } 1199226633Sdim bool isMemRegOffset() const { 1200243830Sdim if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) 1201218893Sdim return false; 1202226633Sdim return true; 1203226633Sdim } 1204226633Sdim bool isT2MemRegOffset() const { 1205243830Sdim if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1206226633Sdim Memory.Alignment != 0) 1207226633Sdim return false; 1208226633Sdim // Only lsl #{0, 1, 2, 3} allowed. 1209226633Sdim if (Memory.ShiftType == ARM_AM::no_shift) 1210226633Sdim return true; 1211226633Sdim if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 1212226633Sdim return false; 1213226633Sdim return true; 1214226633Sdim } 1215226633Sdim bool isMemThumbRR() const { 1216226633Sdim // Thumb reg+reg addressing is simple. Just two registers, a base and 1217226633Sdim // an offset. No shifts, negations or any other complicating factors. 1218243830Sdim if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1219226633Sdim Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1220226633Sdim return false; 1221226633Sdim return isARMLowRegister(Memory.BaseRegNum) && 1222226633Sdim (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 1223226633Sdim } 1224226633Sdim bool isMemThumbRIs4() const { 1225243830Sdim if (!isMem() || Memory.OffsetRegNum != 0 || 1226226633Sdim !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1227226633Sdim return false; 1228226633Sdim // Immediate offset, multiple of 4 in range [0, 124]. 1229226633Sdim if (!Memory.OffsetImm) return true; 1230226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1231226633Sdim return Val >= 0 && Val <= 124 && (Val % 4) == 0; 1232226633Sdim } 1233226633Sdim bool isMemThumbRIs2() const { 1234243830Sdim if (!isMem() || Memory.OffsetRegNum != 0 || 1235226633Sdim !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1236226633Sdim return false; 1237226633Sdim // Immediate offset, multiple of 4 in range [0, 62]. 1238226633Sdim if (!Memory.OffsetImm) return true; 1239226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1240226633Sdim return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1241226633Sdim } 1242226633Sdim bool isMemThumbRIs1() const { 1243243830Sdim if (!isMem() || Memory.OffsetRegNum != 0 || 1244226633Sdim !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1245226633Sdim return false; 1246226633Sdim // Immediate offset in range [0, 31]. 1247226633Sdim if (!Memory.OffsetImm) return true; 1248226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1249226633Sdim return Val >= 0 && Val <= 31; 1250226633Sdim } 1251226633Sdim bool isMemThumbSPI() const { 1252243830Sdim if (!isMem() || Memory.OffsetRegNum != 0 || 1253226633Sdim Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1254226633Sdim return false; 1255226633Sdim // Immediate offset, multiple of 4 in range [0, 1020]. 1256226633Sdim if (!Memory.OffsetImm) return true; 1257226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1258226633Sdim return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1259226633Sdim } 1260226633Sdim bool isMemImm8s4Offset() const { 1261234353Sdim // If we have an immediate that's not a constant, treat it as a label 1262234353Sdim // reference needing a fixup. If it is a constant, it's something else 1263234353Sdim // and we reject it. 1264234353Sdim if (isImm() && !isa<MCConstantExpr>(getImm())) 1265234353Sdim return true; 1266243830Sdim if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1267226633Sdim return false; 1268226633Sdim // Immediate offset a multiple of 4 in range [-1020, 1020]. 1269226633Sdim if (!Memory.OffsetImm) return true; 1270226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1271239462Sdim // Special case, #-0 is INT32_MIN. 1272239462Sdim return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; 1273226633Sdim } 1274226633Sdim bool isMemImm0_1020s4Offset() const { 1275243830Sdim if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1276226633Sdim return false; 1277226633Sdim // Immediate offset a multiple of 4 in range [0, 1020]. 1278226633Sdim if (!Memory.OffsetImm) return true; 1279226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1280226633Sdim return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1281226633Sdim } 1282226633Sdim bool isMemImm8Offset() const { 1283243830Sdim if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1284226633Sdim return false; 1285234353Sdim // Base reg of PC isn't allowed for these encodings. 1286234353Sdim if (Memory.BaseRegNum == ARM::PC) return false; 1287226633Sdim // Immediate offset in range [-255, 255]. 1288226633Sdim if (!Memory.OffsetImm) return true; 1289226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1290226633Sdim return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1291226633Sdim } 1292226633Sdim bool isMemPosImm8Offset() const { 1293243830Sdim if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1294226633Sdim return false; 1295226633Sdim // Immediate offset in range [0, 255]. 1296226633Sdim if (!Memory.OffsetImm) return true; 1297226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1298226633Sdim return Val >= 0 && Val < 256; 1299226633Sdim } 1300226633Sdim bool isMemNegImm8Offset() const { 1301243830Sdim if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1302226633Sdim return false; 1303234353Sdim // Base reg of PC isn't allowed for these encodings. 1304234353Sdim if (Memory.BaseRegNum == ARM::PC) return false; 1305226633Sdim // Immediate offset in range [-255, -1]. 1306234353Sdim if (!Memory.OffsetImm) return false; 1307226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1308234353Sdim return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1309226633Sdim } 1310226633Sdim bool isMemUImm12Offset() const { 1311243830Sdim if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1312226633Sdim return false; 1313226633Sdim // Immediate offset in range [0, 4095]. 1314226633Sdim if (!Memory.OffsetImm) return true; 1315226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1316226633Sdim return (Val >= 0 && Val < 4096); 1317226633Sdim } 1318226633Sdim bool isMemImm12Offset() const { 1319226633Sdim // If we have an immediate that's not a constant, treat it as a label 1320226633Sdim // reference needing a fixup. If it is a constant, it's something else 1321226633Sdim // and we reject it. 1322234353Sdim if (isImm() && !isa<MCConstantExpr>(getImm())) 1323226633Sdim return true; 1324226633Sdim 1325243830Sdim if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1326226633Sdim return false; 1327226633Sdim // Immediate offset in range [-4095, 4095]. 1328226633Sdim if (!Memory.OffsetImm) return true; 1329226633Sdim int64_t Val = Memory.OffsetImm->getValue(); 1330226633Sdim return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1331226633Sdim } 1332226633Sdim bool isPostIdxImm8() const { 1333234353Sdim if (!isImm()) return false; 1334226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1335218893Sdim if (!CE) return false; 1336226633Sdim int64_t Val = CE->getValue(); 1337226633Sdim return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1338226633Sdim } 1339226633Sdim bool isPostIdxImm8s4() const { 1340234353Sdim if (!isImm()) return false; 1341226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1342226633Sdim if (!CE) return false; 1343226633Sdim int64_t Val = CE->getValue(); 1344226633Sdim return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1345226633Sdim (Val == INT32_MIN); 1346226633Sdim } 1347218893Sdim 1348226633Sdim bool isMSRMask() const { return Kind == k_MSRMask; } 1349280031Sdim bool isBankedReg() const { return Kind == k_BankedReg; } 1350226633Sdim bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1351226633Sdim 1352234353Sdim // NEON operands. 1353234353Sdim bool isSingleSpacedVectorList() const { 1354234353Sdim return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1355234353Sdim } 1356234353Sdim bool isDoubleSpacedVectorList() const { 1357234353Sdim return Kind == k_VectorList && VectorList.isDoubleSpaced; 1358234353Sdim } 1359234353Sdim bool isVecListOneD() const { 1360234353Sdim if (!isSingleSpacedVectorList()) return false; 1361234353Sdim return VectorList.Count == 1; 1362234353Sdim } 1363234353Sdim 1364234353Sdim bool isVecListDPair() const { 1365234353Sdim if (!isSingleSpacedVectorList()) return false; 1366234353Sdim return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1367234353Sdim .contains(VectorList.RegNum)); 1368234353Sdim } 1369234353Sdim 1370234353Sdim bool isVecListThreeD() const { 1371234353Sdim if (!isSingleSpacedVectorList()) return false; 1372234353Sdim return VectorList.Count == 3; 1373234353Sdim } 1374234353Sdim 1375234353Sdim bool isVecListFourD() const { 1376234353Sdim if (!isSingleSpacedVectorList()) return false; 1377234353Sdim return VectorList.Count == 4; 1378234353Sdim } 1379234353Sdim 1380234353Sdim bool isVecListDPairSpaced() const { 1381276479Sdim if (Kind != k_VectorList) return false; 1382234353Sdim if (isSingleSpacedVectorList()) return false; 1383234353Sdim return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1384234353Sdim .contains(VectorList.RegNum)); 1385234353Sdim } 1386234353Sdim 1387234353Sdim bool isVecListThreeQ() const { 1388234353Sdim if (!isDoubleSpacedVectorList()) return false; 1389234353Sdim return VectorList.Count == 3; 1390234353Sdim } 1391234353Sdim 1392234353Sdim bool isVecListFourQ() const { 1393234353Sdim if (!isDoubleSpacedVectorList()) return false; 1394234353Sdim return VectorList.Count == 4; 1395234353Sdim } 1396234353Sdim 1397234353Sdim bool isSingleSpacedVectorAllLanes() const { 1398234353Sdim return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1399234353Sdim } 1400234353Sdim bool isDoubleSpacedVectorAllLanes() const { 1401234353Sdim return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1402234353Sdim } 1403234353Sdim bool isVecListOneDAllLanes() const { 1404234353Sdim if (!isSingleSpacedVectorAllLanes()) return false; 1405234353Sdim return VectorList.Count == 1; 1406234353Sdim } 1407234353Sdim 1408234353Sdim bool isVecListDPairAllLanes() const { 1409234353Sdim if (!isSingleSpacedVectorAllLanes()) return false; 1410234353Sdim return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1411234353Sdim .contains(VectorList.RegNum)); 1412234353Sdim } 1413234353Sdim 1414234353Sdim bool isVecListDPairSpacedAllLanes() const { 1415234353Sdim if (!isDoubleSpacedVectorAllLanes()) return false; 1416234353Sdim return VectorList.Count == 2; 1417234353Sdim } 1418234353Sdim 1419234353Sdim bool isVecListThreeDAllLanes() const { 1420234353Sdim if (!isSingleSpacedVectorAllLanes()) return false; 1421234353Sdim return VectorList.Count == 3; 1422234353Sdim } 1423234353Sdim 1424234353Sdim bool isVecListThreeQAllLanes() const { 1425234353Sdim if (!isDoubleSpacedVectorAllLanes()) return false; 1426234353Sdim return VectorList.Count == 3; 1427234353Sdim } 1428234353Sdim 1429234353Sdim bool isVecListFourDAllLanes() const { 1430234353Sdim if (!isSingleSpacedVectorAllLanes()) return false; 1431234353Sdim return VectorList.Count == 4; 1432234353Sdim } 1433234353Sdim 1434234353Sdim bool isVecListFourQAllLanes() const { 1435234353Sdim if (!isDoubleSpacedVectorAllLanes()) return false; 1436234353Sdim return VectorList.Count == 4; 1437234353Sdim } 1438234353Sdim 1439234353Sdim bool isSingleSpacedVectorIndexed() const { 1440234353Sdim return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1441234353Sdim } 1442234353Sdim bool isDoubleSpacedVectorIndexed() const { 1443234353Sdim return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1444234353Sdim } 1445234353Sdim bool isVecListOneDByteIndexed() const { 1446234353Sdim if (!isSingleSpacedVectorIndexed()) return false; 1447234353Sdim return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1448234353Sdim } 1449234353Sdim 1450234353Sdim bool isVecListOneDHWordIndexed() const { 1451234353Sdim if (!isSingleSpacedVectorIndexed()) return false; 1452234353Sdim return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1453234353Sdim } 1454234353Sdim 1455234353Sdim bool isVecListOneDWordIndexed() const { 1456234353Sdim if (!isSingleSpacedVectorIndexed()) return false; 1457234353Sdim return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1458234353Sdim } 1459234353Sdim 1460234353Sdim bool isVecListTwoDByteIndexed() const { 1461234353Sdim if (!isSingleSpacedVectorIndexed()) return false; 1462234353Sdim return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1463234353Sdim } 1464234353Sdim 1465234353Sdim bool isVecListTwoDHWordIndexed() const { 1466234353Sdim if (!isSingleSpacedVectorIndexed()) return false; 1467234353Sdim return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1468234353Sdim } 1469234353Sdim 1470234353Sdim bool isVecListTwoQWordIndexed() const { 1471234353Sdim if (!isDoubleSpacedVectorIndexed()) return false; 1472234353Sdim return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1473234353Sdim } 1474234353Sdim 1475234353Sdim bool isVecListTwoQHWordIndexed() const { 1476234353Sdim if (!isDoubleSpacedVectorIndexed()) return false; 1477234353Sdim return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1478234353Sdim } 1479234353Sdim 1480234353Sdim bool isVecListTwoDWordIndexed() const { 1481234353Sdim if (!isSingleSpacedVectorIndexed()) return false; 1482234353Sdim return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1483234353Sdim } 1484234353Sdim 1485234353Sdim bool isVecListThreeDByteIndexed() const { 1486234353Sdim if (!isSingleSpacedVectorIndexed()) return false; 1487234353Sdim return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1488234353Sdim } 1489234353Sdim 1490234353Sdim bool isVecListThreeDHWordIndexed() const { 1491234353Sdim if (!isSingleSpacedVectorIndexed()) return false; 1492234353Sdim return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1493234353Sdim } 1494234353Sdim 1495234353Sdim bool isVecListThreeQWordIndexed() const { 1496234353Sdim if (!isDoubleSpacedVectorIndexed()) return false; 1497234353Sdim return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1498234353Sdim } 1499234353Sdim 1500234353Sdim bool isVecListThreeQHWordIndexed() const { 1501234353Sdim if (!isDoubleSpacedVectorIndexed()) return false; 1502234353Sdim return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1503234353Sdim } 1504234353Sdim 1505234353Sdim bool isVecListThreeDWordIndexed() const { 1506234353Sdim if (!isSingleSpacedVectorIndexed()) return false; 1507234353Sdim return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1508234353Sdim } 1509234353Sdim 1510234353Sdim bool isVecListFourDByteIndexed() const { 1511234353Sdim if (!isSingleSpacedVectorIndexed()) return false; 1512234353Sdim return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1513234353Sdim } 1514234353Sdim 1515234353Sdim bool isVecListFourDHWordIndexed() const { 1516234353Sdim if (!isSingleSpacedVectorIndexed()) return false; 1517234353Sdim return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1518234353Sdim } 1519234353Sdim 1520234353Sdim bool isVecListFourQWordIndexed() const { 1521234353Sdim if (!isDoubleSpacedVectorIndexed()) return false; 1522234353Sdim return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1523234353Sdim } 1524234353Sdim 1525234353Sdim bool isVecListFourQHWordIndexed() const { 1526234353Sdim if (!isDoubleSpacedVectorIndexed()) return false; 1527234353Sdim return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1528234353Sdim } 1529234353Sdim 1530234353Sdim bool isVecListFourDWordIndexed() const { 1531234353Sdim if (!isSingleSpacedVectorIndexed()) return false; 1532234353Sdim return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1533234353Sdim } 1534234353Sdim 1535226633Sdim bool isVectorIndex8() const { 1536226633Sdim if (Kind != k_VectorIndex) return false; 1537226633Sdim return VectorIndex.Val < 8; 1538218893Sdim } 1539226633Sdim bool isVectorIndex16() const { 1540226633Sdim if (Kind != k_VectorIndex) return false; 1541226633Sdim return VectorIndex.Val < 4; 1542226633Sdim } 1543226633Sdim bool isVectorIndex32() const { 1544226633Sdim if (Kind != k_VectorIndex) return false; 1545226633Sdim return VectorIndex.Val < 2; 1546226633Sdim } 1547218893Sdim 1548234353Sdim bool isNEONi8splat() const { 1549234353Sdim if (!isImm()) return false; 1550234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1551234353Sdim // Must be a constant. 1552234353Sdim if (!CE) return false; 1553234353Sdim int64_t Value = CE->getValue(); 1554234353Sdim // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1555234353Sdim // value. 1556234353Sdim return Value >= 0 && Value < 256; 1557234353Sdim } 1558226633Sdim 1559234353Sdim bool isNEONi16splat() const { 1560276479Sdim if (isNEONByteReplicate(2)) 1561276479Sdim return false; // Leave that for bytes replication and forbid by default. 1562276479Sdim if (!isImm()) 1563276479Sdim return false; 1564234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1565234353Sdim // Must be a constant. 1566234353Sdim if (!CE) return false; 1567280031Sdim unsigned Value = CE->getValue(); 1568280031Sdim return ARM_AM::isNEONi16splat(Value); 1569234353Sdim } 1570226633Sdim 1571280031Sdim bool isNEONi16splatNot() const { 1572280031Sdim if (!isImm()) 1573280031Sdim return false; 1574280031Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1575280031Sdim // Must be a constant. 1576280031Sdim if (!CE) return false; 1577280031Sdim unsigned Value = CE->getValue(); 1578280031Sdim return ARM_AM::isNEONi16splat(~Value & 0xffff); 1579280031Sdim } 1580280031Sdim 1581234353Sdim bool isNEONi32splat() const { 1582276479Sdim if (isNEONByteReplicate(4)) 1583276479Sdim return false; // Leave that for bytes replication and forbid by default. 1584276479Sdim if (!isImm()) 1585276479Sdim return false; 1586234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1587234353Sdim // Must be a constant. 1588234353Sdim if (!CE) return false; 1589280031Sdim unsigned Value = CE->getValue(); 1590280031Sdim return ARM_AM::isNEONi32splat(Value); 1591234353Sdim } 1592234353Sdim 1593280031Sdim bool isNEONi32splatNot() const { 1594280031Sdim if (!isImm()) 1595280031Sdim return false; 1596280031Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1597280031Sdim // Must be a constant. 1598280031Sdim if (!CE) return false; 1599280031Sdim unsigned Value = CE->getValue(); 1600280031Sdim return ARM_AM::isNEONi32splat(~Value); 1601280031Sdim } 1602280031Sdim 1603276479Sdim bool isNEONByteReplicate(unsigned NumBytes) const { 1604276479Sdim if (!isImm()) 1605276479Sdim return false; 1606276479Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1607276479Sdim // Must be a constant. 1608276479Sdim if (!CE) 1609276479Sdim return false; 1610276479Sdim int64_t Value = CE->getValue(); 1611276479Sdim if (!Value) 1612276479Sdim return false; // Don't bother with zero. 1613276479Sdim 1614276479Sdim unsigned char B = Value & 0xff; 1615276479Sdim for (unsigned i = 1; i < NumBytes; ++i) { 1616276479Sdim Value >>= 8; 1617276479Sdim if ((Value & 0xff) != B) 1618276479Sdim return false; 1619276479Sdim } 1620276479Sdim return true; 1621276479Sdim } 1622276479Sdim bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); } 1623276479Sdim bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); } 1624234353Sdim bool isNEONi32vmov() const { 1625276479Sdim if (isNEONByteReplicate(4)) 1626276479Sdim return false; // Let it to be classified as byte-replicate case. 1627276479Sdim if (!isImm()) 1628276479Sdim return false; 1629234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1630234353Sdim // Must be a constant. 1631276479Sdim if (!CE) 1632276479Sdim return false; 1633234353Sdim int64_t Value = CE->getValue(); 1634234353Sdim // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1635234353Sdim // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1636280031Sdim // FIXME: This is probably wrong and a copy and paste from previous example 1637234353Sdim return (Value >= 0 && Value < 256) || 1638234353Sdim (Value >= 0x0100 && Value <= 0xff00) || 1639234353Sdim (Value >= 0x010000 && Value <= 0xff0000) || 1640234353Sdim (Value >= 0x01000000 && Value <= 0xff000000) || 1641234353Sdim (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1642234353Sdim (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1643234353Sdim } 1644234353Sdim bool isNEONi32vmovNeg() const { 1645234353Sdim if (!isImm()) return false; 1646234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1647234353Sdim // Must be a constant. 1648234353Sdim if (!CE) return false; 1649234353Sdim int64_t Value = ~CE->getValue(); 1650234353Sdim // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1651234353Sdim // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1652280031Sdim // FIXME: This is probably wrong and a copy and paste from previous example 1653234353Sdim return (Value >= 0 && Value < 256) || 1654234353Sdim (Value >= 0x0100 && Value <= 0xff00) || 1655234353Sdim (Value >= 0x010000 && Value <= 0xff0000) || 1656234353Sdim (Value >= 0x01000000 && Value <= 0xff000000) || 1657234353Sdim (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1658234353Sdim (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1659234353Sdim } 1660234353Sdim 1661234353Sdim bool isNEONi64splat() const { 1662234353Sdim if (!isImm()) return false; 1663234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1664234353Sdim // Must be a constant. 1665234353Sdim if (!CE) return false; 1666234353Sdim uint64_t Value = CE->getValue(); 1667234353Sdim // i64 value with each byte being either 0 or 0xff. 1668234353Sdim for (unsigned i = 0; i < 8; ++i) 1669234353Sdim if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1670234353Sdim return true; 1671234353Sdim } 1672234353Sdim 1673212904Sdim void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1674218893Sdim // Add as immediates when possible. Null MCExpr = 0. 1675276479Sdim if (!Expr) 1676288943Sdim Inst.addOperand(MCOperand::createImm(0)); 1677218893Sdim else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1678288943Sdim Inst.addOperand(MCOperand::createImm(CE->getValue())); 1679212904Sdim else 1680288943Sdim Inst.addOperand(MCOperand::createExpr(Expr)); 1681212904Sdim } 1682212904Sdim 1683212904Sdim void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1684212904Sdim assert(N == 2 && "Invalid number of operands!"); 1685288943Sdim Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); 1686218893Sdim unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1687288943Sdim Inst.addOperand(MCOperand::createReg(RegNum)); 1688212904Sdim } 1689212904Sdim 1690218893Sdim void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1691218893Sdim assert(N == 1 && "Invalid number of operands!"); 1692288943Sdim Inst.addOperand(MCOperand::createImm(getCoproc())); 1693218893Sdim } 1694218893Sdim 1695218893Sdim void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1696218893Sdim assert(N == 1 && "Invalid number of operands!"); 1697288943Sdim Inst.addOperand(MCOperand::createImm(getCoproc())); 1698218893Sdim } 1699218893Sdim 1700226633Sdim void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1701226633Sdim assert(N == 1 && "Invalid number of operands!"); 1702288943Sdim Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); 1703226633Sdim } 1704226633Sdim 1705226633Sdim void addITMaskOperands(MCInst &Inst, unsigned N) const { 1706226633Sdim assert(N == 1 && "Invalid number of operands!"); 1707288943Sdim Inst.addOperand(MCOperand::createImm(ITMask.Mask)); 1708226633Sdim } 1709226633Sdim 1710226633Sdim void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1711226633Sdim assert(N == 1 && "Invalid number of operands!"); 1712288943Sdim Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); 1713226633Sdim } 1714226633Sdim 1715218893Sdim void addCCOutOperands(MCInst &Inst, unsigned N) const { 1716218893Sdim assert(N == 1 && "Invalid number of operands!"); 1717288943Sdim Inst.addOperand(MCOperand::createReg(getReg())); 1718218893Sdim } 1719218893Sdim 1720198090Srdivacky void addRegOperands(MCInst &Inst, unsigned N) const { 1721198090Srdivacky assert(N == 1 && "Invalid number of operands!"); 1722288943Sdim Inst.addOperand(MCOperand::createReg(getReg())); 1723198090Srdivacky } 1724198090Srdivacky 1725226633Sdim void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1726224145Sdim assert(N == 3 && "Invalid number of operands!"); 1727234353Sdim assert(isRegShiftedReg() && 1728276479Sdim "addRegShiftedRegOperands() on non-RegShiftedReg!"); 1729288943Sdim Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); 1730288943Sdim Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); 1731288943Sdim Inst.addOperand(MCOperand::createImm( 1732226633Sdim ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1733224145Sdim } 1734224145Sdim 1735226633Sdim void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1736226633Sdim assert(N == 2 && "Invalid number of operands!"); 1737234353Sdim assert(isRegShiftedImm() && 1738276479Sdim "addRegShiftedImmOperands() on non-RegShiftedImm!"); 1739288943Sdim Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); 1740239462Sdim // Shift of #32 is encoded as 0 where permitted 1741239462Sdim unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1742288943Sdim Inst.addOperand(MCOperand::createImm( 1743239462Sdim ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1744221345Sdim } 1745221345Sdim 1746226633Sdim void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1747226633Sdim assert(N == 1 && "Invalid number of operands!"); 1748288943Sdim Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) | 1749226633Sdim ShifterImm.Imm)); 1750226633Sdim } 1751226633Sdim 1752218893Sdim void addRegListOperands(MCInst &Inst, unsigned N) const { 1753218893Sdim assert(N == 1 && "Invalid number of operands!"); 1754218893Sdim const SmallVectorImpl<unsigned> &RegList = getRegList(); 1755218893Sdim for (SmallVectorImpl<unsigned>::const_iterator 1756218893Sdim I = RegList.begin(), E = RegList.end(); I != E; ++I) 1757288943Sdim Inst.addOperand(MCOperand::createReg(*I)); 1758218893Sdim } 1759218893Sdim 1760218893Sdim void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1761218893Sdim addRegListOperands(Inst, N); 1762218893Sdim } 1763218893Sdim 1764218893Sdim void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1765218893Sdim addRegListOperands(Inst, N); 1766218893Sdim } 1767218893Sdim 1768226633Sdim void addRotImmOperands(MCInst &Inst, unsigned N) const { 1769226633Sdim assert(N == 1 && "Invalid number of operands!"); 1770226633Sdim // Encoded as val>>3. The printer handles display as 8, 16, 24. 1771288943Sdim Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3)); 1772226633Sdim } 1773226633Sdim 1774280031Sdim void addModImmOperands(MCInst &Inst, unsigned N) const { 1775280031Sdim assert(N == 1 && "Invalid number of operands!"); 1776280031Sdim 1777280031Sdim // Support for fixups (MCFixup) 1778280031Sdim if (isImm()) 1779280031Sdim return addImmOperands(Inst, N); 1780280031Sdim 1781288943Sdim Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7))); 1782280031Sdim } 1783280031Sdim 1784280031Sdim void addModImmNotOperands(MCInst &Inst, unsigned N) const { 1785280031Sdim assert(N == 1 && "Invalid number of operands!"); 1786280031Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1787280031Sdim uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue()); 1788288943Sdim Inst.addOperand(MCOperand::createImm(Enc)); 1789280031Sdim } 1790280031Sdim 1791280031Sdim void addModImmNegOperands(MCInst &Inst, unsigned N) const { 1792280031Sdim assert(N == 1 && "Invalid number of operands!"); 1793280031Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1794280031Sdim uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue()); 1795288943Sdim Inst.addOperand(MCOperand::createImm(Enc)); 1796280031Sdim } 1797280031Sdim 1798226633Sdim void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1799226633Sdim assert(N == 1 && "Invalid number of operands!"); 1800226633Sdim // Munge the lsb/width into a bitfield mask. 1801226633Sdim unsigned lsb = Bitfield.LSB; 1802226633Sdim unsigned width = Bitfield.Width; 1803226633Sdim // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1804226633Sdim uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1805226633Sdim (32 - (lsb + width))); 1806288943Sdim Inst.addOperand(MCOperand::createImm(Mask)); 1807226633Sdim } 1808226633Sdim 1809212904Sdim void addImmOperands(MCInst &Inst, unsigned N) const { 1810212904Sdim assert(N == 1 && "Invalid number of operands!"); 1811212904Sdim addExpr(Inst, getImm()); 1812212904Sdim } 1813212904Sdim 1814234353Sdim void addFBits16Operands(MCInst &Inst, unsigned N) const { 1815234353Sdim assert(N == 1 && "Invalid number of operands!"); 1816234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1817288943Sdim Inst.addOperand(MCOperand::createImm(16 - CE->getValue())); 1818234353Sdim } 1819234353Sdim 1820234353Sdim void addFBits32Operands(MCInst &Inst, unsigned N) const { 1821234353Sdim assert(N == 1 && "Invalid number of operands!"); 1822234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1823288943Sdim Inst.addOperand(MCOperand::createImm(32 - CE->getValue())); 1824234353Sdim } 1825234353Sdim 1826226633Sdim void addFPImmOperands(MCInst &Inst, unsigned N) const { 1827226633Sdim assert(N == 1 && "Invalid number of operands!"); 1828234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1829234353Sdim int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1830288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 1831226633Sdim } 1832226633Sdim 1833226633Sdim void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1834226633Sdim assert(N == 1 && "Invalid number of operands!"); 1835226633Sdim // FIXME: We really want to scale the value here, but the LDRD/STRD 1836226633Sdim // instruction don't encode operands that way yet. 1837226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1838288943Sdim Inst.addOperand(MCOperand::createImm(CE->getValue())); 1839226633Sdim } 1840226633Sdim 1841226633Sdim void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1842226633Sdim assert(N == 1 && "Invalid number of operands!"); 1843226633Sdim // The immediate is scaled by four in the encoding and is stored 1844226633Sdim // in the MCInst as such. Lop off the low two bits here. 1845226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1846288943Sdim Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); 1847226633Sdim } 1848226633Sdim 1849234353Sdim void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1850226633Sdim assert(N == 1 && "Invalid number of operands!"); 1851226633Sdim // The immediate is scaled by four in the encoding and is stored 1852226633Sdim // in the MCInst as such. Lop off the low two bits here. 1853226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1854288943Sdim Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4))); 1855226633Sdim } 1856226633Sdim 1857234353Sdim void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1858224145Sdim assert(N == 1 && "Invalid number of operands!"); 1859234353Sdim // The immediate is scaled by four in the encoding and is stored 1860234353Sdim // in the MCInst as such. Lop off the low two bits here. 1861234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1862288943Sdim Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); 1863224145Sdim } 1864224145Sdim 1865226633Sdim void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1866226633Sdim assert(N == 1 && "Invalid number of operands!"); 1867226633Sdim // The constant encodes as the immediate-1, and we store in the instruction 1868226633Sdim // the bits as encoded, so subtract off one here. 1869226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1870288943Sdim Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); 1871226633Sdim } 1872226633Sdim 1873226633Sdim void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1874226633Sdim assert(N == 1 && "Invalid number of operands!"); 1875226633Sdim // The constant encodes as the immediate-1, and we store in the instruction 1876226633Sdim // the bits as encoded, so subtract off one here. 1877226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1878288943Sdim Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); 1879226633Sdim } 1880226633Sdim 1881226633Sdim void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1882226633Sdim assert(N == 1 && "Invalid number of operands!"); 1883226633Sdim // The constant encodes as the immediate, except for 32, which encodes as 1884226633Sdim // zero. 1885226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1886226633Sdim unsigned Imm = CE->getValue(); 1887288943Sdim Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm))); 1888226633Sdim } 1889226633Sdim 1890226633Sdim void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1891226633Sdim assert(N == 1 && "Invalid number of operands!"); 1892226633Sdim // An ASR value of 32 encodes as 0, so that's how we want to add it to 1893226633Sdim // the instruction as well. 1894226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1895226633Sdim int Val = CE->getValue(); 1896288943Sdim Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val)); 1897226633Sdim } 1898226633Sdim 1899234353Sdim void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1900226633Sdim assert(N == 1 && "Invalid number of operands!"); 1901234353Sdim // The operand is actually a t2_so_imm, but we have its bitwise 1902234353Sdim // negation in the assembly source, so twiddle it here. 1903234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1904288943Sdim Inst.addOperand(MCOperand::createImm(~CE->getValue())); 1905226633Sdim } 1906226633Sdim 1907234353Sdim void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1908224145Sdim assert(N == 1 && "Invalid number of operands!"); 1909234353Sdim // The operand is actually a t2_so_imm, but we have its 1910234353Sdim // negation in the assembly source, so twiddle it here. 1911234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1912288943Sdim Inst.addOperand(MCOperand::createImm(-CE->getValue())); 1913224145Sdim } 1914224145Sdim 1915234353Sdim void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1916226633Sdim assert(N == 1 && "Invalid number of operands!"); 1917234353Sdim // The operand is actually an imm0_4095, but we have its 1918234353Sdim // negation in the assembly source, so twiddle it here. 1919234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1920288943Sdim Inst.addOperand(MCOperand::createImm(-CE->getValue())); 1921226633Sdim } 1922226633Sdim 1923261991Sdim void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { 1924261991Sdim if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) { 1925288943Sdim Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2)); 1926261991Sdim return; 1927261991Sdim } 1928261991Sdim 1929261991Sdim const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1930261991Sdim assert(SR && "Unknown value type!"); 1931288943Sdim Inst.addOperand(MCOperand::createExpr(SR)); 1932261991Sdim } 1933261991Sdim 1934261991Sdim void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { 1935261991Sdim assert(N == 1 && "Invalid number of operands!"); 1936261991Sdim if (isImm()) { 1937261991Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1938261991Sdim if (CE) { 1939288943Sdim Inst.addOperand(MCOperand::createImm(CE->getValue())); 1940261991Sdim return; 1941261991Sdim } 1942261991Sdim 1943261991Sdim const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1944261991Sdim assert(SR && "Unknown value type!"); 1945288943Sdim Inst.addOperand(MCOperand::createExpr(SR)); 1946261991Sdim return; 1947261991Sdim } 1948261991Sdim 1949261991Sdim assert(isMem() && "Unknown value type!"); 1950261991Sdim assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!"); 1951288943Sdim Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue())); 1952261991Sdim } 1953261991Sdim 1954218893Sdim void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1955218893Sdim assert(N == 1 && "Invalid number of operands!"); 1956288943Sdim Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt()))); 1957218893Sdim } 1958218893Sdim 1959261991Sdim void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { 1960261991Sdim assert(N == 1 && "Invalid number of operands!"); 1961288943Sdim Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt()))); 1962261991Sdim } 1963261991Sdim 1964226633Sdim void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1965226633Sdim assert(N == 1 && "Invalid number of operands!"); 1966288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 1967226633Sdim } 1968221345Sdim 1969234353Sdim void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 1970234353Sdim assert(N == 1 && "Invalid number of operands!"); 1971234353Sdim int32_t Imm = Memory.OffsetImm->getValue(); 1972288943Sdim Inst.addOperand(MCOperand::createImm(Imm)); 1973234353Sdim } 1974234353Sdim 1975239462Sdim void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 1976239462Sdim assert(N == 1 && "Invalid number of operands!"); 1977239462Sdim assert(isImm() && "Not an immediate!"); 1978239462Sdim 1979239462Sdim // If we have an immediate that's not a constant, treat it as a label 1980239462Sdim // reference needing a fixup. 1981239462Sdim if (!isa<MCConstantExpr>(getImm())) { 1982288943Sdim Inst.addOperand(MCOperand::createExpr(getImm())); 1983239462Sdim return; 1984239462Sdim } 1985239462Sdim 1986239462Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1987239462Sdim int Val = CE->getValue(); 1988288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 1989239462Sdim } 1990239462Sdim 1991226633Sdim void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 1992226633Sdim assert(N == 2 && "Invalid number of operands!"); 1993288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 1994288943Sdim Inst.addOperand(MCOperand::createImm(Memory.Alignment)); 1995221345Sdim } 1996221345Sdim 1997276479Sdim void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { 1998276479Sdim addAlignedMemoryOperands(Inst, N); 1999276479Sdim } 2000276479Sdim 2001276479Sdim void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { 2002276479Sdim addAlignedMemoryOperands(Inst, N); 2003276479Sdim } 2004276479Sdim 2005276479Sdim void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const { 2006276479Sdim addAlignedMemoryOperands(Inst, N); 2007276479Sdim } 2008276479Sdim 2009276479Sdim void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const { 2010276479Sdim addAlignedMemoryOperands(Inst, N); 2011276479Sdim } 2012276479Sdim 2013276479Sdim void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const { 2014276479Sdim addAlignedMemoryOperands(Inst, N); 2015276479Sdim } 2016276479Sdim 2017276479Sdim void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const { 2018276479Sdim addAlignedMemoryOperands(Inst, N); 2019276479Sdim } 2020276479Sdim 2021276479Sdim void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const { 2022276479Sdim addAlignedMemoryOperands(Inst, N); 2023276479Sdim } 2024276479Sdim 2025276479Sdim void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const { 2026276479Sdim addAlignedMemoryOperands(Inst, N); 2027276479Sdim } 2028276479Sdim 2029276479Sdim void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { 2030276479Sdim addAlignedMemoryOperands(Inst, N); 2031276479Sdim } 2032276479Sdim 2033276479Sdim void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { 2034276479Sdim addAlignedMemoryOperands(Inst, N); 2035276479Sdim } 2036276479Sdim 2037276479Sdim void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const { 2038276479Sdim addAlignedMemoryOperands(Inst, N); 2039276479Sdim } 2040276479Sdim 2041226633Sdim void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 2042226633Sdim assert(N == 3 && "Invalid number of operands!"); 2043226633Sdim int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2044226633Sdim if (!Memory.OffsetRegNum) { 2045226633Sdim ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2046226633Sdim // Special case for #-0 2047226633Sdim if (Val == INT32_MIN) Val = 0; 2048226633Sdim if (Val < 0) Val = -Val; 2049226633Sdim Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 2050226633Sdim } else { 2051226633Sdim // For register offset, we encode the shift type and negation flag 2052226633Sdim // here. 2053226633Sdim Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 2054226633Sdim Memory.ShiftImm, Memory.ShiftType); 2055226633Sdim } 2056288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2057288943Sdim Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2058288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2059226633Sdim } 2060221345Sdim 2061226633Sdim void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 2062226633Sdim assert(N == 2 && "Invalid number of operands!"); 2063226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2064226633Sdim assert(CE && "non-constant AM2OffsetImm operand!"); 2065226633Sdim int32_t Val = CE->getValue(); 2066226633Sdim ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2067226633Sdim // Special case for #-0 2068226633Sdim if (Val == INT32_MIN) Val = 0; 2069226633Sdim if (Val < 0) Val = -Val; 2070226633Sdim Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 2071288943Sdim Inst.addOperand(MCOperand::createReg(0)); 2072288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2073226633Sdim } 2074221345Sdim 2075226633Sdim void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 2076226633Sdim assert(N == 3 && "Invalid number of operands!"); 2077234353Sdim // If we have an immediate that's not a constant, treat it as a label 2078234353Sdim // reference needing a fixup. If it is a constant, it's something else 2079234353Sdim // and we reject it. 2080234353Sdim if (isImm()) { 2081288943Sdim Inst.addOperand(MCOperand::createExpr(getImm())); 2082288943Sdim Inst.addOperand(MCOperand::createReg(0)); 2083288943Sdim Inst.addOperand(MCOperand::createImm(0)); 2084234353Sdim return; 2085234353Sdim } 2086234353Sdim 2087226633Sdim int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2088226633Sdim if (!Memory.OffsetRegNum) { 2089226633Sdim ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2090226633Sdim // Special case for #-0 2091226633Sdim if (Val == INT32_MIN) Val = 0; 2092226633Sdim if (Val < 0) Val = -Val; 2093226633Sdim Val = ARM_AM::getAM3Opc(AddSub, Val); 2094226633Sdim } else { 2095226633Sdim // For register offset, we encode the shift type and negation flag 2096226633Sdim // here. 2097226633Sdim Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 2098226633Sdim } 2099288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2100288943Sdim Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2101288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2102226633Sdim } 2103221345Sdim 2104226633Sdim void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 2105226633Sdim assert(N == 2 && "Invalid number of operands!"); 2106226633Sdim if (Kind == k_PostIndexRegister) { 2107226633Sdim int32_t Val = 2108226633Sdim ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 2109288943Sdim Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); 2110288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2111221345Sdim return; 2112221345Sdim } 2113221345Sdim 2114226633Sdim // Constant offset. 2115226633Sdim const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 2116226633Sdim int32_t Val = CE->getValue(); 2117226633Sdim ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2118226633Sdim // Special case for #-0 2119226633Sdim if (Val == INT32_MIN) Val = 0; 2120226633Sdim if (Val < 0) Val = -Val; 2121226633Sdim Val = ARM_AM::getAM3Opc(AddSub, Val); 2122288943Sdim Inst.addOperand(MCOperand::createReg(0)); 2123288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2124226633Sdim } 2125221345Sdim 2126226633Sdim void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 2127226633Sdim assert(N == 2 && "Invalid number of operands!"); 2128234353Sdim // If we have an immediate that's not a constant, treat it as a label 2129234353Sdim // reference needing a fixup. If it is a constant, it's something else 2130234353Sdim // and we reject it. 2131234353Sdim if (isImm()) { 2132288943Sdim Inst.addOperand(MCOperand::createExpr(getImm())); 2133288943Sdim Inst.addOperand(MCOperand::createImm(0)); 2134234353Sdim return; 2135234353Sdim } 2136234353Sdim 2137226633Sdim // The lower two bits are always zero and as such are not encoded. 2138226633Sdim int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2139226633Sdim ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2140226633Sdim // Special case for #-0 2141226633Sdim if (Val == INT32_MIN) Val = 0; 2142226633Sdim if (Val < 0) Val = -Val; 2143226633Sdim Val = ARM_AM::getAM5Opc(AddSub, Val); 2144288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2145288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2146226633Sdim } 2147221345Sdim 2148226633Sdim void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 2149226633Sdim assert(N == 2 && "Invalid number of operands!"); 2150234353Sdim // If we have an immediate that's not a constant, treat it as a label 2151234353Sdim // reference needing a fixup. If it is a constant, it's something else 2152234353Sdim // and we reject it. 2153234353Sdim if (isImm()) { 2154288943Sdim Inst.addOperand(MCOperand::createExpr(getImm())); 2155288943Sdim Inst.addOperand(MCOperand::createImm(0)); 2156234353Sdim return; 2157234353Sdim } 2158234353Sdim 2159226633Sdim int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2160288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2161288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2162221345Sdim } 2163221345Sdim 2164226633Sdim void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 2165226633Sdim assert(N == 2 && "Invalid number of operands!"); 2166226633Sdim // The lower two bits are always zero and as such are not encoded. 2167226633Sdim int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2168288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2169288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2170226633Sdim } 2171221345Sdim 2172226633Sdim void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2173226633Sdim assert(N == 2 && "Invalid number of operands!"); 2174226633Sdim int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2175288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2176288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2177226633Sdim } 2178221345Sdim 2179226633Sdim void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2180226633Sdim addMemImm8OffsetOperands(Inst, N); 2181226633Sdim } 2182226633Sdim 2183226633Sdim void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2184226633Sdim addMemImm8OffsetOperands(Inst, N); 2185226633Sdim } 2186226633Sdim 2187226633Sdim void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2188226633Sdim assert(N == 2 && "Invalid number of operands!"); 2189226633Sdim // If this is an immediate, it's a label reference. 2190234353Sdim if (isImm()) { 2191226633Sdim addExpr(Inst, getImm()); 2192288943Sdim Inst.addOperand(MCOperand::createImm(0)); 2193221345Sdim return; 2194221345Sdim } 2195221345Sdim 2196226633Sdim // Otherwise, it's a normal memory reg+offset. 2197226633Sdim int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2198288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2199288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2200226633Sdim } 2201221345Sdim 2202226633Sdim void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2203226633Sdim assert(N == 2 && "Invalid number of operands!"); 2204226633Sdim // If this is an immediate, it's a label reference. 2205234353Sdim if (isImm()) { 2206226633Sdim addExpr(Inst, getImm()); 2207288943Sdim Inst.addOperand(MCOperand::createImm(0)); 2208226633Sdim return; 2209226633Sdim } 2210221345Sdim 2211226633Sdim // Otherwise, it's a normal memory reg+offset. 2212226633Sdim int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2213288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2214288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2215221345Sdim } 2216221345Sdim 2217226633Sdim void addMemTBBOperands(MCInst &Inst, unsigned N) const { 2218226633Sdim assert(N == 2 && "Invalid number of operands!"); 2219288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2220288943Sdim Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2221226633Sdim } 2222218893Sdim 2223226633Sdim void addMemTBHOperands(MCInst &Inst, unsigned N) const { 2224226633Sdim assert(N == 2 && "Invalid number of operands!"); 2225288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2226288943Sdim Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2227226633Sdim } 2228218893Sdim 2229226633Sdim void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2230226633Sdim assert(N == 3 && "Invalid number of operands!"); 2231234353Sdim unsigned Val = 2232234353Sdim ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 2233234353Sdim Memory.ShiftImm, Memory.ShiftType); 2234288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2235288943Sdim Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2236288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2237226633Sdim } 2238218893Sdim 2239226633Sdim void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2240226633Sdim assert(N == 3 && "Invalid number of operands!"); 2241288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2242288943Sdim Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2243288943Sdim Inst.addOperand(MCOperand::createImm(Memory.ShiftImm)); 2244218893Sdim } 2245218893Sdim 2246226633Sdim void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 2247226633Sdim assert(N == 2 && "Invalid number of operands!"); 2248288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2249288943Sdim Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2250218893Sdim } 2251218893Sdim 2252226633Sdim void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 2253226633Sdim assert(N == 2 && "Invalid number of operands!"); 2254226633Sdim int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2255288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2256288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2257218893Sdim } 2258218893Sdim 2259226633Sdim void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 2260226633Sdim assert(N == 2 && "Invalid number of operands!"); 2261226633Sdim int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 2262288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2263288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2264226633Sdim } 2265226633Sdim 2266226633Sdim void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 2267226633Sdim assert(N == 2 && "Invalid number of operands!"); 2268226633Sdim int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 2269288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2270288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2271226633Sdim } 2272226633Sdim 2273226633Sdim void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 2274226633Sdim assert(N == 2 && "Invalid number of operands!"); 2275226633Sdim int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2276288943Sdim Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2277288943Sdim Inst.addOperand(MCOperand::createImm(Val)); 2278226633Sdim } 2279226633Sdim 2280226633Sdim void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 2281226633Sdim assert(N == 1 && "Invalid number of operands!"); 2282226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2283226633Sdim assert(CE && "non-constant post-idx-imm8 operand!"); 2284226633Sdim int Imm = CE->getValue(); 2285226633Sdim bool isAdd = Imm >= 0; 2286226633Sdim if (Imm == INT32_MIN) Imm = 0; 2287226633Sdim Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 2288288943Sdim Inst.addOperand(MCOperand::createImm(Imm)); 2289226633Sdim } 2290226633Sdim 2291226633Sdim void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 2292226633Sdim assert(N == 1 && "Invalid number of operands!"); 2293226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2294226633Sdim assert(CE && "non-constant post-idx-imm8s4 operand!"); 2295226633Sdim int Imm = CE->getValue(); 2296226633Sdim bool isAdd = Imm >= 0; 2297226633Sdim if (Imm == INT32_MIN) Imm = 0; 2298226633Sdim // Immediate is scaled by 4. 2299226633Sdim Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 2300288943Sdim Inst.addOperand(MCOperand::createImm(Imm)); 2301226633Sdim } 2302226633Sdim 2303226633Sdim void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 2304226633Sdim assert(N == 2 && "Invalid number of operands!"); 2305288943Sdim Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); 2306288943Sdim Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); 2307226633Sdim } 2308226633Sdim 2309226633Sdim void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 2310226633Sdim assert(N == 2 && "Invalid number of operands!"); 2311288943Sdim Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); 2312226633Sdim // The sign, shift type, and shift amount are encoded in a single operand 2313226633Sdim // using the AM2 encoding helpers. 2314226633Sdim ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 2315226633Sdim unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 2316226633Sdim PostIdxReg.ShiftTy); 2317288943Sdim Inst.addOperand(MCOperand::createImm(Imm)); 2318226633Sdim } 2319226633Sdim 2320218893Sdim void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 2321218893Sdim assert(N == 1 && "Invalid number of operands!"); 2322288943Sdim Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask()))); 2323218893Sdim } 2324218893Sdim 2325280031Sdim void addBankedRegOperands(MCInst &Inst, unsigned N) const { 2326280031Sdim assert(N == 1 && "Invalid number of operands!"); 2327288943Sdim Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg()))); 2328280031Sdim } 2329280031Sdim 2330218893Sdim void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 2331218893Sdim assert(N == 1 && "Invalid number of operands!"); 2332288943Sdim Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags()))); 2333218893Sdim } 2334218893Sdim 2335234353Sdim void addVecListOperands(MCInst &Inst, unsigned N) const { 2336234353Sdim assert(N == 1 && "Invalid number of operands!"); 2337288943Sdim Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); 2338234353Sdim } 2339234353Sdim 2340234353Sdim void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 2341234353Sdim assert(N == 2 && "Invalid number of operands!"); 2342288943Sdim Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); 2343288943Sdim Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex)); 2344234353Sdim } 2345234353Sdim 2346226633Sdim void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 2347226633Sdim assert(N == 1 && "Invalid number of operands!"); 2348288943Sdim Inst.addOperand(MCOperand::createImm(getVectorIndex())); 2349226633Sdim } 2350226633Sdim 2351226633Sdim void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 2352226633Sdim assert(N == 1 && "Invalid number of operands!"); 2353288943Sdim Inst.addOperand(MCOperand::createImm(getVectorIndex())); 2354226633Sdim } 2355226633Sdim 2356226633Sdim void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 2357226633Sdim assert(N == 1 && "Invalid number of operands!"); 2358288943Sdim Inst.addOperand(MCOperand::createImm(getVectorIndex())); 2359226633Sdim } 2360226633Sdim 2361234353Sdim void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 2362234353Sdim assert(N == 1 && "Invalid number of operands!"); 2363234353Sdim // The immediate encodes the type of constant as well as the value. 2364234353Sdim // Mask in that this is an i8 splat. 2365234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2366288943Sdim Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00)); 2367234353Sdim } 2368234353Sdim 2369234353Sdim void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 2370234353Sdim assert(N == 1 && "Invalid number of operands!"); 2371234353Sdim // The immediate encodes the type of constant as well as the value. 2372234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2373234353Sdim unsigned Value = CE->getValue(); 2374280031Sdim Value = ARM_AM::encodeNEONi16splat(Value); 2375288943Sdim Inst.addOperand(MCOperand::createImm(Value)); 2376234353Sdim } 2377234353Sdim 2378280031Sdim void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const { 2379280031Sdim assert(N == 1 && "Invalid number of operands!"); 2380280031Sdim // The immediate encodes the type of constant as well as the value. 2381280031Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2382280031Sdim unsigned Value = CE->getValue(); 2383280031Sdim Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff); 2384288943Sdim Inst.addOperand(MCOperand::createImm(Value)); 2385280031Sdim } 2386280031Sdim 2387234353Sdim void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 2388234353Sdim assert(N == 1 && "Invalid number of operands!"); 2389234353Sdim // The immediate encodes the type of constant as well as the value. 2390234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2391234353Sdim unsigned Value = CE->getValue(); 2392280031Sdim Value = ARM_AM::encodeNEONi32splat(Value); 2393288943Sdim Inst.addOperand(MCOperand::createImm(Value)); 2394234353Sdim } 2395234353Sdim 2396280031Sdim void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const { 2397280031Sdim assert(N == 1 && "Invalid number of operands!"); 2398280031Sdim // The immediate encodes the type of constant as well as the value. 2399280031Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2400280031Sdim unsigned Value = CE->getValue(); 2401280031Sdim Value = ARM_AM::encodeNEONi32splat(~Value); 2402288943Sdim Inst.addOperand(MCOperand::createImm(Value)); 2403280031Sdim } 2404280031Sdim 2405276479Sdim void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const { 2406276479Sdim assert(N == 1 && "Invalid number of operands!"); 2407276479Sdim // The immediate encodes the type of constant as well as the value. 2408276479Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2409276479Sdim unsigned Value = CE->getValue(); 2410276479Sdim assert((Inst.getOpcode() == ARM::VMOVv8i8 || 2411276479Sdim Inst.getOpcode() == ARM::VMOVv16i8) && 2412276479Sdim "All vmvn instructions that wants to replicate non-zero byte " 2413276479Sdim "always must be replaced with VMOVv8i8 or VMOVv16i8."); 2414276479Sdim unsigned B = ((~Value) & 0xff); 2415276479Sdim B |= 0xe00; // cmode = 0b1110 2416288943Sdim Inst.addOperand(MCOperand::createImm(B)); 2417276479Sdim } 2418234353Sdim void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2419234353Sdim assert(N == 1 && "Invalid number of operands!"); 2420234353Sdim // The immediate encodes the type of constant as well as the value. 2421234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2422234353Sdim unsigned Value = CE->getValue(); 2423234353Sdim if (Value >= 256 && Value <= 0xffff) 2424234353Sdim Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2425234353Sdim else if (Value > 0xffff && Value <= 0xffffff) 2426234353Sdim Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2427234353Sdim else if (Value > 0xffffff) 2428234353Sdim Value = (Value >> 24) | 0x600; 2429288943Sdim Inst.addOperand(MCOperand::createImm(Value)); 2430234353Sdim } 2431234353Sdim 2432276479Sdim void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const { 2433276479Sdim assert(N == 1 && "Invalid number of operands!"); 2434276479Sdim // The immediate encodes the type of constant as well as the value. 2435276479Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2436276479Sdim unsigned Value = CE->getValue(); 2437276479Sdim assert((Inst.getOpcode() == ARM::VMOVv8i8 || 2438276479Sdim Inst.getOpcode() == ARM::VMOVv16i8) && 2439276479Sdim "All instructions that wants to replicate non-zero byte " 2440276479Sdim "always must be replaced with VMOVv8i8 or VMOVv16i8."); 2441276479Sdim unsigned B = Value & 0xff; 2442276479Sdim B |= 0xe00; // cmode = 0b1110 2443288943Sdim Inst.addOperand(MCOperand::createImm(B)); 2444276479Sdim } 2445234353Sdim void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2446234353Sdim assert(N == 1 && "Invalid number of operands!"); 2447234353Sdim // The immediate encodes the type of constant as well as the value. 2448234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2449234353Sdim unsigned Value = ~CE->getValue(); 2450234353Sdim if (Value >= 256 && Value <= 0xffff) 2451234353Sdim Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2452234353Sdim else if (Value > 0xffff && Value <= 0xffffff) 2453234353Sdim Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2454234353Sdim else if (Value > 0xffffff) 2455234353Sdim Value = (Value >> 24) | 0x600; 2456288943Sdim Inst.addOperand(MCOperand::createImm(Value)); 2457234353Sdim } 2458234353Sdim 2459234353Sdim void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2460234353Sdim assert(N == 1 && "Invalid number of operands!"); 2461234353Sdim // The immediate encodes the type of constant as well as the value. 2462234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2463234353Sdim uint64_t Value = CE->getValue(); 2464234353Sdim unsigned Imm = 0; 2465234353Sdim for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2466234353Sdim Imm |= (Value & 1) << i; 2467234353Sdim } 2468288943Sdim Inst.addOperand(MCOperand::createImm(Imm | 0x1e00)); 2469234353Sdim } 2470234353Sdim 2471276479Sdim void print(raw_ostream &OS) const override; 2472212904Sdim 2473276479Sdim static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) { 2474276479Sdim auto Op = make_unique<ARMOperand>(k_ITCondMask); 2475226633Sdim Op->ITMask.Mask = Mask; 2476226633Sdim Op->StartLoc = S; 2477226633Sdim Op->EndLoc = S; 2478226633Sdim return Op; 2479226633Sdim } 2480226633Sdim 2481276479Sdim static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC, 2482276479Sdim SMLoc S) { 2483276479Sdim auto Op = make_unique<ARMOperand>(k_CondCode); 2484212904Sdim Op->CC.Val = CC; 2485212904Sdim Op->StartLoc = S; 2486212904Sdim Op->EndLoc = S; 2487218893Sdim return Op; 2488212904Sdim } 2489212904Sdim 2490276479Sdim static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) { 2491276479Sdim auto Op = make_unique<ARMOperand>(k_CoprocNum); 2492218893Sdim Op->Cop.Val = CopVal; 2493218893Sdim Op->StartLoc = S; 2494218893Sdim Op->EndLoc = S; 2495218893Sdim return Op; 2496218893Sdim } 2497218893Sdim 2498276479Sdim static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) { 2499276479Sdim auto Op = make_unique<ARMOperand>(k_CoprocReg); 2500218893Sdim Op->Cop.Val = CopVal; 2501218893Sdim Op->StartLoc = S; 2502218893Sdim Op->EndLoc = S; 2503218893Sdim return Op; 2504218893Sdim } 2505218893Sdim 2506276479Sdim static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S, 2507276479Sdim SMLoc E) { 2508276479Sdim auto Op = make_unique<ARMOperand>(k_CoprocOption); 2509226633Sdim Op->Cop.Val = Val; 2510226633Sdim Op->StartLoc = S; 2511226633Sdim Op->EndLoc = E; 2512226633Sdim return Op; 2513226633Sdim } 2514226633Sdim 2515276479Sdim static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) { 2516276479Sdim auto Op = make_unique<ARMOperand>(k_CCOut); 2517218893Sdim Op->Reg.RegNum = RegNum; 2518218893Sdim Op->StartLoc = S; 2519218893Sdim Op->EndLoc = S; 2520218893Sdim return Op; 2521218893Sdim } 2522218893Sdim 2523276479Sdim static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) { 2524276479Sdim auto Op = make_unique<ARMOperand>(k_Token); 2525206124Srdivacky Op->Tok.Data = Str.data(); 2526206124Srdivacky Op->Tok.Length = Str.size(); 2527206124Srdivacky Op->StartLoc = S; 2528206124Srdivacky Op->EndLoc = S; 2529218893Sdim return Op; 2530198090Srdivacky } 2531198090Srdivacky 2532276479Sdim static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S, 2533276479Sdim SMLoc E) { 2534276479Sdim auto Op = make_unique<ARMOperand>(k_Register); 2535206124Srdivacky Op->Reg.RegNum = RegNum; 2536206124Srdivacky Op->StartLoc = S; 2537206124Srdivacky Op->EndLoc = E; 2538218893Sdim return Op; 2539198090Srdivacky } 2540198090Srdivacky 2541276479Sdim static std::unique_ptr<ARMOperand> 2542276479Sdim CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, 2543276479Sdim unsigned ShiftReg, unsigned ShiftImm, SMLoc S, 2544276479Sdim SMLoc E) { 2545276479Sdim auto Op = make_unique<ARMOperand>(k_ShiftedRegister); 2546226633Sdim Op->RegShiftedReg.ShiftTy = ShTy; 2547226633Sdim Op->RegShiftedReg.SrcReg = SrcReg; 2548226633Sdim Op->RegShiftedReg.ShiftReg = ShiftReg; 2549226633Sdim Op->RegShiftedReg.ShiftImm = ShiftImm; 2550224145Sdim Op->StartLoc = S; 2551224145Sdim Op->EndLoc = E; 2552224145Sdim return Op; 2553224145Sdim } 2554224145Sdim 2555276479Sdim static std::unique_ptr<ARMOperand> 2556276479Sdim CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, 2557276479Sdim unsigned ShiftImm, SMLoc S, SMLoc E) { 2558276479Sdim auto Op = make_unique<ARMOperand>(k_ShiftedImmediate); 2559226633Sdim Op->RegShiftedImm.ShiftTy = ShTy; 2560226633Sdim Op->RegShiftedImm.SrcReg = SrcReg; 2561226633Sdim Op->RegShiftedImm.ShiftImm = ShiftImm; 2562226633Sdim Op->StartLoc = S; 2563226633Sdim Op->EndLoc = E; 2564226633Sdim return Op; 2565226633Sdim } 2566226633Sdim 2567276479Sdim static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm, 2568276479Sdim SMLoc S, SMLoc E) { 2569276479Sdim auto Op = make_unique<ARMOperand>(k_ShifterImmediate); 2570226633Sdim Op->ShifterImm.isASR = isASR; 2571226633Sdim Op->ShifterImm.Imm = Imm; 2572221345Sdim Op->StartLoc = S; 2573221345Sdim Op->EndLoc = E; 2574221345Sdim return Op; 2575221345Sdim } 2576221345Sdim 2577276479Sdim static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S, 2578276479Sdim SMLoc E) { 2579276479Sdim auto Op = make_unique<ARMOperand>(k_RotateImmediate); 2580226633Sdim Op->RotImm.Imm = Imm; 2581226633Sdim Op->StartLoc = S; 2582226633Sdim Op->EndLoc = E; 2583226633Sdim return Op; 2584226633Sdim } 2585226633Sdim 2586280031Sdim static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot, 2587280031Sdim SMLoc S, SMLoc E) { 2588280031Sdim auto Op = make_unique<ARMOperand>(k_ModifiedImmediate); 2589280031Sdim Op->ModImm.Bits = Bits; 2590280031Sdim Op->ModImm.Rot = Rot; 2591280031Sdim Op->StartLoc = S; 2592280031Sdim Op->EndLoc = E; 2593280031Sdim return Op; 2594280031Sdim } 2595280031Sdim 2596276479Sdim static std::unique_ptr<ARMOperand> 2597276479Sdim CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) { 2598276479Sdim auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor); 2599226633Sdim Op->Bitfield.LSB = LSB; 2600226633Sdim Op->Bitfield.Width = Width; 2601226633Sdim Op->StartLoc = S; 2602226633Sdim Op->EndLoc = E; 2603226633Sdim return Op; 2604226633Sdim } 2605226633Sdim 2606276479Sdim static std::unique_ptr<ARMOperand> 2607276479Sdim CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, 2608218893Sdim SMLoc StartLoc, SMLoc EndLoc) { 2609261991Sdim assert (Regs.size() > 0 && "RegList contains no registers?"); 2610226633Sdim KindTy Kind = k_RegisterList; 2611218893Sdim 2612261991Sdim if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second)) 2613226633Sdim Kind = k_DPRRegisterList; 2614226633Sdim else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2615261991Sdim contains(Regs.front().second)) 2616226633Sdim Kind = k_SPRRegisterList; 2617218893Sdim 2618261991Sdim // Sort based on the register encoding values. 2619261991Sdim array_pod_sort(Regs.begin(), Regs.end()); 2620261991Sdim 2621276479Sdim auto Op = make_unique<ARMOperand>(Kind); 2622261991Sdim for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator 2623218893Sdim I = Regs.begin(), E = Regs.end(); I != E; ++I) 2624261991Sdim Op->Registers.push_back(I->second); 2625218893Sdim Op->StartLoc = StartLoc; 2626218893Sdim Op->EndLoc = EndLoc; 2627218893Sdim return Op; 2628218893Sdim } 2629218893Sdim 2630276479Sdim static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum, 2631276479Sdim unsigned Count, 2632276479Sdim bool isDoubleSpaced, 2633276479Sdim SMLoc S, SMLoc E) { 2634276479Sdim auto Op = make_unique<ARMOperand>(k_VectorList); 2635234353Sdim Op->VectorList.RegNum = RegNum; 2636234353Sdim Op->VectorList.Count = Count; 2637234353Sdim Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2638234353Sdim Op->StartLoc = S; 2639234353Sdim Op->EndLoc = E; 2640234353Sdim return Op; 2641234353Sdim } 2642234353Sdim 2643276479Sdim static std::unique_ptr<ARMOperand> 2644276479Sdim CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, 2645276479Sdim SMLoc S, SMLoc E) { 2646276479Sdim auto Op = make_unique<ARMOperand>(k_VectorListAllLanes); 2647234353Sdim Op->VectorList.RegNum = RegNum; 2648234353Sdim Op->VectorList.Count = Count; 2649234353Sdim Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2650234353Sdim Op->StartLoc = S; 2651234353Sdim Op->EndLoc = E; 2652234353Sdim return Op; 2653234353Sdim } 2654234353Sdim 2655276479Sdim static std::unique_ptr<ARMOperand> 2656276479Sdim CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, 2657276479Sdim bool isDoubleSpaced, SMLoc S, SMLoc E) { 2658276479Sdim auto Op = make_unique<ARMOperand>(k_VectorListIndexed); 2659234353Sdim Op->VectorList.RegNum = RegNum; 2660234353Sdim Op->VectorList.Count = Count; 2661234353Sdim Op->VectorList.LaneIndex = Index; 2662234353Sdim Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2663234353Sdim Op->StartLoc = S; 2664234353Sdim Op->EndLoc = E; 2665234353Sdim return Op; 2666234353Sdim } 2667234353Sdim 2668276479Sdim static std::unique_ptr<ARMOperand> 2669276479Sdim CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) { 2670276479Sdim auto Op = make_unique<ARMOperand>(k_VectorIndex); 2671226633Sdim Op->VectorIndex.Val = Idx; 2672226633Sdim Op->StartLoc = S; 2673226633Sdim Op->EndLoc = E; 2674226633Sdim return Op; 2675226633Sdim } 2676226633Sdim 2677276479Sdim static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S, 2678276479Sdim SMLoc E) { 2679276479Sdim auto Op = make_unique<ARMOperand>(k_Immediate); 2680206124Srdivacky Op->Imm.Val = Val; 2681206124Srdivacky Op->StartLoc = S; 2682206124Srdivacky Op->EndLoc = E; 2683218893Sdim return Op; 2684198090Srdivacky } 2685198090Srdivacky 2686276479Sdim static std::unique_ptr<ARMOperand> 2687276479Sdim CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm, 2688276479Sdim unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, 2689276479Sdim unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, 2690276479Sdim SMLoc E, SMLoc AlignmentLoc = SMLoc()) { 2691276479Sdim auto Op = make_unique<ARMOperand>(k_Memory); 2692226633Sdim Op->Memory.BaseRegNum = BaseRegNum; 2693226633Sdim Op->Memory.OffsetImm = OffsetImm; 2694226633Sdim Op->Memory.OffsetRegNum = OffsetRegNum; 2695226633Sdim Op->Memory.ShiftType = ShiftType; 2696226633Sdim Op->Memory.ShiftImm = ShiftImm; 2697226633Sdim Op->Memory.Alignment = Alignment; 2698226633Sdim Op->Memory.isNegative = isNegative; 2699226633Sdim Op->StartLoc = S; 2700226633Sdim Op->EndLoc = E; 2701276479Sdim Op->AlignmentLoc = AlignmentLoc; 2702226633Sdim return Op; 2703226633Sdim } 2704218893Sdim 2705276479Sdim static std::unique_ptr<ARMOperand> 2706276479Sdim CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, 2707276479Sdim unsigned ShiftImm, SMLoc S, SMLoc E) { 2708276479Sdim auto Op = make_unique<ARMOperand>(k_PostIndexRegister); 2709226633Sdim Op->PostIdxReg.RegNum = RegNum; 2710226633Sdim Op->PostIdxReg.isAdd = isAdd; 2711226633Sdim Op->PostIdxReg.ShiftTy = ShiftTy; 2712226633Sdim Op->PostIdxReg.ShiftImm = ShiftImm; 2713206124Srdivacky Op->StartLoc = S; 2714206124Srdivacky Op->EndLoc = E; 2715218893Sdim return Op; 2716198090Srdivacky } 2717218893Sdim 2718276479Sdim static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, 2719276479Sdim SMLoc S) { 2720276479Sdim auto Op = make_unique<ARMOperand>(k_MemBarrierOpt); 2721218893Sdim Op->MBOpt.Val = Opt; 2722218893Sdim Op->StartLoc = S; 2723218893Sdim Op->EndLoc = S; 2724218893Sdim return Op; 2725218893Sdim } 2726218893Sdim 2727276479Sdim static std::unique_ptr<ARMOperand> 2728276479Sdim CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) { 2729276479Sdim auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt); 2730261991Sdim Op->ISBOpt.Val = Opt; 2731261991Sdim Op->StartLoc = S; 2732261991Sdim Op->EndLoc = S; 2733261991Sdim return Op; 2734261991Sdim } 2735261991Sdim 2736276479Sdim static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags, 2737276479Sdim SMLoc S) { 2738276479Sdim auto Op = make_unique<ARMOperand>(k_ProcIFlags); 2739218893Sdim Op->IFlags.Val = IFlags; 2740218893Sdim Op->StartLoc = S; 2741218893Sdim Op->EndLoc = S; 2742218893Sdim return Op; 2743218893Sdim } 2744218893Sdim 2745276479Sdim static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) { 2746276479Sdim auto Op = make_unique<ARMOperand>(k_MSRMask); 2747218893Sdim Op->MMask.Val = MMask; 2748218893Sdim Op->StartLoc = S; 2749218893Sdim Op->EndLoc = S; 2750218893Sdim return Op; 2751218893Sdim } 2752280031Sdim 2753280031Sdim static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) { 2754280031Sdim auto Op = make_unique<ARMOperand>(k_BankedReg); 2755280031Sdim Op->BankedReg.Val = Reg; 2756280031Sdim Op->StartLoc = S; 2757280031Sdim Op->EndLoc = S; 2758280031Sdim return Op; 2759280031Sdim } 2760198090Srdivacky}; 2761198090Srdivacky 2762198090Srdivacky} // end anonymous namespace. 2763198090Srdivacky 2764224145Sdimvoid ARMOperand::print(raw_ostream &OS) const { 2765212904Sdim switch (Kind) { 2766226633Sdim case k_CondCode: 2767218893Sdim OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2768212904Sdim break; 2769226633Sdim case k_CCOut: 2770218893Sdim OS << "<ccout " << getReg() << ">"; 2771218893Sdim break; 2772226633Sdim case k_ITCondMask: { 2773239462Sdim static const char *const MaskStr[] = { 2774234353Sdim "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2775234353Sdim "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2776234353Sdim }; 2777226633Sdim assert((ITMask.Mask & 0xf) == ITMask.Mask); 2778226633Sdim OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2779226633Sdim break; 2780226633Sdim } 2781226633Sdim case k_CoprocNum: 2782218893Sdim OS << "<coprocessor number: " << getCoproc() << ">"; 2783218893Sdim break; 2784226633Sdim case k_CoprocReg: 2785218893Sdim OS << "<coprocessor register: " << getCoproc() << ">"; 2786218893Sdim break; 2787226633Sdim case k_CoprocOption: 2788226633Sdim OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2789226633Sdim break; 2790226633Sdim case k_MSRMask: 2791218893Sdim OS << "<mask: " << getMSRMask() << ">"; 2792218893Sdim break; 2793280031Sdim case k_BankedReg: 2794280031Sdim OS << "<banked reg: " << getBankedReg() << ">"; 2795280031Sdim break; 2796226633Sdim case k_Immediate: 2797288943Sdim OS << *getImm(); 2798212904Sdim break; 2799226633Sdim case k_MemBarrierOpt: 2800261991Sdim OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">"; 2801218893Sdim break; 2802261991Sdim case k_InstSyncBarrierOpt: 2803261991Sdim OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">"; 2804261991Sdim break; 2805226633Sdim case k_Memory: 2806218893Sdim OS << "<memory " 2807226633Sdim << " base:" << Memory.BaseRegNum; 2808218893Sdim OS << ">"; 2809212904Sdim break; 2810226633Sdim case k_PostIndexRegister: 2811226633Sdim OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2812226633Sdim << PostIdxReg.RegNum; 2813226633Sdim if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2814226633Sdim OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2815226633Sdim << PostIdxReg.ShiftImm; 2816226633Sdim OS << ">"; 2817226633Sdim break; 2818226633Sdim case k_ProcIFlags: { 2819218893Sdim OS << "<ARM_PROC::"; 2820218893Sdim unsigned IFlags = getProcIFlags(); 2821218893Sdim for (int i=2; i >= 0; --i) 2822218893Sdim if (IFlags & (1 << i)) 2823218893Sdim OS << ARM_PROC::IFlagsToString(1 << i); 2824218893Sdim OS << ">"; 2825218893Sdim break; 2826218893Sdim } 2827226633Sdim case k_Register: 2828212904Sdim OS << "<register " << getReg() << ">"; 2829212904Sdim break; 2830226633Sdim case k_ShifterImmediate: 2831226633Sdim OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2832226633Sdim << " #" << ShifterImm.Imm << ">"; 2833221345Sdim break; 2834226633Sdim case k_ShiftedRegister: 2835226633Sdim OS << "<so_reg_reg " 2836234353Sdim << RegShiftedReg.SrcReg << " " 2837234353Sdim << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2838234353Sdim << " " << RegShiftedReg.ShiftReg << ">"; 2839224145Sdim break; 2840226633Sdim case k_ShiftedImmediate: 2841226633Sdim OS << "<so_reg_imm " 2842234353Sdim << RegShiftedImm.SrcReg << " " 2843234353Sdim << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2844234353Sdim << " #" << RegShiftedImm.ShiftImm << ">"; 2845226633Sdim break; 2846226633Sdim case k_RotateImmediate: 2847226633Sdim OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2848226633Sdim break; 2849280031Sdim case k_ModifiedImmediate: 2850280031Sdim OS << "<mod_imm #" << ModImm.Bits << ", #" 2851280031Sdim << ModImm.Rot << ")>"; 2852280031Sdim break; 2853226633Sdim case k_BitfieldDescriptor: 2854226633Sdim OS << "<bitfield " << "lsb: " << Bitfield.LSB 2855226633Sdim << ", width: " << Bitfield.Width << ">"; 2856226633Sdim break; 2857226633Sdim case k_RegisterList: 2858226633Sdim case k_DPRRegisterList: 2859226633Sdim case k_SPRRegisterList: { 2860218893Sdim OS << "<register_list "; 2861218893Sdim 2862218893Sdim const SmallVectorImpl<unsigned> &RegList = getRegList(); 2863218893Sdim for (SmallVectorImpl<unsigned>::const_iterator 2864218893Sdim I = RegList.begin(), E = RegList.end(); I != E; ) { 2865218893Sdim OS << *I; 2866218893Sdim if (++I < E) OS << ", "; 2867218893Sdim } 2868218893Sdim 2869218893Sdim OS << ">"; 2870218893Sdim break; 2871218893Sdim } 2872234353Sdim case k_VectorList: 2873234353Sdim OS << "<vector_list " << VectorList.Count << " * " 2874234353Sdim << VectorList.RegNum << ">"; 2875234353Sdim break; 2876234353Sdim case k_VectorListAllLanes: 2877234353Sdim OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2878234353Sdim << VectorList.RegNum << ">"; 2879234353Sdim break; 2880234353Sdim case k_VectorListIndexed: 2881234353Sdim OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2882234353Sdim << VectorList.Count << " * " << VectorList.RegNum << ">"; 2883234353Sdim break; 2884226633Sdim case k_Token: 2885212904Sdim OS << "'" << getToken() << "'"; 2886212904Sdim break; 2887226633Sdim case k_VectorIndex: 2888226633Sdim OS << "<vectorindex " << getVectorIndex() << ">"; 2889226633Sdim break; 2890212904Sdim } 2891212904Sdim} 2892212904Sdim 2893212904Sdim/// @name Auto-generated Match Functions 2894212904Sdim/// { 2895212904Sdim 2896212904Sdimstatic unsigned MatchRegisterName(StringRef Name); 2897212904Sdim 2898212904Sdim/// } 2899212904Sdim 2900218893Sdimbool ARMAsmParser::ParseRegister(unsigned &RegNo, 2901218893Sdim SMLoc &StartLoc, SMLoc &EndLoc) { 2902280031Sdim const AsmToken &Tok = getParser().getTok(); 2903280031Sdim StartLoc = Tok.getLoc(); 2904280031Sdim EndLoc = Tok.getEndLoc(); 2905226633Sdim RegNo = tryParseRegister(); 2906218893Sdim 2907218893Sdim return (RegNo == (unsigned)-1); 2908218893Sdim} 2909218893Sdim 2910198892Srdivacky/// Try to parse a register name. The token must be an Identifier when called, 2911218893Sdim/// and if it is a register name the token is eaten and the register number is 2912218893Sdim/// returned. Otherwise return -1. 2913218893Sdim/// 2914226633Sdimint ARMAsmParser::tryParseRegister() { 2915280031Sdim MCAsmParser &Parser = getParser(); 2916202878Srdivacky const AsmToken &Tok = Parser.getTok(); 2917226633Sdim if (Tok.isNot(AsmToken::Identifier)) return -1; 2918198090Srdivacky 2919234353Sdim std::string lowerCase = Tok.getString().lower(); 2920218893Sdim unsigned RegNum = MatchRegisterName(lowerCase); 2921218893Sdim if (!RegNum) { 2922218893Sdim RegNum = StringSwitch<unsigned>(lowerCase) 2923218893Sdim .Case("r13", ARM::SP) 2924218893Sdim .Case("r14", ARM::LR) 2925218893Sdim .Case("r15", ARM::PC) 2926218893Sdim .Case("ip", ARM::R12) 2927234353Sdim // Additional register name aliases for 'gas' compatibility. 2928234353Sdim .Case("a1", ARM::R0) 2929234353Sdim .Case("a2", ARM::R1) 2930234353Sdim .Case("a3", ARM::R2) 2931234353Sdim .Case("a4", ARM::R3) 2932234353Sdim .Case("v1", ARM::R4) 2933234353Sdim .Case("v2", ARM::R5) 2934234353Sdim .Case("v3", ARM::R6) 2935234353Sdim .Case("v4", ARM::R7) 2936234353Sdim .Case("v5", ARM::R8) 2937234353Sdim .Case("v6", ARM::R9) 2938234353Sdim .Case("v7", ARM::R10) 2939234353Sdim .Case("v8", ARM::R11) 2940234353Sdim .Case("sb", ARM::R9) 2941234353Sdim .Case("sl", ARM::R10) 2942234353Sdim .Case("fp", ARM::R11) 2943218893Sdim .Default(0); 2944218893Sdim } 2945234353Sdim if (!RegNum) { 2946234353Sdim // Check for aliases registered via .req. Canonicalize to lower case. 2947234353Sdim // That's more consistent since register names are case insensitive, and 2948234353Sdim // it's how the original entry was passed in from MC/MCParser/AsmParser. 2949234353Sdim StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2950234353Sdim // If no match, return failure. 2951234353Sdim if (Entry == RegisterReqs.end()) 2952234353Sdim return -1; 2953234353Sdim Parser.Lex(); // Eat identifier token. 2954234353Sdim return Entry->getValue(); 2955234353Sdim } 2956198090Srdivacky 2957280031Sdim // Some FPUs only have 16 D registers, so D16-D31 are invalid 2958280031Sdim if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31) 2959280031Sdim return -1; 2960280031Sdim 2961202878Srdivacky Parser.Lex(); // Eat identifier token. 2962226633Sdim 2963218893Sdim return RegNum; 2964218893Sdim} 2965198090Srdivacky 2966224145Sdim// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2967224145Sdim// If a recoverable error occurs, return 1. If an irrecoverable error 2968224145Sdim// occurs, return -1. An irrecoverable error is one where tokens have been 2969224145Sdim// consumed in the process of trying to parse the shifter (i.e., when it is 2970224145Sdim// indeed a shifter operand, but malformed). 2971276479Sdimint ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { 2972280031Sdim MCAsmParser &Parser = getParser(); 2973221345Sdim SMLoc S = Parser.getTok().getLoc(); 2974221345Sdim const AsmToken &Tok = Parser.getTok(); 2975276479Sdim if (Tok.isNot(AsmToken::Identifier)) 2976276479Sdim return -1; 2977221345Sdim 2978234353Sdim std::string lowerCase = Tok.getString().lower(); 2979221345Sdim ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2980234353Sdim .Case("asl", ARM_AM::lsl) 2981221345Sdim .Case("lsl", ARM_AM::lsl) 2982221345Sdim .Case("lsr", ARM_AM::lsr) 2983221345Sdim .Case("asr", ARM_AM::asr) 2984221345Sdim .Case("ror", ARM_AM::ror) 2985221345Sdim .Case("rrx", ARM_AM::rrx) 2986221345Sdim .Default(ARM_AM::no_shift); 2987221345Sdim 2988221345Sdim if (ShiftTy == ARM_AM::no_shift) 2989224145Sdim return 1; 2990221345Sdim 2991224145Sdim Parser.Lex(); // Eat the operator. 2992221345Sdim 2993224145Sdim // The source register for the shift has already been added to the 2994224145Sdim // operand list, so we need to pop it off and combine it into the shifted 2995224145Sdim // register operand instead. 2996276479Sdim std::unique_ptr<ARMOperand> PrevOp( 2997276479Sdim (ARMOperand *)Operands.pop_back_val().release()); 2998224145Sdim if (!PrevOp->isReg()) 2999224145Sdim return Error(PrevOp->getStartLoc(), "shift must be of a register"); 3000224145Sdim int SrcReg = PrevOp->getReg(); 3001249423Sdim 3002249423Sdim SMLoc EndLoc; 3003224145Sdim int64_t Imm = 0; 3004224145Sdim int ShiftReg = 0; 3005224145Sdim if (ShiftTy == ARM_AM::rrx) { 3006224145Sdim // RRX Doesn't have an explicit shift amount. The encoder expects 3007224145Sdim // the shift register to be the same as the source register. Seems odd, 3008224145Sdim // but OK. 3009224145Sdim ShiftReg = SrcReg; 3010224145Sdim } else { 3011224145Sdim // Figure out if this is shifted by a constant or a register (for non-RRX). 3012234353Sdim if (Parser.getTok().is(AsmToken::Hash) || 3013234353Sdim Parser.getTok().is(AsmToken::Dollar)) { 3014224145Sdim Parser.Lex(); // Eat hash. 3015224145Sdim SMLoc ImmLoc = Parser.getTok().getLoc(); 3016276479Sdim const MCExpr *ShiftExpr = nullptr; 3017249423Sdim if (getParser().parseExpression(ShiftExpr, EndLoc)) { 3018224145Sdim Error(ImmLoc, "invalid immediate shift value"); 3019224145Sdim return -1; 3020224145Sdim } 3021224145Sdim // The expression must be evaluatable as an immediate. 3022224145Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 3023224145Sdim if (!CE) { 3024224145Sdim Error(ImmLoc, "invalid immediate shift value"); 3025224145Sdim return -1; 3026224145Sdim } 3027224145Sdim // Range check the immediate. 3028224145Sdim // lsl, ror: 0 <= imm <= 31 3029224145Sdim // lsr, asr: 0 <= imm <= 32 3030224145Sdim Imm = CE->getValue(); 3031224145Sdim if (Imm < 0 || 3032224145Sdim ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 3033224145Sdim ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 3034224145Sdim Error(ImmLoc, "immediate shift value out of range"); 3035224145Sdim return -1; 3036224145Sdim } 3037234353Sdim // shift by zero is a nop. Always send it through as lsl. 3038234353Sdim // ('as' compatibility) 3039234353Sdim if (Imm == 0) 3040234353Sdim ShiftTy = ARM_AM::lsl; 3041224145Sdim } else if (Parser.getTok().is(AsmToken::Identifier)) { 3042249423Sdim SMLoc L = Parser.getTok().getLoc(); 3043249423Sdim EndLoc = Parser.getTok().getEndLoc(); 3044226633Sdim ShiftReg = tryParseRegister(); 3045224145Sdim if (ShiftReg == -1) { 3046276479Sdim Error(L, "expected immediate or register in shift operand"); 3047224145Sdim return -1; 3048224145Sdim } 3049224145Sdim } else { 3050276479Sdim Error(Parser.getTok().getLoc(), 3051276479Sdim "expected immediate or register in shift operand"); 3052224145Sdim return -1; 3053224145Sdim } 3054224145Sdim } 3055224145Sdim 3056226633Sdim if (ShiftReg && ShiftTy != ARM_AM::rrx) 3057226633Sdim Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 3058226633Sdim ShiftReg, Imm, 3059249423Sdim S, EndLoc)); 3060226633Sdim else 3061226633Sdim Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 3062249423Sdim S, EndLoc)); 3063221345Sdim 3064224145Sdim return 0; 3065221345Sdim} 3066221345Sdim 3067221345Sdim 3068218893Sdim/// Try to parse a register name. The token must be an Identifier when called. 3069218893Sdim/// If it's a register, an AsmOperand is created. Another AsmOperand is created 3070218893Sdim/// if there is a "writeback". 'true' if it's not a register. 3071218893Sdim/// 3072218893Sdim/// TODO this is likely to change to allow different register types and or to 3073218893Sdim/// parse for a specific register type. 3074276479Sdimbool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { 3075280031Sdim MCAsmParser &Parser = getParser(); 3076249423Sdim const AsmToken &RegTok = Parser.getTok(); 3077226633Sdim int RegNo = tryParseRegister(); 3078218893Sdim if (RegNo == -1) 3079218893Sdim return true; 3080218893Sdim 3081249423Sdim Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), 3082249423Sdim RegTok.getEndLoc())); 3083218893Sdim 3084218893Sdim const AsmToken &ExclaimTok = Parser.getTok(); 3085218893Sdim if (ExclaimTok.is(AsmToken::Exclaim)) { 3086218893Sdim Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 3087218893Sdim ExclaimTok.getLoc())); 3088218893Sdim Parser.Lex(); // Eat exclaim token 3089226633Sdim return false; 3090218893Sdim } 3091218893Sdim 3092226633Sdim // Also check for an index operand. This is only legal for vector registers, 3093226633Sdim // but that'll get caught OK in operand matching, so we don't need to 3094226633Sdim // explicitly filter everything else out here. 3095226633Sdim if (Parser.getTok().is(AsmToken::LBrac)) { 3096226633Sdim SMLoc SIdx = Parser.getTok().getLoc(); 3097226633Sdim Parser.Lex(); // Eat left bracket token. 3098226633Sdim 3099226633Sdim const MCExpr *ImmVal; 3100249423Sdim if (getParser().parseExpression(ImmVal)) 3101234353Sdim return true; 3102226633Sdim const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 3103234353Sdim if (!MCE) 3104234353Sdim return TokError("immediate value expected for vector index"); 3105226633Sdim 3106234353Sdim if (Parser.getTok().isNot(AsmToken::RBrac)) 3107249423Sdim return Error(Parser.getTok().getLoc(), "']' expected"); 3108226633Sdim 3109249423Sdim SMLoc E = Parser.getTok().getEndLoc(); 3110226633Sdim Parser.Lex(); // Eat right bracket token. 3111226633Sdim 3112226633Sdim Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 3113226633Sdim SIdx, E, 3114226633Sdim getContext())); 3115226633Sdim } 3116226633Sdim 3117218893Sdim return false; 3118218893Sdim} 3119218893Sdim 3120218893Sdim/// MatchCoprocessorOperandName - Try to parse an coprocessor related 3121276479Sdim/// instruction with a symbolic operand name. 3122276479Sdim/// We accept "crN" syntax for GAS compatibility. 3123276479Sdim/// <operand-name> ::= <prefix><number> 3124276479Sdim/// If CoprocOp is 'c', then: 3125276479Sdim/// <prefix> ::= c | cr 3126276479Sdim/// If CoprocOp is 'p', then : 3127276479Sdim/// <prefix> ::= p 3128276479Sdim/// <number> ::= integer in range [0, 15] 3129218893Sdimstatic int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 3130218893Sdim // Use the same layout as the tablegen'erated register name matcher. Ugly, 3131218893Sdim // but efficient. 3132276479Sdim if (Name.size() < 2 || Name[0] != CoprocOp) 3133276479Sdim return -1; 3134276479Sdim Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front(); 3135276479Sdim 3136218893Sdim switch (Name.size()) { 3137234353Sdim default: return -1; 3138276479Sdim case 1: 3139276479Sdim switch (Name[0]) { 3140218893Sdim default: return -1; 3141218893Sdim case '0': return 0; 3142218893Sdim case '1': return 1; 3143218893Sdim case '2': return 2; 3144218893Sdim case '3': return 3; 3145218893Sdim case '4': return 4; 3146218893Sdim case '5': return 5; 3147218893Sdim case '6': return 6; 3148218893Sdim case '7': return 7; 3149218893Sdim case '8': return 8; 3150218893Sdim case '9': return 9; 3151198892Srdivacky } 3152276479Sdim case 2: 3153276479Sdim if (Name[0] != '1') 3154218893Sdim return -1; 3155276479Sdim switch (Name[1]) { 3156218893Sdim default: return -1; 3157276479Sdim // CP10 and CP11 are VFP/NEON and so vector instructions should be used. 3158276479Sdim // However, old cores (v5/v6) did use them in that way. 3159276479Sdim case '0': return 10; 3160276479Sdim case '1': return 11; 3161218893Sdim case '2': return 12; 3162218893Sdim case '3': return 13; 3163218893Sdim case '4': return 14; 3164218893Sdim case '5': return 15; 3165218893Sdim } 3166198090Srdivacky } 3167218893Sdim} 3168198090Srdivacky 3169226633Sdim/// parseITCondCode - Try to parse a condition code for an IT instruction. 3170276479SdimARMAsmParser::OperandMatchResultTy 3171276479SdimARMAsmParser::parseITCondCode(OperandVector &Operands) { 3172280031Sdim MCAsmParser &Parser = getParser(); 3173226633Sdim SMLoc S = Parser.getTok().getLoc(); 3174226633Sdim const AsmToken &Tok = Parser.getTok(); 3175226633Sdim if (!Tok.is(AsmToken::Identifier)) 3176226633Sdim return MatchOperand_NoMatch; 3177239462Sdim unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 3178226633Sdim .Case("eq", ARMCC::EQ) 3179226633Sdim .Case("ne", ARMCC::NE) 3180226633Sdim .Case("hs", ARMCC::HS) 3181226633Sdim .Case("cs", ARMCC::HS) 3182226633Sdim .Case("lo", ARMCC::LO) 3183226633Sdim .Case("cc", ARMCC::LO) 3184226633Sdim .Case("mi", ARMCC::MI) 3185226633Sdim .Case("pl", ARMCC::PL) 3186226633Sdim .Case("vs", ARMCC::VS) 3187226633Sdim .Case("vc", ARMCC::VC) 3188226633Sdim .Case("hi", ARMCC::HI) 3189226633Sdim .Case("ls", ARMCC::LS) 3190226633Sdim .Case("ge", ARMCC::GE) 3191226633Sdim .Case("lt", ARMCC::LT) 3192226633Sdim .Case("gt", ARMCC::GT) 3193226633Sdim .Case("le", ARMCC::LE) 3194226633Sdim .Case("al", ARMCC::AL) 3195226633Sdim .Default(~0U); 3196226633Sdim if (CC == ~0U) 3197226633Sdim return MatchOperand_NoMatch; 3198226633Sdim Parser.Lex(); // Eat the token. 3199226633Sdim 3200226633Sdim Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 3201226633Sdim 3202226633Sdim return MatchOperand_Success; 3203226633Sdim} 3204226633Sdim 3205226633Sdim/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 3206218893Sdim/// token must be an Identifier when called, and if it is a coprocessor 3207218893Sdim/// number, the token is eaten and the operand is added to the operand list. 3208276479SdimARMAsmParser::OperandMatchResultTy 3209276479SdimARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { 3210280031Sdim MCAsmParser &Parser = getParser(); 3211218893Sdim SMLoc S = Parser.getTok().getLoc(); 3212218893Sdim const AsmToken &Tok = Parser.getTok(); 3213226633Sdim if (Tok.isNot(AsmToken::Identifier)) 3214226633Sdim return MatchOperand_NoMatch; 3215218893Sdim 3216218893Sdim int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 3217218893Sdim if (Num == -1) 3218218893Sdim return MatchOperand_NoMatch; 3219276479Sdim // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions 3220276479Sdim if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11)) 3221276479Sdim return MatchOperand_NoMatch; 3222218893Sdim 3223218893Sdim Parser.Lex(); // Eat identifier token. 3224218893Sdim Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 3225218893Sdim return MatchOperand_Success; 3226198090Srdivacky} 3227198090Srdivacky 3228226633Sdim/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 3229218893Sdim/// token must be an Identifier when called, and if it is a coprocessor 3230218893Sdim/// number, the token is eaten and the operand is added to the operand list. 3231276479SdimARMAsmParser::OperandMatchResultTy 3232276479SdimARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { 3233280031Sdim MCAsmParser &Parser = getParser(); 3234218893Sdim SMLoc S = Parser.getTok().getLoc(); 3235218893Sdim const AsmToken &Tok = Parser.getTok(); 3236226633Sdim if (Tok.isNot(AsmToken::Identifier)) 3237226633Sdim return MatchOperand_NoMatch; 3238198090Srdivacky 3239218893Sdim int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 3240218893Sdim if (Reg == -1) 3241218893Sdim return MatchOperand_NoMatch; 3242218893Sdim 3243202878Srdivacky Parser.Lex(); // Eat identifier token. 3244218893Sdim Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 3245218893Sdim return MatchOperand_Success; 3246218893Sdim} 3247198090Srdivacky 3248226633Sdim/// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 3249226633Sdim/// coproc_option : '{' imm0_255 '}' 3250276479SdimARMAsmParser::OperandMatchResultTy 3251276479SdimARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { 3252280031Sdim MCAsmParser &Parser = getParser(); 3253218893Sdim SMLoc S = Parser.getTok().getLoc(); 3254198090Srdivacky 3255226633Sdim // If this isn't a '{', this isn't a coprocessor immediate operand. 3256226633Sdim if (Parser.getTok().isNot(AsmToken::LCurly)) 3257226633Sdim return MatchOperand_NoMatch; 3258226633Sdim Parser.Lex(); // Eat the '{' 3259218893Sdim 3260226633Sdim const MCExpr *Expr; 3261226633Sdim SMLoc Loc = Parser.getTok().getLoc(); 3262249423Sdim if (getParser().parseExpression(Expr)) { 3263226633Sdim Error(Loc, "illegal expression"); 3264226633Sdim return MatchOperand_ParseFail; 3265226633Sdim } 3266226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 3267226633Sdim if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 3268226633Sdim Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 3269226633Sdim return MatchOperand_ParseFail; 3270226633Sdim } 3271226633Sdim int Val = CE->getValue(); 3272218893Sdim 3273226633Sdim // Check for and consume the closing '}' 3274226633Sdim if (Parser.getTok().isNot(AsmToken::RCurly)) 3275226633Sdim return MatchOperand_ParseFail; 3276249423Sdim SMLoc E = Parser.getTok().getEndLoc(); 3277226633Sdim Parser.Lex(); // Eat the '}' 3278198090Srdivacky 3279226633Sdim Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 3280226633Sdim return MatchOperand_Success; 3281226633Sdim} 3282198090Srdivacky 3283226633Sdim// For register list parsing, we need to map from raw GPR register numbering 3284226633Sdim// to the enumeration values. The enumeration values aren't sorted by 3285226633Sdim// register number due to our using "sp", "lr" and "pc" as canonical names. 3286226633Sdimstatic unsigned getNextRegister(unsigned Reg) { 3287226633Sdim // If this is a GPR, we need to do it manually, otherwise we can rely 3288226633Sdim // on the sort ordering of the enumeration since the other reg-classes 3289226633Sdim // are sane. 3290226633Sdim if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3291226633Sdim return Reg + 1; 3292226633Sdim switch(Reg) { 3293234353Sdim default: llvm_unreachable("Invalid GPR number!"); 3294226633Sdim case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 3295226633Sdim case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 3296226633Sdim case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 3297226633Sdim case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 3298226633Sdim case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 3299226633Sdim case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 3300226633Sdim case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 3301226633Sdim case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 3302198090Srdivacky } 3303226633Sdim} 3304198090Srdivacky 3305234353Sdim// Return the low-subreg of a given Q register. 3306234353Sdimstatic unsigned getDRegFromQReg(unsigned QReg) { 3307234353Sdim switch (QReg) { 3308234353Sdim default: llvm_unreachable("expected a Q register!"); 3309234353Sdim case ARM::Q0: return ARM::D0; 3310234353Sdim case ARM::Q1: return ARM::D2; 3311234353Sdim case ARM::Q2: return ARM::D4; 3312234353Sdim case ARM::Q3: return ARM::D6; 3313234353Sdim case ARM::Q4: return ARM::D8; 3314234353Sdim case ARM::Q5: return ARM::D10; 3315234353Sdim case ARM::Q6: return ARM::D12; 3316234353Sdim case ARM::Q7: return ARM::D14; 3317234353Sdim case ARM::Q8: return ARM::D16; 3318234353Sdim case ARM::Q9: return ARM::D18; 3319234353Sdim case ARM::Q10: return ARM::D20; 3320234353Sdim case ARM::Q11: return ARM::D22; 3321234353Sdim case ARM::Q12: return ARM::D24; 3322234353Sdim case ARM::Q13: return ARM::D26; 3323234353Sdim case ARM::Q14: return ARM::D28; 3324234353Sdim case ARM::Q15: return ARM::D30; 3325234353Sdim } 3326234353Sdim} 3327234353Sdim 3328226633Sdim/// Parse a register list. 3329276479Sdimbool ARMAsmParser::parseRegisterList(OperandVector &Operands) { 3330280031Sdim MCAsmParser &Parser = getParser(); 3331226633Sdim assert(Parser.getTok().is(AsmToken::LCurly) && 3332226633Sdim "Token is not a Left Curly Brace"); 3333226633Sdim SMLoc S = Parser.getTok().getLoc(); 3334226633Sdim Parser.Lex(); // Eat '{' token. 3335226633Sdim SMLoc RegLoc = Parser.getTok().getLoc(); 3336218893Sdim 3337226633Sdim // Check the first register in the list to see what register class 3338226633Sdim // this is a list of. 3339226633Sdim int Reg = tryParseRegister(); 3340226633Sdim if (Reg == -1) 3341226633Sdim return Error(RegLoc, "register expected"); 3342218893Sdim 3343234353Sdim // The reglist instructions have at most 16 registers, so reserve 3344234353Sdim // space for that many. 3345261991Sdim int EReg = 0; 3346261991Sdim SmallVector<std::pair<unsigned, unsigned>, 16> Registers; 3347234353Sdim 3348234353Sdim // Allow Q regs and just interpret them as the two D sub-registers. 3349234353Sdim if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3350234353Sdim Reg = getDRegFromQReg(Reg); 3351261991Sdim EReg = MRI->getEncodingValue(Reg); 3352261991Sdim Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3353234353Sdim ++Reg; 3354234353Sdim } 3355234353Sdim const MCRegisterClass *RC; 3356226633Sdim if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3357226633Sdim RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 3358226633Sdim else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 3359226633Sdim RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 3360226633Sdim else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 3361226633Sdim RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 3362226633Sdim else 3363226633Sdim return Error(RegLoc, "invalid register in register list"); 3364218893Sdim 3365234353Sdim // Store the register. 3366261991Sdim EReg = MRI->getEncodingValue(Reg); 3367261991Sdim Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3368218893Sdim 3369226633Sdim // This starts immediately after the first register token in the list, 3370226633Sdim // so we can see either a comma or a minus (range separator) as a legal 3371226633Sdim // next token. 3372226633Sdim while (Parser.getTok().is(AsmToken::Comma) || 3373226633Sdim Parser.getTok().is(AsmToken::Minus)) { 3374226633Sdim if (Parser.getTok().is(AsmToken::Minus)) { 3375234353Sdim Parser.Lex(); // Eat the minus. 3376249423Sdim SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3377226633Sdim int EndReg = tryParseRegister(); 3378226633Sdim if (EndReg == -1) 3379249423Sdim return Error(AfterMinusLoc, "register expected"); 3380234353Sdim // Allow Q regs and just interpret them as the two D sub-registers. 3381234353Sdim if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3382234353Sdim EndReg = getDRegFromQReg(EndReg) + 1; 3383226633Sdim // If the register is the same as the start reg, there's nothing 3384226633Sdim // more to do. 3385226633Sdim if (Reg == EndReg) 3386226633Sdim continue; 3387226633Sdim // The register must be in the same register class as the first. 3388226633Sdim if (!RC->contains(EndReg)) 3389249423Sdim return Error(AfterMinusLoc, "invalid register in register list"); 3390226633Sdim // Ranges must go from low to high. 3391239462Sdim if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 3392249423Sdim return Error(AfterMinusLoc, "bad range in register list"); 3393218893Sdim 3394226633Sdim // Add all the registers in the range to the register list. 3395226633Sdim while (Reg != EndReg) { 3396226633Sdim Reg = getNextRegister(Reg); 3397261991Sdim EReg = MRI->getEncodingValue(Reg); 3398261991Sdim Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3399226633Sdim } 3400226633Sdim continue; 3401218893Sdim } 3402226633Sdim Parser.Lex(); // Eat the comma. 3403226633Sdim RegLoc = Parser.getTok().getLoc(); 3404226633Sdim int OldReg = Reg; 3405234353Sdim const AsmToken RegTok = Parser.getTok(); 3406226633Sdim Reg = tryParseRegister(); 3407226633Sdim if (Reg == -1) 3408226633Sdim return Error(RegLoc, "register expected"); 3409234353Sdim // Allow Q regs and just interpret them as the two D sub-registers. 3410234353Sdim bool isQReg = false; 3411234353Sdim if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3412234353Sdim Reg = getDRegFromQReg(Reg); 3413234353Sdim isQReg = true; 3414234353Sdim } 3415226633Sdim // The register must be in the same register class as the first. 3416226633Sdim if (!RC->contains(Reg)) 3417226633Sdim return Error(RegLoc, "invalid register in register list"); 3418226633Sdim // List must be monotonically increasing. 3419239462Sdim if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 3420234353Sdim if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3421234353Sdim Warning(RegLoc, "register list not in ascending order"); 3422234353Sdim else 3423234353Sdim return Error(RegLoc, "register list not in ascending order"); 3424234353Sdim } 3425239462Sdim if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { 3426234353Sdim Warning(RegLoc, "duplicated register (" + RegTok.getString() + 3427234353Sdim ") in register list"); 3428234353Sdim continue; 3429234353Sdim } 3430226633Sdim // VFP register lists must also be contiguous. 3431226633Sdim if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 3432226633Sdim Reg != OldReg + 1) 3433226633Sdim return Error(RegLoc, "non-contiguous register range"); 3434261991Sdim EReg = MRI->getEncodingValue(Reg); 3435261991Sdim Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3436261991Sdim if (isQReg) { 3437261991Sdim EReg = MRI->getEncodingValue(++Reg); 3438261991Sdim Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3439261991Sdim } 3440226633Sdim } 3441218893Sdim 3442226633Sdim if (Parser.getTok().isNot(AsmToken::RCurly)) 3443249423Sdim return Error(Parser.getTok().getLoc(), "'}' expected"); 3444249423Sdim SMLoc E = Parser.getTok().getEndLoc(); 3445226633Sdim Parser.Lex(); // Eat '}' token. 3446218893Sdim 3447234353Sdim // Push the register list operand. 3448218893Sdim Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 3449234353Sdim 3450234353Sdim // The ARM system instruction variants for LDM/STM have a '^' token here. 3451234353Sdim if (Parser.getTok().is(AsmToken::Caret)) { 3452234353Sdim Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 3453234353Sdim Parser.Lex(); // Eat '^' token. 3454234353Sdim } 3455234353Sdim 3456198090Srdivacky return false; 3457198090Srdivacky} 3458198090Srdivacky 3459234353Sdim// Helper function to parse the lane index for vector lists. 3460234353SdimARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3461249423SdimparseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { 3462280031Sdim MCAsmParser &Parser = getParser(); 3463234353Sdim Index = 0; // Always return a defined index value. 3464234353Sdim if (Parser.getTok().is(AsmToken::LBrac)) { 3465234353Sdim Parser.Lex(); // Eat the '['. 3466234353Sdim if (Parser.getTok().is(AsmToken::RBrac)) { 3467234353Sdim // "Dn[]" is the 'all lanes' syntax. 3468234353Sdim LaneKind = AllLanes; 3469249423Sdim EndLoc = Parser.getTok().getEndLoc(); 3470234353Sdim Parser.Lex(); // Eat the ']'. 3471234353Sdim return MatchOperand_Success; 3472234353Sdim } 3473234353Sdim 3474234353Sdim // There's an optional '#' token here. Normally there wouldn't be, but 3475234353Sdim // inline assemble puts one in, and it's friendly to accept that. 3476234353Sdim if (Parser.getTok().is(AsmToken::Hash)) 3477261991Sdim Parser.Lex(); // Eat '#' or '$'. 3478234353Sdim 3479234353Sdim const MCExpr *LaneIndex; 3480234353Sdim SMLoc Loc = Parser.getTok().getLoc(); 3481249423Sdim if (getParser().parseExpression(LaneIndex)) { 3482234353Sdim Error(Loc, "illegal expression"); 3483234353Sdim return MatchOperand_ParseFail; 3484234353Sdim } 3485234353Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 3486234353Sdim if (!CE) { 3487234353Sdim Error(Loc, "lane index must be empty or an integer"); 3488234353Sdim return MatchOperand_ParseFail; 3489234353Sdim } 3490234353Sdim if (Parser.getTok().isNot(AsmToken::RBrac)) { 3491234353Sdim Error(Parser.getTok().getLoc(), "']' expected"); 3492234353Sdim return MatchOperand_ParseFail; 3493234353Sdim } 3494249423Sdim EndLoc = Parser.getTok().getEndLoc(); 3495234353Sdim Parser.Lex(); // Eat the ']'. 3496234353Sdim int64_t Val = CE->getValue(); 3497234353Sdim 3498234353Sdim // FIXME: Make this range check context sensitive for .8, .16, .32. 3499234353Sdim if (Val < 0 || Val > 7) { 3500234353Sdim Error(Parser.getTok().getLoc(), "lane index out of range"); 3501234353Sdim return MatchOperand_ParseFail; 3502234353Sdim } 3503234353Sdim Index = Val; 3504234353Sdim LaneKind = IndexedLane; 3505234353Sdim return MatchOperand_Success; 3506234353Sdim } 3507234353Sdim LaneKind = NoLanes; 3508234353Sdim return MatchOperand_Success; 3509234353Sdim} 3510234353Sdim 3511234353Sdim// parse a vector register list 3512276479SdimARMAsmParser::OperandMatchResultTy 3513276479SdimARMAsmParser::parseVectorList(OperandVector &Operands) { 3514280031Sdim MCAsmParser &Parser = getParser(); 3515234353Sdim VectorLaneTy LaneKind; 3516234353Sdim unsigned LaneIndex; 3517234353Sdim SMLoc S = Parser.getTok().getLoc(); 3518234353Sdim // As an extension (to match gas), support a plain D register or Q register 3519234353Sdim // (without encosing curly braces) as a single or double entry list, 3520234353Sdim // respectively. 3521234353Sdim if (Parser.getTok().is(AsmToken::Identifier)) { 3522249423Sdim SMLoc E = Parser.getTok().getEndLoc(); 3523234353Sdim int Reg = tryParseRegister(); 3524234353Sdim if (Reg == -1) 3525234353Sdim return MatchOperand_NoMatch; 3526234353Sdim if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3527249423Sdim OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3528234353Sdim if (Res != MatchOperand_Success) 3529234353Sdim return Res; 3530234353Sdim switch (LaneKind) { 3531234353Sdim case NoLanes: 3532234353Sdim Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3533234353Sdim break; 3534234353Sdim case AllLanes: 3535234353Sdim Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3536234353Sdim S, E)); 3537234353Sdim break; 3538234353Sdim case IndexedLane: 3539234353Sdim Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3540234353Sdim LaneIndex, 3541234353Sdim false, S, E)); 3542234353Sdim break; 3543234353Sdim } 3544234353Sdim return MatchOperand_Success; 3545234353Sdim } 3546234353Sdim if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3547234353Sdim Reg = getDRegFromQReg(Reg); 3548249423Sdim OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3549234353Sdim if (Res != MatchOperand_Success) 3550234353Sdim return Res; 3551234353Sdim switch (LaneKind) { 3552234353Sdim case NoLanes: 3553234353Sdim Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3554234353Sdim &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3555234353Sdim Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3556234353Sdim break; 3557234353Sdim case AllLanes: 3558234353Sdim Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3559234353Sdim &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3560234353Sdim Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3561234353Sdim S, E)); 3562234353Sdim break; 3563234353Sdim case IndexedLane: 3564234353Sdim Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3565234353Sdim LaneIndex, 3566234353Sdim false, S, E)); 3567234353Sdim break; 3568234353Sdim } 3569234353Sdim return MatchOperand_Success; 3570234353Sdim } 3571234353Sdim Error(S, "vector register expected"); 3572234353Sdim return MatchOperand_ParseFail; 3573234353Sdim } 3574234353Sdim 3575234353Sdim if (Parser.getTok().isNot(AsmToken::LCurly)) 3576234353Sdim return MatchOperand_NoMatch; 3577234353Sdim 3578234353Sdim Parser.Lex(); // Eat '{' token. 3579234353Sdim SMLoc RegLoc = Parser.getTok().getLoc(); 3580234353Sdim 3581234353Sdim int Reg = tryParseRegister(); 3582234353Sdim if (Reg == -1) { 3583234353Sdim Error(RegLoc, "register expected"); 3584234353Sdim return MatchOperand_ParseFail; 3585234353Sdim } 3586234353Sdim unsigned Count = 1; 3587234353Sdim int Spacing = 0; 3588234353Sdim unsigned FirstReg = Reg; 3589234353Sdim // The list is of D registers, but we also allow Q regs and just interpret 3590234353Sdim // them as the two D sub-registers. 3591234353Sdim if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3592234353Sdim FirstReg = Reg = getDRegFromQReg(Reg); 3593234353Sdim Spacing = 1; // double-spacing requires explicit D registers, otherwise 3594234353Sdim // it's ambiguous with four-register single spaced. 3595234353Sdim ++Reg; 3596234353Sdim ++Count; 3597234353Sdim } 3598249423Sdim 3599249423Sdim SMLoc E; 3600249423Sdim if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) 3601234353Sdim return MatchOperand_ParseFail; 3602234353Sdim 3603234353Sdim while (Parser.getTok().is(AsmToken::Comma) || 3604234353Sdim Parser.getTok().is(AsmToken::Minus)) { 3605234353Sdim if (Parser.getTok().is(AsmToken::Minus)) { 3606234353Sdim if (!Spacing) 3607234353Sdim Spacing = 1; // Register range implies a single spaced list. 3608234353Sdim else if (Spacing == 2) { 3609234353Sdim Error(Parser.getTok().getLoc(), 3610234353Sdim "sequential registers in double spaced list"); 3611234353Sdim return MatchOperand_ParseFail; 3612234353Sdim } 3613234353Sdim Parser.Lex(); // Eat the minus. 3614249423Sdim SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3615234353Sdim int EndReg = tryParseRegister(); 3616234353Sdim if (EndReg == -1) { 3617249423Sdim Error(AfterMinusLoc, "register expected"); 3618234353Sdim return MatchOperand_ParseFail; 3619234353Sdim } 3620234353Sdim // Allow Q regs and just interpret them as the two D sub-registers. 3621234353Sdim if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3622234353Sdim EndReg = getDRegFromQReg(EndReg) + 1; 3623234353Sdim // If the register is the same as the start reg, there's nothing 3624234353Sdim // more to do. 3625234353Sdim if (Reg == EndReg) 3626234353Sdim continue; 3627234353Sdim // The register must be in the same register class as the first. 3628234353Sdim if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3629249423Sdim Error(AfterMinusLoc, "invalid register in register list"); 3630234353Sdim return MatchOperand_ParseFail; 3631234353Sdim } 3632234353Sdim // Ranges must go from low to high. 3633234353Sdim if (Reg > EndReg) { 3634249423Sdim Error(AfterMinusLoc, "bad range in register list"); 3635234353Sdim return MatchOperand_ParseFail; 3636234353Sdim } 3637234353Sdim // Parse the lane specifier if present. 3638234353Sdim VectorLaneTy NextLaneKind; 3639234353Sdim unsigned NextLaneIndex; 3640249423Sdim if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3641249423Sdim MatchOperand_Success) 3642234353Sdim return MatchOperand_ParseFail; 3643234353Sdim if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3644249423Sdim Error(AfterMinusLoc, "mismatched lane index in register list"); 3645234353Sdim return MatchOperand_ParseFail; 3646234353Sdim } 3647234353Sdim 3648234353Sdim // Add all the registers in the range to the register list. 3649234353Sdim Count += EndReg - Reg; 3650234353Sdim Reg = EndReg; 3651234353Sdim continue; 3652234353Sdim } 3653234353Sdim Parser.Lex(); // Eat the comma. 3654234353Sdim RegLoc = Parser.getTok().getLoc(); 3655234353Sdim int OldReg = Reg; 3656234353Sdim Reg = tryParseRegister(); 3657234353Sdim if (Reg == -1) { 3658234353Sdim Error(RegLoc, "register expected"); 3659234353Sdim return MatchOperand_ParseFail; 3660234353Sdim } 3661234353Sdim // vector register lists must be contiguous. 3662234353Sdim // It's OK to use the enumeration values directly here rather, as the 3663234353Sdim // VFP register classes have the enum sorted properly. 3664234353Sdim // 3665234353Sdim // The list is of D registers, but we also allow Q regs and just interpret 3666234353Sdim // them as the two D sub-registers. 3667234353Sdim if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3668234353Sdim if (!Spacing) 3669234353Sdim Spacing = 1; // Register range implies a single spaced list. 3670234353Sdim else if (Spacing == 2) { 3671234353Sdim Error(RegLoc, 3672234353Sdim "invalid register in double-spaced list (must be 'D' register')"); 3673234353Sdim return MatchOperand_ParseFail; 3674234353Sdim } 3675234353Sdim Reg = getDRegFromQReg(Reg); 3676234353Sdim if (Reg != OldReg + 1) { 3677234353Sdim Error(RegLoc, "non-contiguous register range"); 3678234353Sdim return MatchOperand_ParseFail; 3679234353Sdim } 3680234353Sdim ++Reg; 3681234353Sdim Count += 2; 3682234353Sdim // Parse the lane specifier if present. 3683234353Sdim VectorLaneTy NextLaneKind; 3684234353Sdim unsigned NextLaneIndex; 3685249423Sdim SMLoc LaneLoc = Parser.getTok().getLoc(); 3686249423Sdim if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3687249423Sdim MatchOperand_Success) 3688234353Sdim return MatchOperand_ParseFail; 3689234353Sdim if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3690249423Sdim Error(LaneLoc, "mismatched lane index in register list"); 3691234353Sdim return MatchOperand_ParseFail; 3692234353Sdim } 3693234353Sdim continue; 3694234353Sdim } 3695234353Sdim // Normal D register. 3696234353Sdim // Figure out the register spacing (single or double) of the list if 3697234353Sdim // we don't know it already. 3698234353Sdim if (!Spacing) 3699234353Sdim Spacing = 1 + (Reg == OldReg + 2); 3700234353Sdim 3701234353Sdim // Just check that it's contiguous and keep going. 3702234353Sdim if (Reg != OldReg + Spacing) { 3703234353Sdim Error(RegLoc, "non-contiguous register range"); 3704234353Sdim return MatchOperand_ParseFail; 3705234353Sdim } 3706234353Sdim ++Count; 3707234353Sdim // Parse the lane specifier if present. 3708234353Sdim VectorLaneTy NextLaneKind; 3709234353Sdim unsigned NextLaneIndex; 3710234353Sdim SMLoc EndLoc = Parser.getTok().getLoc(); 3711249423Sdim if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) 3712234353Sdim return MatchOperand_ParseFail; 3713234353Sdim if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3714234353Sdim Error(EndLoc, "mismatched lane index in register list"); 3715234353Sdim return MatchOperand_ParseFail; 3716234353Sdim } 3717234353Sdim } 3718234353Sdim 3719234353Sdim if (Parser.getTok().isNot(AsmToken::RCurly)) { 3720249423Sdim Error(Parser.getTok().getLoc(), "'}' expected"); 3721234353Sdim return MatchOperand_ParseFail; 3722234353Sdim } 3723249423Sdim E = Parser.getTok().getEndLoc(); 3724234353Sdim Parser.Lex(); // Eat '}' token. 3725234353Sdim 3726234353Sdim switch (LaneKind) { 3727234353Sdim case NoLanes: 3728234353Sdim // Two-register operands have been converted to the 3729234353Sdim // composite register classes. 3730234353Sdim if (Count == 2) { 3731234353Sdim const MCRegisterClass *RC = (Spacing == 1) ? 3732234353Sdim &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3733234353Sdim &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3734234353Sdim FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3735234353Sdim } 3736234353Sdim 3737234353Sdim Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3738234353Sdim (Spacing == 2), S, E)); 3739234353Sdim break; 3740234353Sdim case AllLanes: 3741234353Sdim // Two-register operands have been converted to the 3742234353Sdim // composite register classes. 3743234353Sdim if (Count == 2) { 3744234353Sdim const MCRegisterClass *RC = (Spacing == 1) ? 3745234353Sdim &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3746234353Sdim &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3747234353Sdim FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3748234353Sdim } 3749234353Sdim Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3750234353Sdim (Spacing == 2), 3751234353Sdim S, E)); 3752234353Sdim break; 3753234353Sdim case IndexedLane: 3754234353Sdim Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3755234353Sdim LaneIndex, 3756234353Sdim (Spacing == 2), 3757234353Sdim S, E)); 3758234353Sdim break; 3759234353Sdim } 3760234353Sdim return MatchOperand_Success; 3761234353Sdim} 3762234353Sdim 3763226633Sdim/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3764276479SdimARMAsmParser::OperandMatchResultTy 3765276479SdimARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { 3766280031Sdim MCAsmParser &Parser = getParser(); 3767218893Sdim SMLoc S = Parser.getTok().getLoc(); 3768218893Sdim const AsmToken &Tok = Parser.getTok(); 3769239462Sdim unsigned Opt; 3770218893Sdim 3771239462Sdim if (Tok.is(AsmToken::Identifier)) { 3772239462Sdim StringRef OptStr = Tok.getString(); 3773218893Sdim 3774239462Sdim Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 3775239462Sdim .Case("sy", ARM_MB::SY) 3776239462Sdim .Case("st", ARM_MB::ST) 3777261991Sdim .Case("ld", ARM_MB::LD) 3778239462Sdim .Case("sh", ARM_MB::ISH) 3779239462Sdim .Case("ish", ARM_MB::ISH) 3780239462Sdim .Case("shst", ARM_MB::ISHST) 3781239462Sdim .Case("ishst", ARM_MB::ISHST) 3782261991Sdim .Case("ishld", ARM_MB::ISHLD) 3783239462Sdim .Case("nsh", ARM_MB::NSH) 3784239462Sdim .Case("un", ARM_MB::NSH) 3785239462Sdim .Case("nshst", ARM_MB::NSHST) 3786261991Sdim .Case("nshld", ARM_MB::NSHLD) 3787239462Sdim .Case("unst", ARM_MB::NSHST) 3788239462Sdim .Case("osh", ARM_MB::OSH) 3789239462Sdim .Case("oshst", ARM_MB::OSHST) 3790261991Sdim .Case("oshld", ARM_MB::OSHLD) 3791239462Sdim .Default(~0U); 3792218893Sdim 3793261991Sdim // ishld, oshld, nshld and ld are only available from ARMv8. 3794261991Sdim if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD || 3795261991Sdim Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD)) 3796261991Sdim Opt = ~0U; 3797261991Sdim 3798239462Sdim if (Opt == ~0U) 3799239462Sdim return MatchOperand_NoMatch; 3800239462Sdim 3801239462Sdim Parser.Lex(); // Eat identifier token. 3802239462Sdim } else if (Tok.is(AsmToken::Hash) || 3803239462Sdim Tok.is(AsmToken::Dollar) || 3804239462Sdim Tok.is(AsmToken::Integer)) { 3805239462Sdim if (Parser.getTok().isNot(AsmToken::Integer)) 3806261991Sdim Parser.Lex(); // Eat '#' or '$'. 3807239462Sdim SMLoc Loc = Parser.getTok().getLoc(); 3808239462Sdim 3809239462Sdim const MCExpr *MemBarrierID; 3810249423Sdim if (getParser().parseExpression(MemBarrierID)) { 3811239462Sdim Error(Loc, "illegal expression"); 3812239462Sdim return MatchOperand_ParseFail; 3813239462Sdim } 3814276479Sdim 3815239462Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 3816239462Sdim if (!CE) { 3817239462Sdim Error(Loc, "constant expression expected"); 3818239462Sdim return MatchOperand_ParseFail; 3819239462Sdim } 3820239462Sdim 3821239462Sdim int Val = CE->getValue(); 3822239462Sdim if (Val & ~0xf) { 3823239462Sdim Error(Loc, "immediate value out of range"); 3824239462Sdim return MatchOperand_ParseFail; 3825239462Sdim } 3826239462Sdim 3827239462Sdim Opt = ARM_MB::RESERVED_0 + Val; 3828239462Sdim } else 3829239462Sdim return MatchOperand_ParseFail; 3830239462Sdim 3831218893Sdim Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3832218893Sdim return MatchOperand_Success; 3833218893Sdim} 3834218893Sdim 3835261991Sdim/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. 3836276479SdimARMAsmParser::OperandMatchResultTy 3837276479SdimARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { 3838280031Sdim MCAsmParser &Parser = getParser(); 3839261991Sdim SMLoc S = Parser.getTok().getLoc(); 3840261991Sdim const AsmToken &Tok = Parser.getTok(); 3841261991Sdim unsigned Opt; 3842261991Sdim 3843261991Sdim if (Tok.is(AsmToken::Identifier)) { 3844261991Sdim StringRef OptStr = Tok.getString(); 3845261991Sdim 3846261991Sdim if (OptStr.equals_lower("sy")) 3847261991Sdim Opt = ARM_ISB::SY; 3848261991Sdim else 3849261991Sdim return MatchOperand_NoMatch; 3850261991Sdim 3851261991Sdim Parser.Lex(); // Eat identifier token. 3852261991Sdim } else if (Tok.is(AsmToken::Hash) || 3853261991Sdim Tok.is(AsmToken::Dollar) || 3854261991Sdim Tok.is(AsmToken::Integer)) { 3855261991Sdim if (Parser.getTok().isNot(AsmToken::Integer)) 3856261991Sdim Parser.Lex(); // Eat '#' or '$'. 3857261991Sdim SMLoc Loc = Parser.getTok().getLoc(); 3858261991Sdim 3859261991Sdim const MCExpr *ISBarrierID; 3860261991Sdim if (getParser().parseExpression(ISBarrierID)) { 3861261991Sdim Error(Loc, "illegal expression"); 3862261991Sdim return MatchOperand_ParseFail; 3863261991Sdim } 3864261991Sdim 3865261991Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID); 3866261991Sdim if (!CE) { 3867261991Sdim Error(Loc, "constant expression expected"); 3868261991Sdim return MatchOperand_ParseFail; 3869261991Sdim } 3870261991Sdim 3871261991Sdim int Val = CE->getValue(); 3872261991Sdim if (Val & ~0xf) { 3873261991Sdim Error(Loc, "immediate value out of range"); 3874261991Sdim return MatchOperand_ParseFail; 3875261991Sdim } 3876261991Sdim 3877261991Sdim Opt = ARM_ISB::RESERVED_0 + Val; 3878261991Sdim } else 3879261991Sdim return MatchOperand_ParseFail; 3880261991Sdim 3881261991Sdim Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( 3882261991Sdim (ARM_ISB::InstSyncBOpt)Opt, S)); 3883261991Sdim return MatchOperand_Success; 3884261991Sdim} 3885261991Sdim 3886261991Sdim 3887226633Sdim/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3888276479SdimARMAsmParser::OperandMatchResultTy 3889276479SdimARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { 3890280031Sdim MCAsmParser &Parser = getParser(); 3891218893Sdim SMLoc S = Parser.getTok().getLoc(); 3892218893Sdim const AsmToken &Tok = Parser.getTok(); 3893239462Sdim if (!Tok.is(AsmToken::Identifier)) 3894239462Sdim return MatchOperand_NoMatch; 3895218893Sdim StringRef IFlagsStr = Tok.getString(); 3896218893Sdim 3897226633Sdim // An iflags string of "none" is interpreted to mean that none of the AIF 3898226633Sdim // bits are set. Not a terribly useful instruction, but a valid encoding. 3899218893Sdim unsigned IFlags = 0; 3900226633Sdim if (IFlagsStr != "none") { 3901226633Sdim for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3902226633Sdim unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3903226633Sdim .Case("a", ARM_PROC::A) 3904226633Sdim .Case("i", ARM_PROC::I) 3905226633Sdim .Case("f", ARM_PROC::F) 3906226633Sdim .Default(~0U); 3907218893Sdim 3908226633Sdim // If some specific iflag is already set, it means that some letter is 3909226633Sdim // present more than once, this is not acceptable. 3910226633Sdim if (Flag == ~0U || (IFlags & Flag)) 3911226633Sdim return MatchOperand_NoMatch; 3912218893Sdim 3913226633Sdim IFlags |= Flag; 3914226633Sdim } 3915218893Sdim } 3916218893Sdim 3917218893Sdim Parser.Lex(); // Eat identifier token. 3918218893Sdim Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3919218893Sdim return MatchOperand_Success; 3920218893Sdim} 3921218893Sdim 3922226633Sdim/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3923276479SdimARMAsmParser::OperandMatchResultTy 3924276479SdimARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { 3925280031Sdim MCAsmParser &Parser = getParser(); 3926218893Sdim SMLoc S = Parser.getTok().getLoc(); 3927218893Sdim const AsmToken &Tok = Parser.getTok(); 3928243830Sdim if (!Tok.is(AsmToken::Identifier)) 3929243830Sdim return MatchOperand_NoMatch; 3930218893Sdim StringRef Mask = Tok.getString(); 3931218893Sdim 3932226633Sdim if (isMClass()) { 3933226633Sdim // See ARMv6-M 10.1.1 3934234353Sdim std::string Name = Mask.lower(); 3935234353Sdim unsigned FlagsVal = StringSwitch<unsigned>(Name) 3936239462Sdim // Note: in the documentation: 3937239462Sdim // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 3938239462Sdim // for MSR APSR_nzcvq. 3939239462Sdim // but we do make it an alias here. This is so to get the "mask encoding" 3940239462Sdim // bits correct on MSR APSR writes. 3941239462Sdim // 3942239462Sdim // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 3943239462Sdim // should really only be allowed when writing a special register. Note 3944239462Sdim // they get dropped in the MRS instruction reading a special register as 3945239462Sdim // the SYSm field is only 8 bits. 3946239462Sdim .Case("apsr", 0x800) 3947239462Sdim .Case("apsr_nzcvq", 0x800) 3948239462Sdim .Case("apsr_g", 0x400) 3949239462Sdim .Case("apsr_nzcvqg", 0xc00) 3950239462Sdim .Case("iapsr", 0x801) 3951239462Sdim .Case("iapsr_nzcvq", 0x801) 3952239462Sdim .Case("iapsr_g", 0x401) 3953239462Sdim .Case("iapsr_nzcvqg", 0xc01) 3954239462Sdim .Case("eapsr", 0x802) 3955239462Sdim .Case("eapsr_nzcvq", 0x802) 3956239462Sdim .Case("eapsr_g", 0x402) 3957239462Sdim .Case("eapsr_nzcvqg", 0xc02) 3958239462Sdim .Case("xpsr", 0x803) 3959239462Sdim .Case("xpsr_nzcvq", 0x803) 3960239462Sdim .Case("xpsr_g", 0x403) 3961239462Sdim .Case("xpsr_nzcvqg", 0xc03) 3962239462Sdim .Case("ipsr", 0x805) 3963239462Sdim .Case("epsr", 0x806) 3964239462Sdim .Case("iepsr", 0x807) 3965239462Sdim .Case("msp", 0x808) 3966239462Sdim .Case("psp", 0x809) 3967239462Sdim .Case("primask", 0x810) 3968239462Sdim .Case("basepri", 0x811) 3969239462Sdim .Case("basepri_max", 0x812) 3970239462Sdim .Case("faultmask", 0x813) 3971239462Sdim .Case("control", 0x814) 3972226633Sdim .Default(~0U); 3973234353Sdim 3974226633Sdim if (FlagsVal == ~0U) 3975226633Sdim return MatchOperand_NoMatch; 3976226633Sdim 3977296417Sdim if (!hasDSP() && (FlagsVal & 0x400)) 3978280031Sdim // The _g and _nzcvqg versions are only valid if the DSP extension is 3979280031Sdim // available. 3980280031Sdim return MatchOperand_NoMatch; 3981280031Sdim 3982239462Sdim if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 3983226633Sdim // basepri, basepri_max and faultmask only valid for V7m. 3984226633Sdim return MatchOperand_NoMatch; 3985234353Sdim 3986226633Sdim Parser.Lex(); // Eat identifier token. 3987226633Sdim Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3988226633Sdim return MatchOperand_Success; 3989226633Sdim } 3990226633Sdim 3991218893Sdim // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3992218893Sdim size_t Start = 0, Next = Mask.find('_'); 3993218893Sdim StringRef Flags = ""; 3994234353Sdim std::string SpecReg = Mask.slice(Start, Next).lower(); 3995218893Sdim if (Next != StringRef::npos) 3996218893Sdim Flags = Mask.slice(Next+1, Mask.size()); 3997218893Sdim 3998218893Sdim // FlagsVal contains the complete mask: 3999218893Sdim // 3-0: Mask 4000218893Sdim // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 4001218893Sdim unsigned FlagsVal = 0; 4002218893Sdim 4003218893Sdim if (SpecReg == "apsr") { 4004218893Sdim FlagsVal = StringSwitch<unsigned>(Flags) 4005226633Sdim .Case("nzcvq", 0x8) // same as CPSR_f 4006218893Sdim .Case("g", 0x4) // same as CPSR_s 4007218893Sdim .Case("nzcvqg", 0xc) // same as CPSR_fs 4008218893Sdim .Default(~0U); 4009218893Sdim 4010218893Sdim if (FlagsVal == ~0U) { 4011218893Sdim if (!Flags.empty()) 4012218893Sdim return MatchOperand_NoMatch; 4013218893Sdim else 4014226633Sdim FlagsVal = 8; // No flag 4015218893Sdim } 4016218893Sdim } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 4017234353Sdim // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 4018234353Sdim if (Flags == "all" || Flags == "") 4019223017Sdim Flags = "fc"; 4020218893Sdim for (int i = 0, e = Flags.size(); i != e; ++i) { 4021218893Sdim unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 4022218893Sdim .Case("c", 1) 4023218893Sdim .Case("x", 2) 4024218893Sdim .Case("s", 4) 4025218893Sdim .Case("f", 8) 4026218893Sdim .Default(~0U); 4027218893Sdim 4028218893Sdim // If some specific flag is already set, it means that some letter is 4029218893Sdim // present more than once, this is not acceptable. 4030218893Sdim if (FlagsVal == ~0U || (FlagsVal & Flag)) 4031218893Sdim return MatchOperand_NoMatch; 4032218893Sdim FlagsVal |= Flag; 4033218893Sdim } 4034218893Sdim } else // No match for special register. 4035218893Sdim return MatchOperand_NoMatch; 4036218893Sdim 4037234353Sdim // Special register without flags is NOT equivalent to "fc" flags. 4038234353Sdim // NOTE: This is a divergence from gas' behavior. Uncommenting the following 4039234353Sdim // two lines would enable gas compatibility at the expense of breaking 4040234353Sdim // round-tripping. 4041234353Sdim // 4042234353Sdim // if (!FlagsVal) 4043234353Sdim // FlagsVal = 0x9; 4044218893Sdim 4045218893Sdim // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 4046218893Sdim if (SpecReg == "spsr") 4047218893Sdim FlagsVal |= 16; 4048218893Sdim 4049218893Sdim Parser.Lex(); // Eat identifier token. 4050218893Sdim Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 4051218893Sdim return MatchOperand_Success; 4052218893Sdim} 4053218893Sdim 4054280031Sdim/// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for 4055280031Sdim/// use in the MRS/MSR instructions added to support virtualization. 4056276479SdimARMAsmParser::OperandMatchResultTy 4057280031SdimARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { 4058280031Sdim MCAsmParser &Parser = getParser(); 4059280031Sdim SMLoc S = Parser.getTok().getLoc(); 4060280031Sdim const AsmToken &Tok = Parser.getTok(); 4061280031Sdim if (!Tok.is(AsmToken::Identifier)) 4062280031Sdim return MatchOperand_NoMatch; 4063280031Sdim StringRef RegName = Tok.getString(); 4064280031Sdim 4065280031Sdim // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM 4066280031Sdim // and bit 5 is R. 4067280031Sdim unsigned Encoding = StringSwitch<unsigned>(RegName.lower()) 4068280031Sdim .Case("r8_usr", 0x00) 4069280031Sdim .Case("r9_usr", 0x01) 4070280031Sdim .Case("r10_usr", 0x02) 4071280031Sdim .Case("r11_usr", 0x03) 4072280031Sdim .Case("r12_usr", 0x04) 4073280031Sdim .Case("sp_usr", 0x05) 4074280031Sdim .Case("lr_usr", 0x06) 4075280031Sdim .Case("r8_fiq", 0x08) 4076280031Sdim .Case("r9_fiq", 0x09) 4077280031Sdim .Case("r10_fiq", 0x0a) 4078280031Sdim .Case("r11_fiq", 0x0b) 4079280031Sdim .Case("r12_fiq", 0x0c) 4080280031Sdim .Case("sp_fiq", 0x0d) 4081280031Sdim .Case("lr_fiq", 0x0e) 4082280031Sdim .Case("lr_irq", 0x10) 4083280031Sdim .Case("sp_irq", 0x11) 4084280031Sdim .Case("lr_svc", 0x12) 4085280031Sdim .Case("sp_svc", 0x13) 4086280031Sdim .Case("lr_abt", 0x14) 4087280031Sdim .Case("sp_abt", 0x15) 4088280031Sdim .Case("lr_und", 0x16) 4089280031Sdim .Case("sp_und", 0x17) 4090280031Sdim .Case("lr_mon", 0x1c) 4091280031Sdim .Case("sp_mon", 0x1d) 4092280031Sdim .Case("elr_hyp", 0x1e) 4093280031Sdim .Case("sp_hyp", 0x1f) 4094280031Sdim .Case("spsr_fiq", 0x2e) 4095280031Sdim .Case("spsr_irq", 0x30) 4096280031Sdim .Case("spsr_svc", 0x32) 4097280031Sdim .Case("spsr_abt", 0x34) 4098280031Sdim .Case("spsr_und", 0x36) 4099280031Sdim .Case("spsr_mon", 0x3c) 4100280031Sdim .Case("spsr_hyp", 0x3e) 4101280031Sdim .Default(~0U); 4102280031Sdim 4103280031Sdim if (Encoding == ~0U) 4104280031Sdim return MatchOperand_NoMatch; 4105280031Sdim 4106280031Sdim Parser.Lex(); // Eat identifier token. 4107280031Sdim Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); 4108280031Sdim return MatchOperand_Success; 4109280031Sdim} 4110280031Sdim 4111280031SdimARMAsmParser::OperandMatchResultTy 4112276479SdimARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, 4113276479Sdim int High) { 4114280031Sdim MCAsmParser &Parser = getParser(); 4115226633Sdim const AsmToken &Tok = Parser.getTok(); 4116226633Sdim if (Tok.isNot(AsmToken::Identifier)) { 4117226633Sdim Error(Parser.getTok().getLoc(), Op + " operand expected."); 4118226633Sdim return MatchOperand_ParseFail; 4119226633Sdim } 4120226633Sdim StringRef ShiftName = Tok.getString(); 4121234353Sdim std::string LowerOp = Op.lower(); 4122234353Sdim std::string UpperOp = Op.upper(); 4123226633Sdim if (ShiftName != LowerOp && ShiftName != UpperOp) { 4124226633Sdim Error(Parser.getTok().getLoc(), Op + " operand expected."); 4125226633Sdim return MatchOperand_ParseFail; 4126226633Sdim } 4127226633Sdim Parser.Lex(); // Eat shift type token. 4128221345Sdim 4129226633Sdim // There must be a '#' and a shift amount. 4130234353Sdim if (Parser.getTok().isNot(AsmToken::Hash) && 4131234353Sdim Parser.getTok().isNot(AsmToken::Dollar)) { 4132226633Sdim Error(Parser.getTok().getLoc(), "'#' expected"); 4133226633Sdim return MatchOperand_ParseFail; 4134226633Sdim } 4135226633Sdim Parser.Lex(); // Eat hash token. 4136221345Sdim 4137226633Sdim const MCExpr *ShiftAmount; 4138226633Sdim SMLoc Loc = Parser.getTok().getLoc(); 4139249423Sdim SMLoc EndLoc; 4140249423Sdim if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4141226633Sdim Error(Loc, "illegal expression"); 4142226633Sdim return MatchOperand_ParseFail; 4143226633Sdim } 4144226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4145226633Sdim if (!CE) { 4146226633Sdim Error(Loc, "constant expression expected"); 4147226633Sdim return MatchOperand_ParseFail; 4148226633Sdim } 4149226633Sdim int Val = CE->getValue(); 4150226633Sdim if (Val < Low || Val > High) { 4151226633Sdim Error(Loc, "immediate value out of range"); 4152226633Sdim return MatchOperand_ParseFail; 4153226633Sdim } 4154226633Sdim 4155249423Sdim Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); 4156226633Sdim 4157221345Sdim return MatchOperand_Success; 4158221345Sdim} 4159221345Sdim 4160276479SdimARMAsmParser::OperandMatchResultTy 4161276479SdimARMAsmParser::parseSetEndImm(OperandVector &Operands) { 4162280031Sdim MCAsmParser &Parser = getParser(); 4163226633Sdim const AsmToken &Tok = Parser.getTok(); 4164226633Sdim SMLoc S = Tok.getLoc(); 4165226633Sdim if (Tok.isNot(AsmToken::Identifier)) { 4166249423Sdim Error(S, "'be' or 'le' operand expected"); 4167226633Sdim return MatchOperand_ParseFail; 4168226633Sdim } 4169261991Sdim int Val = StringSwitch<int>(Tok.getString().lower()) 4170226633Sdim .Case("be", 1) 4171226633Sdim .Case("le", 0) 4172226633Sdim .Default(-1); 4173226633Sdim Parser.Lex(); // Eat the token. 4174221345Sdim 4175226633Sdim if (Val == -1) { 4176249423Sdim Error(S, "'be' or 'le' operand expected"); 4177226633Sdim return MatchOperand_ParseFail; 4178226633Sdim } 4179288943Sdim Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val, 4180226633Sdim getContext()), 4181249423Sdim S, Tok.getEndLoc())); 4182226633Sdim return MatchOperand_Success; 4183226633Sdim} 4184226633Sdim 4185226633Sdim/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 4186226633Sdim/// instructions. Legal values are: 4187226633Sdim/// lsl #n 'n' in [0,31] 4188226633Sdim/// asr #n 'n' in [1,32] 4189226633Sdim/// n == 32 encoded as n == 0. 4190276479SdimARMAsmParser::OperandMatchResultTy 4191276479SdimARMAsmParser::parseShifterImm(OperandVector &Operands) { 4192280031Sdim MCAsmParser &Parser = getParser(); 4193226633Sdim const AsmToken &Tok = Parser.getTok(); 4194226633Sdim SMLoc S = Tok.getLoc(); 4195226633Sdim if (Tok.isNot(AsmToken::Identifier)) { 4196226633Sdim Error(S, "shift operator 'asr' or 'lsl' expected"); 4197226633Sdim return MatchOperand_ParseFail; 4198226633Sdim } 4199226633Sdim StringRef ShiftName = Tok.getString(); 4200226633Sdim bool isASR; 4201226633Sdim if (ShiftName == "lsl" || ShiftName == "LSL") 4202226633Sdim isASR = false; 4203226633Sdim else if (ShiftName == "asr" || ShiftName == "ASR") 4204226633Sdim isASR = true; 4205226633Sdim else { 4206226633Sdim Error(S, "shift operator 'asr' or 'lsl' expected"); 4207226633Sdim return MatchOperand_ParseFail; 4208226633Sdim } 4209226633Sdim Parser.Lex(); // Eat the operator. 4210226633Sdim 4211226633Sdim // A '#' and a shift amount. 4212234353Sdim if (Parser.getTok().isNot(AsmToken::Hash) && 4213234353Sdim Parser.getTok().isNot(AsmToken::Dollar)) { 4214226633Sdim Error(Parser.getTok().getLoc(), "'#' expected"); 4215226633Sdim return MatchOperand_ParseFail; 4216226633Sdim } 4217226633Sdim Parser.Lex(); // Eat hash token. 4218249423Sdim SMLoc ExLoc = Parser.getTok().getLoc(); 4219226633Sdim 4220226633Sdim const MCExpr *ShiftAmount; 4221249423Sdim SMLoc EndLoc; 4222249423Sdim if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4223249423Sdim Error(ExLoc, "malformed shift expression"); 4224226633Sdim return MatchOperand_ParseFail; 4225226633Sdim } 4226226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4227226633Sdim if (!CE) { 4228249423Sdim Error(ExLoc, "shift amount must be an immediate"); 4229226633Sdim return MatchOperand_ParseFail; 4230226633Sdim } 4231226633Sdim 4232226633Sdim int64_t Val = CE->getValue(); 4233226633Sdim if (isASR) { 4234226633Sdim // Shift amount must be in [1,32] 4235226633Sdim if (Val < 1 || Val > 32) { 4236249423Sdim Error(ExLoc, "'asr' shift amount must be in range [1,32]"); 4237226633Sdim return MatchOperand_ParseFail; 4238226633Sdim } 4239226633Sdim // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 4240226633Sdim if (isThumb() && Val == 32) { 4241249423Sdim Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); 4242226633Sdim return MatchOperand_ParseFail; 4243226633Sdim } 4244226633Sdim if (Val == 32) Val = 0; 4245226633Sdim } else { 4246226633Sdim // Shift amount must be in [1,32] 4247226633Sdim if (Val < 0 || Val > 31) { 4248249423Sdim Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); 4249226633Sdim return MatchOperand_ParseFail; 4250226633Sdim } 4251226633Sdim } 4252226633Sdim 4253249423Sdim Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); 4254226633Sdim 4255226633Sdim return MatchOperand_Success; 4256226633Sdim} 4257226633Sdim 4258226633Sdim/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 4259226633Sdim/// of instructions. Legal values are: 4260226633Sdim/// ror #n 'n' in {0, 8, 16, 24} 4261276479SdimARMAsmParser::OperandMatchResultTy 4262276479SdimARMAsmParser::parseRotImm(OperandVector &Operands) { 4263280031Sdim MCAsmParser &Parser = getParser(); 4264226633Sdim const AsmToken &Tok = Parser.getTok(); 4265226633Sdim SMLoc S = Tok.getLoc(); 4266226633Sdim if (Tok.isNot(AsmToken::Identifier)) 4267221345Sdim return MatchOperand_NoMatch; 4268226633Sdim StringRef ShiftName = Tok.getString(); 4269226633Sdim if (ShiftName != "ror" && ShiftName != "ROR") 4270226633Sdim return MatchOperand_NoMatch; 4271226633Sdim Parser.Lex(); // Eat the operator. 4272221345Sdim 4273226633Sdim // A '#' and a rotate amount. 4274234353Sdim if (Parser.getTok().isNot(AsmToken::Hash) && 4275234353Sdim Parser.getTok().isNot(AsmToken::Dollar)) { 4276226633Sdim Error(Parser.getTok().getLoc(), "'#' expected"); 4277226633Sdim return MatchOperand_ParseFail; 4278226633Sdim } 4279226633Sdim Parser.Lex(); // Eat hash token. 4280249423Sdim SMLoc ExLoc = Parser.getTok().getLoc(); 4281226633Sdim 4282226633Sdim const MCExpr *ShiftAmount; 4283249423Sdim SMLoc EndLoc; 4284249423Sdim if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4285249423Sdim Error(ExLoc, "malformed rotate expression"); 4286226633Sdim return MatchOperand_ParseFail; 4287226633Sdim } 4288226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4289226633Sdim if (!CE) { 4290249423Sdim Error(ExLoc, "rotate amount must be an immediate"); 4291226633Sdim return MatchOperand_ParseFail; 4292226633Sdim } 4293226633Sdim 4294226633Sdim int64_t Val = CE->getValue(); 4295226633Sdim // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 4296226633Sdim // normally, zero is represented in asm by omitting the rotate operand 4297226633Sdim // entirely. 4298226633Sdim if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 4299249423Sdim Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); 4300226633Sdim return MatchOperand_ParseFail; 4301226633Sdim } 4302226633Sdim 4303249423Sdim Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); 4304226633Sdim 4305221345Sdim return MatchOperand_Success; 4306221345Sdim} 4307221345Sdim 4308276479SdimARMAsmParser::OperandMatchResultTy 4309280031SdimARMAsmParser::parseModImm(OperandVector &Operands) { 4310280031Sdim MCAsmParser &Parser = getParser(); 4311280031Sdim MCAsmLexer &Lexer = getLexer(); 4312280031Sdim int64_t Imm1, Imm2; 4313280031Sdim 4314280031Sdim SMLoc S = Parser.getTok().getLoc(); 4315280031Sdim 4316280031Sdim // 1) A mod_imm operand can appear in the place of a register name: 4317280031Sdim // add r0, #mod_imm 4318280031Sdim // add r0, r0, #mod_imm 4319280031Sdim // to correctly handle the latter, we bail out as soon as we see an 4320280031Sdim // identifier. 4321280031Sdim // 4322280031Sdim // 2) Similarly, we do not want to parse into complex operands: 4323280031Sdim // mov r0, #mod_imm 4324280031Sdim // mov r0, :lower16:(_foo) 4325280031Sdim if (Parser.getTok().is(AsmToken::Identifier) || 4326280031Sdim Parser.getTok().is(AsmToken::Colon)) 4327280031Sdim return MatchOperand_NoMatch; 4328280031Sdim 4329280031Sdim // Hash (dollar) is optional as per the ARMARM 4330280031Sdim if (Parser.getTok().is(AsmToken::Hash) || 4331280031Sdim Parser.getTok().is(AsmToken::Dollar)) { 4332280031Sdim // Avoid parsing into complex operands (#:) 4333280031Sdim if (Lexer.peekTok().is(AsmToken::Colon)) 4334280031Sdim return MatchOperand_NoMatch; 4335280031Sdim 4336280031Sdim // Eat the hash (dollar) 4337280031Sdim Parser.Lex(); 4338280031Sdim } 4339280031Sdim 4340280031Sdim SMLoc Sx1, Ex1; 4341280031Sdim Sx1 = Parser.getTok().getLoc(); 4342280031Sdim const MCExpr *Imm1Exp; 4343280031Sdim if (getParser().parseExpression(Imm1Exp, Ex1)) { 4344280031Sdim Error(Sx1, "malformed expression"); 4345280031Sdim return MatchOperand_ParseFail; 4346280031Sdim } 4347280031Sdim 4348280031Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp); 4349280031Sdim 4350280031Sdim if (CE) { 4351280031Sdim // Immediate must fit within 32-bits 4352280031Sdim Imm1 = CE->getValue(); 4353280031Sdim int Enc = ARM_AM::getSOImmVal(Imm1); 4354280031Sdim if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) { 4355280031Sdim // We have a match! 4356280031Sdim Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF), 4357280031Sdim (Enc & 0xF00) >> 7, 4358280031Sdim Sx1, Ex1)); 4359280031Sdim return MatchOperand_Success; 4360280031Sdim } 4361280031Sdim 4362280031Sdim // We have parsed an immediate which is not for us, fallback to a plain 4363280031Sdim // immediate. This can happen for instruction aliases. For an example, 4364280031Sdim // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform 4365280031Sdim // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite 4366280031Sdim // instruction with a mod_imm operand. The alias is defined such that the 4367280031Sdim // parser method is shared, that's why we have to do this here. 4368280031Sdim if (Parser.getTok().is(AsmToken::EndOfStatement)) { 4369280031Sdim Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); 4370280031Sdim return MatchOperand_Success; 4371280031Sdim } 4372280031Sdim } else { 4373280031Sdim // Operands like #(l1 - l2) can only be evaluated at a later stage (via an 4374280031Sdim // MCFixup). Fallback to a plain immediate. 4375280031Sdim Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); 4376280031Sdim return MatchOperand_Success; 4377280031Sdim } 4378280031Sdim 4379280031Sdim // From this point onward, we expect the input to be a (#bits, #rot) pair 4380280031Sdim if (Parser.getTok().isNot(AsmToken::Comma)) { 4381280031Sdim Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]"); 4382280031Sdim return MatchOperand_ParseFail; 4383280031Sdim } 4384280031Sdim 4385280031Sdim if (Imm1 & ~0xFF) { 4386280031Sdim Error(Sx1, "immediate operand must a number in the range [0, 255]"); 4387280031Sdim return MatchOperand_ParseFail; 4388280031Sdim } 4389280031Sdim 4390280031Sdim // Eat the comma 4391280031Sdim Parser.Lex(); 4392280031Sdim 4393280031Sdim // Repeat for #rot 4394280031Sdim SMLoc Sx2, Ex2; 4395280031Sdim Sx2 = Parser.getTok().getLoc(); 4396280031Sdim 4397280031Sdim // Eat the optional hash (dollar) 4398280031Sdim if (Parser.getTok().is(AsmToken::Hash) || 4399280031Sdim Parser.getTok().is(AsmToken::Dollar)) 4400280031Sdim Parser.Lex(); 4401280031Sdim 4402280031Sdim const MCExpr *Imm2Exp; 4403280031Sdim if (getParser().parseExpression(Imm2Exp, Ex2)) { 4404280031Sdim Error(Sx2, "malformed expression"); 4405280031Sdim return MatchOperand_ParseFail; 4406280031Sdim } 4407280031Sdim 4408280031Sdim CE = dyn_cast<MCConstantExpr>(Imm2Exp); 4409280031Sdim 4410280031Sdim if (CE) { 4411280031Sdim Imm2 = CE->getValue(); 4412280031Sdim if (!(Imm2 & ~0x1E)) { 4413280031Sdim // We have a match! 4414280031Sdim Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2)); 4415280031Sdim return MatchOperand_Success; 4416280031Sdim } 4417280031Sdim Error(Sx2, "immediate operand must an even number in the range [0, 30]"); 4418280031Sdim return MatchOperand_ParseFail; 4419280031Sdim } else { 4420280031Sdim Error(Sx2, "constant expression expected"); 4421280031Sdim return MatchOperand_ParseFail; 4422280031Sdim } 4423280031Sdim} 4424280031Sdim 4425280031SdimARMAsmParser::OperandMatchResultTy 4426276479SdimARMAsmParser::parseBitfield(OperandVector &Operands) { 4427280031Sdim MCAsmParser &Parser = getParser(); 4428226633Sdim SMLoc S = Parser.getTok().getLoc(); 4429226633Sdim // The bitfield descriptor is really two operands, the LSB and the width. 4430234353Sdim if (Parser.getTok().isNot(AsmToken::Hash) && 4431234353Sdim Parser.getTok().isNot(AsmToken::Dollar)) { 4432226633Sdim Error(Parser.getTok().getLoc(), "'#' expected"); 4433226633Sdim return MatchOperand_ParseFail; 4434226633Sdim } 4435226633Sdim Parser.Lex(); // Eat hash token. 4436226633Sdim 4437226633Sdim const MCExpr *LSBExpr; 4438226633Sdim SMLoc E = Parser.getTok().getLoc(); 4439249423Sdim if (getParser().parseExpression(LSBExpr)) { 4440226633Sdim Error(E, "malformed immediate expression"); 4441226633Sdim return MatchOperand_ParseFail; 4442226633Sdim } 4443226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 4444226633Sdim if (!CE) { 4445226633Sdim Error(E, "'lsb' operand must be an immediate"); 4446226633Sdim return MatchOperand_ParseFail; 4447226633Sdim } 4448226633Sdim 4449226633Sdim int64_t LSB = CE->getValue(); 4450226633Sdim // The LSB must be in the range [0,31] 4451226633Sdim if (LSB < 0 || LSB > 31) { 4452226633Sdim Error(E, "'lsb' operand must be in the range [0,31]"); 4453226633Sdim return MatchOperand_ParseFail; 4454226633Sdim } 4455226633Sdim E = Parser.getTok().getLoc(); 4456226633Sdim 4457226633Sdim // Expect another immediate operand. 4458226633Sdim if (Parser.getTok().isNot(AsmToken::Comma)) { 4459226633Sdim Error(Parser.getTok().getLoc(), "too few operands"); 4460226633Sdim return MatchOperand_ParseFail; 4461226633Sdim } 4462226633Sdim Parser.Lex(); // Eat hash token. 4463234353Sdim if (Parser.getTok().isNot(AsmToken::Hash) && 4464234353Sdim Parser.getTok().isNot(AsmToken::Dollar)) { 4465226633Sdim Error(Parser.getTok().getLoc(), "'#' expected"); 4466226633Sdim return MatchOperand_ParseFail; 4467226633Sdim } 4468226633Sdim Parser.Lex(); // Eat hash token. 4469226633Sdim 4470226633Sdim const MCExpr *WidthExpr; 4471249423Sdim SMLoc EndLoc; 4472249423Sdim if (getParser().parseExpression(WidthExpr, EndLoc)) { 4473226633Sdim Error(E, "malformed immediate expression"); 4474226633Sdim return MatchOperand_ParseFail; 4475226633Sdim } 4476226633Sdim CE = dyn_cast<MCConstantExpr>(WidthExpr); 4477226633Sdim if (!CE) { 4478226633Sdim Error(E, "'width' operand must be an immediate"); 4479226633Sdim return MatchOperand_ParseFail; 4480226633Sdim } 4481226633Sdim 4482226633Sdim int64_t Width = CE->getValue(); 4483226633Sdim // The LSB must be in the range [1,32-lsb] 4484226633Sdim if (Width < 1 || Width > 32 - LSB) { 4485226633Sdim Error(E, "'width' operand must be in the range [1,32-lsb]"); 4486226633Sdim return MatchOperand_ParseFail; 4487226633Sdim } 4488226633Sdim 4489249423Sdim Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); 4490226633Sdim 4491226633Sdim return MatchOperand_Success; 4492226633Sdim} 4493226633Sdim 4494276479SdimARMAsmParser::OperandMatchResultTy 4495276479SdimARMAsmParser::parsePostIdxReg(OperandVector &Operands) { 4496226633Sdim // Check for a post-index addressing register operand. Specifically: 4497226633Sdim // postidx_reg := '+' register {, shift} 4498226633Sdim // | '-' register {, shift} 4499226633Sdim // | register {, shift} 4500226633Sdim 4501226633Sdim // This method must return MatchOperand_NoMatch without consuming any tokens 4502226633Sdim // in the case where there is no match, as other alternatives take other 4503226633Sdim // parse methods. 4504280031Sdim MCAsmParser &Parser = getParser(); 4505226633Sdim AsmToken Tok = Parser.getTok(); 4506226633Sdim SMLoc S = Tok.getLoc(); 4507226633Sdim bool haveEaten = false; 4508226633Sdim bool isAdd = true; 4509226633Sdim if (Tok.is(AsmToken::Plus)) { 4510226633Sdim Parser.Lex(); // Eat the '+' token. 4511226633Sdim haveEaten = true; 4512226633Sdim } else if (Tok.is(AsmToken::Minus)) { 4513226633Sdim Parser.Lex(); // Eat the '-' token. 4514226633Sdim isAdd = false; 4515226633Sdim haveEaten = true; 4516226633Sdim } 4517249423Sdim 4518249423Sdim SMLoc E = Parser.getTok().getEndLoc(); 4519249423Sdim int Reg = tryParseRegister(); 4520226633Sdim if (Reg == -1) { 4521226633Sdim if (!haveEaten) 4522226633Sdim return MatchOperand_NoMatch; 4523226633Sdim Error(Parser.getTok().getLoc(), "register expected"); 4524226633Sdim return MatchOperand_ParseFail; 4525226633Sdim } 4526226633Sdim 4527226633Sdim ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 4528226633Sdim unsigned ShiftImm = 0; 4529226633Sdim if (Parser.getTok().is(AsmToken::Comma)) { 4530226633Sdim Parser.Lex(); // Eat the ','. 4531226633Sdim if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 4532226633Sdim return MatchOperand_ParseFail; 4533249423Sdim 4534249423Sdim // FIXME: Only approximates end...may include intervening whitespace. 4535249423Sdim E = Parser.getTok().getLoc(); 4536226633Sdim } 4537226633Sdim 4538226633Sdim Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 4539226633Sdim ShiftImm, S, E)); 4540226633Sdim 4541226633Sdim return MatchOperand_Success; 4542226633Sdim} 4543226633Sdim 4544276479SdimARMAsmParser::OperandMatchResultTy 4545276479SdimARMAsmParser::parseAM3Offset(OperandVector &Operands) { 4546226633Sdim // Check for a post-index addressing register operand. Specifically: 4547226633Sdim // am3offset := '+' register 4548226633Sdim // | '-' register 4549226633Sdim // | register 4550226633Sdim // | # imm 4551226633Sdim // | # + imm 4552226633Sdim // | # - imm 4553226633Sdim 4554226633Sdim // This method must return MatchOperand_NoMatch without consuming any tokens 4555226633Sdim // in the case where there is no match, as other alternatives take other 4556226633Sdim // parse methods. 4557280031Sdim MCAsmParser &Parser = getParser(); 4558226633Sdim AsmToken Tok = Parser.getTok(); 4559226633Sdim SMLoc S = Tok.getLoc(); 4560226633Sdim 4561226633Sdim // Do immediates first, as we always parse those if we have a '#'. 4562234353Sdim if (Parser.getTok().is(AsmToken::Hash) || 4563234353Sdim Parser.getTok().is(AsmToken::Dollar)) { 4564261991Sdim Parser.Lex(); // Eat '#' or '$'. 4565226633Sdim // Explicitly look for a '-', as we need to encode negative zero 4566226633Sdim // differently. 4567226633Sdim bool isNegative = Parser.getTok().is(AsmToken::Minus); 4568226633Sdim const MCExpr *Offset; 4569249423Sdim SMLoc E; 4570249423Sdim if (getParser().parseExpression(Offset, E)) 4571226633Sdim return MatchOperand_ParseFail; 4572226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4573226633Sdim if (!CE) { 4574226633Sdim Error(S, "constant expression expected"); 4575226633Sdim return MatchOperand_ParseFail; 4576226633Sdim } 4577226633Sdim // Negative zero is encoded as the flag value INT32_MIN. 4578226633Sdim int32_t Val = CE->getValue(); 4579226633Sdim if (isNegative && Val == 0) 4580226633Sdim Val = INT32_MIN; 4581226633Sdim 4582226633Sdim Operands.push_back( 4583288943Sdim ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E)); 4584226633Sdim 4585226633Sdim return MatchOperand_Success; 4586226633Sdim } 4587226633Sdim 4588226633Sdim 4589226633Sdim bool haveEaten = false; 4590226633Sdim bool isAdd = true; 4591226633Sdim if (Tok.is(AsmToken::Plus)) { 4592226633Sdim Parser.Lex(); // Eat the '+' token. 4593226633Sdim haveEaten = true; 4594226633Sdim } else if (Tok.is(AsmToken::Minus)) { 4595226633Sdim Parser.Lex(); // Eat the '-' token. 4596226633Sdim isAdd = false; 4597226633Sdim haveEaten = true; 4598226633Sdim } 4599276479Sdim 4600249423Sdim Tok = Parser.getTok(); 4601249423Sdim int Reg = tryParseRegister(); 4602226633Sdim if (Reg == -1) { 4603226633Sdim if (!haveEaten) 4604226633Sdim return MatchOperand_NoMatch; 4605249423Sdim Error(Tok.getLoc(), "register expected"); 4606226633Sdim return MatchOperand_ParseFail; 4607226633Sdim } 4608226633Sdim 4609226633Sdim Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 4610249423Sdim 0, S, Tok.getEndLoc())); 4611226633Sdim 4612226633Sdim return MatchOperand_Success; 4613226633Sdim} 4614226633Sdim 4615261991Sdim/// Convert parsed operands to MCInst. Needed here because this instruction 4616261991Sdim/// only has two register operands, but multiplication is commutative so 4617261991Sdim/// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN". 4618276479Sdimvoid ARMAsmParser::cvtThumbMultiply(MCInst &Inst, 4619276479Sdim const OperandVector &Operands) { 4620276479Sdim ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); 4621276479Sdim ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1); 4622234353Sdim // If we have a three-operand form, make sure to set Rn to be the operand 4623234353Sdim // that isn't the same as Rd. 4624234353Sdim unsigned RegOp = 4; 4625234353Sdim if (Operands.size() == 6 && 4626276479Sdim ((ARMOperand &)*Operands[4]).getReg() == 4627276479Sdim ((ARMOperand &)*Operands[3]).getReg()) 4628234353Sdim RegOp = 5; 4629276479Sdim ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); 4630234353Sdim Inst.addOperand(Inst.getOperand(0)); 4631276479Sdim ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2); 4632226633Sdim} 4633226633Sdim 4634276479Sdimvoid ARMAsmParser::cvtThumbBranches(MCInst &Inst, 4635276479Sdim const OperandVector &Operands) { 4636261991Sdim int CondOp = -1, ImmOp = -1; 4637261991Sdim switch(Inst.getOpcode()) { 4638261991Sdim case ARM::tB: 4639261991Sdim case ARM::tBcc: CondOp = 1; ImmOp = 2; break; 4640234353Sdim 4641261991Sdim case ARM::t2B: 4642261991Sdim case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; 4643234353Sdim 4644261991Sdim default: llvm_unreachable("Unexpected instruction in cvtThumbBranches"); 4645261991Sdim } 4646261991Sdim // first decide whether or not the branch should be conditional 4647261991Sdim // by looking at it's location relative to an IT block 4648261991Sdim if(inITBlock()) { 4649261991Sdim // inside an IT block we cannot have any conditional branches. any 4650261991Sdim // such instructions needs to be converted to unconditional form 4651261991Sdim switch(Inst.getOpcode()) { 4652261991Sdim case ARM::tBcc: Inst.setOpcode(ARM::tB); break; 4653261991Sdim case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; 4654261991Sdim } 4655261991Sdim } else { 4656261991Sdim // outside IT blocks we can only have unconditional branches with AL 4657261991Sdim // condition code or conditional branches with non-AL condition code 4658276479Sdim unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); 4659261991Sdim switch(Inst.getOpcode()) { 4660261991Sdim case ARM::tB: 4661261991Sdim case ARM::tBcc: 4662261991Sdim Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); 4663261991Sdim break; 4664261991Sdim case ARM::t2B: 4665261991Sdim case ARM::t2Bcc: 4666261991Sdim Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); 4667261991Sdim break; 4668261991Sdim } 4669261991Sdim } 4670276479Sdim 4671261991Sdim // now decide on encoding size based on branch target range 4672261991Sdim switch(Inst.getOpcode()) { 4673261991Sdim // classify tB as either t2B or t1B based on range of immediate operand 4674261991Sdim case ARM::tB: { 4675276479Sdim ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); 4676276479Sdim if (!op.isSignedOffset<11, 1>() && isThumbTwo()) 4677261991Sdim Inst.setOpcode(ARM::t2B); 4678261991Sdim break; 4679261991Sdim } 4680261991Sdim // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand 4681261991Sdim case ARM::tBcc: { 4682276479Sdim ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); 4683276479Sdim if (!op.isSignedOffset<8, 1>() && isThumbTwo()) 4684261991Sdim Inst.setOpcode(ARM::t2Bcc); 4685261991Sdim break; 4686261991Sdim } 4687261991Sdim } 4688276479Sdim ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); 4689276479Sdim ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2); 4690234353Sdim} 4691234353Sdim 4692218893Sdim/// Parse an ARM memory expression, return false if successful else return true 4693198892Srdivacky/// or an error. The first token must be a '[' when called. 4694276479Sdimbool ARMAsmParser::parseMemory(OperandVector &Operands) { 4695280031Sdim MCAsmParser &Parser = getParser(); 4696206124Srdivacky SMLoc S, E; 4697202878Srdivacky assert(Parser.getTok().is(AsmToken::LBrac) && 4698218893Sdim "Token is not a Left Bracket"); 4699206124Srdivacky S = Parser.getTok().getLoc(); 4700202878Srdivacky Parser.Lex(); // Eat left bracket token. 4701198090Srdivacky 4702202878Srdivacky const AsmToken &BaseRegTok = Parser.getTok(); 4703226633Sdim int BaseRegNum = tryParseRegister(); 4704226633Sdim if (BaseRegNum == -1) 4705226633Sdim return Error(BaseRegTok.getLoc(), "register expected"); 4706198090Srdivacky 4707249423Sdim // The next token must either be a comma, a colon or a closing bracket. 4708218893Sdim const AsmToken &Tok = Parser.getTok(); 4709249423Sdim if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && 4710249423Sdim !Tok.is(AsmToken::RBrac)) 4711226633Sdim return Error(Tok.getLoc(), "malformed memory operand"); 4712218893Sdim 4713226633Sdim if (Tok.is(AsmToken::RBrac)) { 4714249423Sdim E = Tok.getEndLoc(); 4715226633Sdim Parser.Lex(); // Eat right bracket token. 4716198090Srdivacky 4717276479Sdim Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, 4718276479Sdim ARM_AM::no_shift, 0, 0, false, 4719276479Sdim S, E)); 4720218893Sdim 4721226633Sdim // If there's a pre-indexing writeback marker, '!', just add it as a token 4722226633Sdim // operand. It's rather odd, but syntactically valid. 4723226633Sdim if (Parser.getTok().is(AsmToken::Exclaim)) { 4724226633Sdim Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4725226633Sdim Parser.Lex(); // Eat the '!'. 4726218893Sdim } 4727198090Srdivacky 4728226633Sdim return false; 4729226633Sdim } 4730221345Sdim 4731249423Sdim assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && 4732249423Sdim "Lost colon or comma in memory operand?!"); 4733249423Sdim if (Tok.is(AsmToken::Comma)) { 4734249423Sdim Parser.Lex(); // Eat the comma. 4735249423Sdim } 4736218893Sdim 4737226633Sdim // If we have a ':', it's an alignment specifier. 4738226633Sdim if (Parser.getTok().is(AsmToken::Colon)) { 4739226633Sdim Parser.Lex(); // Eat the ':'. 4740226633Sdim E = Parser.getTok().getLoc(); 4741276479Sdim SMLoc AlignmentLoc = Tok.getLoc(); 4742198090Srdivacky 4743226633Sdim const MCExpr *Expr; 4744249423Sdim if (getParser().parseExpression(Expr)) 4745226633Sdim return true; 4746198090Srdivacky 4747226633Sdim // The expression has to be a constant. Memory references with relocations 4748226633Sdim // don't come through here, as they use the <label> forms of the relevant 4749226633Sdim // instructions. 4750226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4751226633Sdim if (!CE) 4752226633Sdim return Error (E, "constant expression expected"); 4753218893Sdim 4754226633Sdim unsigned Align = 0; 4755226633Sdim switch (CE->getValue()) { 4756226633Sdim default: 4757234353Sdim return Error(E, 4758234353Sdim "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4759234353Sdim case 16: Align = 2; break; 4760234353Sdim case 32: Align = 4; break; 4761226633Sdim case 64: Align = 8; break; 4762226633Sdim case 128: Align = 16; break; 4763226633Sdim case 256: Align = 32; break; 4764226633Sdim } 4765218893Sdim 4766226633Sdim // Now we should have the closing ']' 4767226633Sdim if (Parser.getTok().isNot(AsmToken::RBrac)) 4768249423Sdim return Error(Parser.getTok().getLoc(), "']' expected"); 4769249423Sdim E = Parser.getTok().getEndLoc(); 4770226633Sdim Parser.Lex(); // Eat right bracket token. 4771218893Sdim 4772226633Sdim // Don't worry about range checking the value here. That's handled by 4773226633Sdim // the is*() predicates. 4774276479Sdim Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, 4775226633Sdim ARM_AM::no_shift, 0, Align, 4776276479Sdim false, S, E, AlignmentLoc)); 4777226633Sdim 4778226633Sdim // If there's a pre-indexing writeback marker, '!', just add it as a token 4779226633Sdim // operand. 4780226633Sdim if (Parser.getTok().is(AsmToken::Exclaim)) { 4781226633Sdim Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4782226633Sdim Parser.Lex(); // Eat the '!'. 4783198090Srdivacky } 4784198090Srdivacky 4785226633Sdim return false; 4786198090Srdivacky } 4787198090Srdivacky 4788226633Sdim // If we have a '#', it's an immediate offset, else assume it's a register 4789234353Sdim // offset. Be friendly and also accept a plain integer (without a leading 4790234353Sdim // hash) for gas compatibility. 4791234353Sdim if (Parser.getTok().is(AsmToken::Hash) || 4792234353Sdim Parser.getTok().is(AsmToken::Dollar) || 4793234353Sdim Parser.getTok().is(AsmToken::Integer)) { 4794234353Sdim if (Parser.getTok().isNot(AsmToken::Integer)) 4795261991Sdim Parser.Lex(); // Eat '#' or '$'. 4796226633Sdim E = Parser.getTok().getLoc(); 4797218893Sdim 4798226633Sdim bool isNegative = getParser().getTok().is(AsmToken::Minus); 4799226633Sdim const MCExpr *Offset; 4800249423Sdim if (getParser().parseExpression(Offset)) 4801226633Sdim return true; 4802198090Srdivacky 4803226633Sdim // The expression has to be a constant. Memory references with relocations 4804226633Sdim // don't come through here, as they use the <label> forms of the relevant 4805226633Sdim // instructions. 4806226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4807226633Sdim if (!CE) 4808226633Sdim return Error (E, "constant expression expected"); 4809226633Sdim 4810226633Sdim // If the constant was #-0, represent it as INT32_MIN. 4811226633Sdim int32_t Val = CE->getValue(); 4812226633Sdim if (isNegative && Val == 0) 4813288943Sdim CE = MCConstantExpr::create(INT32_MIN, getContext()); 4814226633Sdim 4815226633Sdim // Now we should have the closing ']' 4816226633Sdim if (Parser.getTok().isNot(AsmToken::RBrac)) 4817249423Sdim return Error(Parser.getTok().getLoc(), "']' expected"); 4818249423Sdim E = Parser.getTok().getEndLoc(); 4819226633Sdim Parser.Lex(); // Eat right bracket token. 4820226633Sdim 4821226633Sdim // Don't worry about range checking the value here. That's handled by 4822226633Sdim // the is*() predicates. 4823226633Sdim Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 4824226633Sdim ARM_AM::no_shift, 0, 0, 4825226633Sdim false, S, E)); 4826226633Sdim 4827226633Sdim // If there's a pre-indexing writeback marker, '!', just add it as a token 4828226633Sdim // operand. 4829226633Sdim if (Parser.getTok().is(AsmToken::Exclaim)) { 4830226633Sdim Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4831226633Sdim Parser.Lex(); // Eat the '!'. 4832206124Srdivacky } 4833226633Sdim 4834226633Sdim return false; 4835198892Srdivacky } 4836218893Sdim 4837226633Sdim // The register offset is optionally preceded by a '+' or '-' 4838226633Sdim bool isNegative = false; 4839226633Sdim if (Parser.getTok().is(AsmToken::Minus)) { 4840226633Sdim isNegative = true; 4841226633Sdim Parser.Lex(); // Eat the '-'. 4842226633Sdim } else if (Parser.getTok().is(AsmToken::Plus)) { 4843226633Sdim // Nothing to do. 4844226633Sdim Parser.Lex(); // Eat the '+'. 4845226633Sdim } 4846198892Srdivacky 4847226633Sdim E = Parser.getTok().getLoc(); 4848226633Sdim int OffsetRegNum = tryParseRegister(); 4849226633Sdim if (OffsetRegNum == -1) 4850226633Sdim return Error(E, "register expected"); 4851226633Sdim 4852226633Sdim // If there's a shift operator, handle it. 4853226633Sdim ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 4854226633Sdim unsigned ShiftImm = 0; 4855226633Sdim if (Parser.getTok().is(AsmToken::Comma)) { 4856226633Sdim Parser.Lex(); // Eat the ','. 4857226633Sdim if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 4858226633Sdim return true; 4859198892Srdivacky } 4860218893Sdim 4861226633Sdim // Now we should have the closing ']' 4862226633Sdim if (Parser.getTok().isNot(AsmToken::RBrac)) 4863249423Sdim return Error(Parser.getTok().getLoc(), "']' expected"); 4864249423Sdim E = Parser.getTok().getEndLoc(); 4865226633Sdim Parser.Lex(); // Eat right bracket token. 4866198892Srdivacky 4867276479Sdim Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum, 4868226633Sdim ShiftType, ShiftImm, 0, isNegative, 4869226633Sdim S, E)); 4870226633Sdim 4871226633Sdim // If there's a pre-indexing writeback marker, '!', just add it as a token 4872226633Sdim // operand. 4873226633Sdim if (Parser.getTok().is(AsmToken::Exclaim)) { 4874226633Sdim Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4875226633Sdim Parser.Lex(); // Eat the '!'. 4876198892Srdivacky } 4877226633Sdim 4878198892Srdivacky return false; 4879198892Srdivacky} 4880198892Srdivacky 4881226633Sdim/// parseMemRegOffsetShift - one of these two: 4882198090Srdivacky/// ( lsl | lsr | asr | ror ) , # shift_amount 4883198090Srdivacky/// rrx 4884226633Sdim/// return true if it parses a shift otherwise it returns false. 4885226633Sdimbool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 4886226633Sdim unsigned &Amount) { 4887280031Sdim MCAsmParser &Parser = getParser(); 4888226633Sdim SMLoc Loc = Parser.getTok().getLoc(); 4889202878Srdivacky const AsmToken &Tok = Parser.getTok(); 4890198090Srdivacky if (Tok.isNot(AsmToken::Identifier)) 4891198090Srdivacky return true; 4892210299Sed StringRef ShiftName = Tok.getString(); 4893234353Sdim if (ShiftName == "lsl" || ShiftName == "LSL" || 4894234353Sdim ShiftName == "asl" || ShiftName == "ASL") 4895221345Sdim St = ARM_AM::lsl; 4896198090Srdivacky else if (ShiftName == "lsr" || ShiftName == "LSR") 4897221345Sdim St = ARM_AM::lsr; 4898198090Srdivacky else if (ShiftName == "asr" || ShiftName == "ASR") 4899221345Sdim St = ARM_AM::asr; 4900198090Srdivacky else if (ShiftName == "ror" || ShiftName == "ROR") 4901221345Sdim St = ARM_AM::ror; 4902198090Srdivacky else if (ShiftName == "rrx" || ShiftName == "RRX") 4903221345Sdim St = ARM_AM::rrx; 4904198090Srdivacky else 4905226633Sdim return Error(Loc, "illegal shift operator"); 4906202878Srdivacky Parser.Lex(); // Eat shift type token. 4907198090Srdivacky 4908226633Sdim // rrx stands alone. 4909226633Sdim Amount = 0; 4910226633Sdim if (St != ARM_AM::rrx) { 4911226633Sdim Loc = Parser.getTok().getLoc(); 4912226633Sdim // A '#' and a shift amount. 4913226633Sdim const AsmToken &HashTok = Parser.getTok(); 4914234353Sdim if (HashTok.isNot(AsmToken::Hash) && 4915234353Sdim HashTok.isNot(AsmToken::Dollar)) 4916226633Sdim return Error(HashTok.getLoc(), "'#' expected"); 4917226633Sdim Parser.Lex(); // Eat hash token. 4918198090Srdivacky 4919226633Sdim const MCExpr *Expr; 4920249423Sdim if (getParser().parseExpression(Expr)) 4921226633Sdim return true; 4922226633Sdim // Range check the immediate. 4923226633Sdim // lsl, ror: 0 <= imm <= 31 4924226633Sdim // lsr, asr: 0 <= imm <= 32 4925226633Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4926226633Sdim if (!CE) 4927226633Sdim return Error(Loc, "shift amount must be an immediate"); 4928226633Sdim int64_t Imm = CE->getValue(); 4929226633Sdim if (Imm < 0 || 4930226633Sdim ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 4931226633Sdim ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 4932226633Sdim return Error(Loc, "immediate shift value out of range"); 4933243830Sdim // If <ShiftTy> #0, turn it into a no_shift. 4934243830Sdim if (Imm == 0) 4935243830Sdim St = ARM_AM::lsl; 4936243830Sdim // For consistency, treat lsr #32 and asr #32 as having immediate value 0. 4937243830Sdim if (Imm == 32) 4938243830Sdim Imm = 0; 4939226633Sdim Amount = Imm; 4940226633Sdim } 4941198090Srdivacky 4942198090Srdivacky return false; 4943198090Srdivacky} 4944198090Srdivacky 4945226633Sdim/// parseFPImm - A floating point immediate expression operand. 4946276479SdimARMAsmParser::OperandMatchResultTy 4947276479SdimARMAsmParser::parseFPImm(OperandVector &Operands) { 4948280031Sdim MCAsmParser &Parser = getParser(); 4949234353Sdim // Anything that can accept a floating point constant as an operand 4950249423Sdim // needs to go through here, as the regular parseExpression is 4951234353Sdim // integer only. 4952234353Sdim // 4953234353Sdim // This routine still creates a generic Immediate operand, containing 4954234353Sdim // a bitcast of the 64-bit floating point value. The various operands 4955234353Sdim // that accept floats can check whether the value is valid for them 4956234353Sdim // via the standard is*() predicates. 4957234353Sdim 4958226633Sdim SMLoc S = Parser.getTok().getLoc(); 4959226633Sdim 4960234353Sdim if (Parser.getTok().isNot(AsmToken::Hash) && 4961234353Sdim Parser.getTok().isNot(AsmToken::Dollar)) 4962226633Sdim return MatchOperand_NoMatch; 4963234353Sdim 4964234353Sdim // Disambiguate the VMOV forms that can accept an FP immediate. 4965234353Sdim // vmov.f32 <sreg>, #imm 4966234353Sdim // vmov.f64 <dreg>, #imm 4967234353Sdim // vmov.f32 <dreg>, #imm @ vector f32x2 4968234353Sdim // vmov.f32 <qreg>, #imm @ vector f32x4 4969234353Sdim // 4970234353Sdim // There are also the NEON VMOV instructions which expect an 4971234353Sdim // integer constant. Make sure we don't try to parse an FPImm 4972234353Sdim // for these: 4973234353Sdim // vmov.i{8|16|32|64} <dreg|qreg>, #imm 4974276479Sdim ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]); 4975276479Sdim bool isVmovf = TyOp.isToken() && 4976276479Sdim (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64"); 4977276479Sdim ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]); 4978276479Sdim bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" || 4979276479Sdim Mnemonic.getToken() == "fconsts"); 4980276479Sdim if (!(isVmovf || isFconst)) 4981234353Sdim return MatchOperand_NoMatch; 4982234353Sdim 4983261991Sdim Parser.Lex(); // Eat '#' or '$'. 4984226633Sdim 4985226633Sdim // Handle negation, as that still comes through as a separate token. 4986226633Sdim bool isNegative = false; 4987226633Sdim if (Parser.getTok().is(AsmToken::Minus)) { 4988226633Sdim isNegative = true; 4989226633Sdim Parser.Lex(); 4990226633Sdim } 4991226633Sdim const AsmToken &Tok = Parser.getTok(); 4992234353Sdim SMLoc Loc = Tok.getLoc(); 4993276479Sdim if (Tok.is(AsmToken::Real) && isVmovf) { 4994234353Sdim APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 4995226633Sdim uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 4996226633Sdim // If we had a '-' in front, toggle the sign bit. 4997234353Sdim IntVal ^= (uint64_t)isNegative << 31; 4998226633Sdim Parser.Lex(); // Eat the token. 4999234353Sdim Operands.push_back(ARMOperand::CreateImm( 5000288943Sdim MCConstantExpr::create(IntVal, getContext()), 5001234353Sdim S, Parser.getTok().getLoc())); 5002226633Sdim return MatchOperand_Success; 5003226633Sdim } 5004234353Sdim // Also handle plain integers. Instructions which allow floating point 5005234353Sdim // immediates also allow a raw encoded 8-bit value. 5006276479Sdim if (Tok.is(AsmToken::Integer) && isFconst) { 5007226633Sdim int64_t Val = Tok.getIntVal(); 5008226633Sdim Parser.Lex(); // Eat the token. 5009226633Sdim if (Val > 255 || Val < 0) { 5010234353Sdim Error(Loc, "encoded floating point value out of range"); 5011226633Sdim return MatchOperand_ParseFail; 5012226633Sdim } 5013276479Sdim float RealVal = ARM_AM::getFPImmFloat(Val); 5014276479Sdim Val = APFloat(RealVal).bitcastToAPInt().getZExtValue(); 5015276479Sdim 5016234353Sdim Operands.push_back(ARMOperand::CreateImm( 5017288943Sdim MCConstantExpr::create(Val, getContext()), S, 5018234353Sdim Parser.getTok().getLoc())); 5019226633Sdim return MatchOperand_Success; 5020226633Sdim } 5021226633Sdim 5022234353Sdim Error(Loc, "invalid floating point immediate"); 5023226633Sdim return MatchOperand_ParseFail; 5024226633Sdim} 5025234353Sdim 5026198892Srdivacky/// Parse a arm instruction operand. For now this parses the operand regardless 5027198892Srdivacky/// of the mnemonic. 5028276479Sdimbool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { 5029280031Sdim MCAsmParser &Parser = getParser(); 5030206124Srdivacky SMLoc S, E; 5031218893Sdim 5032218893Sdim // Check if the current operand has a custom associated parser, if so, try to 5033218893Sdim // custom parse the operand, or fallback to the general approach. 5034218893Sdim OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 5035218893Sdim if (ResTy == MatchOperand_Success) 5036218893Sdim return false; 5037218893Sdim // If there wasn't a custom match, try the generic matcher below. Otherwise, 5038218893Sdim // there was a match, but an error occurred, in which case, just return that 5039218893Sdim // the operand parsing failed. 5040218893Sdim if (ResTy == MatchOperand_ParseFail) 5041218893Sdim return true; 5042218893Sdim 5043198090Srdivacky switch (getLexer().getKind()) { 5044218893Sdim default: 5045218893Sdim Error(Parser.getTok().getLoc(), "unexpected token in operand"); 5046218893Sdim return true; 5047224145Sdim case AsmToken::Identifier: { 5048249423Sdim // If we've seen a branch mnemonic, the next operand must be a label. This 5049249423Sdim // is true even if the label is a register name. So "br r1" means branch to 5050249423Sdim // label "r1". 5051249423Sdim bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl"; 5052249423Sdim if (!ExpectLabel) { 5053249423Sdim if (!tryParseRegisterWithWriteBack(Operands)) 5054249423Sdim return false; 5055249423Sdim int Res = tryParseShiftRegister(Operands); 5056249423Sdim if (Res == 0) // success 5057249423Sdim return false; 5058249423Sdim else if (Res == -1) // irrecoverable error 5059249423Sdim return true; 5060249423Sdim // If this is VMRS, check for the apsr_nzcv operand. 5061249423Sdim if (Mnemonic == "vmrs" && 5062249423Sdim Parser.getTok().getString().equals_lower("apsr_nzcv")) { 5063249423Sdim S = Parser.getTok().getLoc(); 5064249423Sdim Parser.Lex(); 5065249423Sdim Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 5066249423Sdim return false; 5067249423Sdim } 5068226633Sdim } 5069218893Sdim 5070218893Sdim // Fall though for the Identifier case that is not a register or a 5071218893Sdim // special name. 5072224145Sdim } 5073234353Sdim case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 5074218893Sdim case AsmToken::Integer: // things like 1f and 2b as a branch targets 5075234353Sdim case AsmToken::String: // quoted label names. 5076218893Sdim case AsmToken::Dot: { // . as a branch target 5077198396Srdivacky // This was not a register so parse other operands that start with an 5078198396Srdivacky // identifier (like labels) as expressions and create them as immediates. 5079198396Srdivacky const MCExpr *IdVal; 5080206124Srdivacky S = Parser.getTok().getLoc(); 5081249423Sdim if (getParser().parseExpression(IdVal)) 5082198396Srdivacky return true; 5083206124Srdivacky E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5084218893Sdim Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 5085198396Srdivacky return false; 5086218893Sdim } 5087198090Srdivacky case AsmToken::LBrac: 5088226633Sdim return parseMemory(Operands); 5089198090Srdivacky case AsmToken::LCurly: 5090226633Sdim return parseRegisterList(Operands); 5091234353Sdim case AsmToken::Dollar: 5092226633Sdim case AsmToken::Hash: { 5093198090Srdivacky // #42 -> immediate. 5094206124Srdivacky S = Parser.getTok().getLoc(); 5095202878Srdivacky Parser.Lex(); 5096234982Sdim 5097234982Sdim if (Parser.getTok().isNot(AsmToken::Colon)) { 5098234982Sdim bool isNegative = Parser.getTok().is(AsmToken::Minus); 5099234982Sdim const MCExpr *ImmVal; 5100249423Sdim if (getParser().parseExpression(ImmVal)) 5101234982Sdim return true; 5102234982Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 5103234982Sdim if (CE) { 5104234982Sdim int32_t Val = CE->getValue(); 5105234982Sdim if (isNegative && Val == 0) 5106288943Sdim ImmVal = MCConstantExpr::create(INT32_MIN, getContext()); 5107234982Sdim } 5108234982Sdim E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5109234982Sdim Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 5110249423Sdim 5111249423Sdim // There can be a trailing '!' on operands that we want as a separate 5112276479Sdim // '!' Token operand. Handle that here. For example, the compatibility 5113249423Sdim // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'. 5114249423Sdim if (Parser.getTok().is(AsmToken::Exclaim)) { 5115249423Sdim Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), 5116249423Sdim Parser.getTok().getLoc())); 5117249423Sdim Parser.Lex(); // Eat exclaim token 5118249423Sdim } 5119234982Sdim return false; 5120226633Sdim } 5121234982Sdim // w/ a ':' after the '#', it's just like a plain ':'. 5122234982Sdim // FALLTHROUGH 5123226633Sdim } 5124218893Sdim case AsmToken::Colon: { 5125296417Sdim S = Parser.getTok().getLoc(); 5126218893Sdim // ":lower16:" and ":upper16:" expression prefixes 5127218893Sdim // FIXME: Check it's an expression prefix, 5128218893Sdim // e.g. (FOO - :lower16:BAR) isn't legal. 5129218893Sdim ARMMCExpr::VariantKind RefKind; 5130226633Sdim if (parsePrefix(RefKind)) 5131218893Sdim return true; 5132218893Sdim 5133218893Sdim const MCExpr *SubExprVal; 5134249423Sdim if (getParser().parseExpression(SubExprVal)) 5135218893Sdim return true; 5136218893Sdim 5137288943Sdim const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal, 5138243830Sdim getContext()); 5139218893Sdim E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5140218893Sdim Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 5141218893Sdim return false; 5142198090Srdivacky } 5143276479Sdim case AsmToken::Equal: { 5144296417Sdim S = Parser.getTok().getLoc(); 5145276479Sdim if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val) 5146296417Sdim return Error(S, "unexpected token in operand"); 5147276479Sdim 5148276479Sdim Parser.Lex(); // Eat '=' 5149276479Sdim const MCExpr *SubExprVal; 5150276479Sdim if (getParser().parseExpression(SubExprVal)) 5151276479Sdim return true; 5152276479Sdim E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5153276479Sdim 5154296417Sdim const MCExpr *CPLoc = 5155296417Sdim getTargetStreamer().addConstantPoolEntry(SubExprVal, S); 5156276479Sdim Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E)); 5157276479Sdim return false; 5158218893Sdim } 5159276479Sdim } 5160198090Srdivacky} 5161198090Srdivacky 5162226633Sdim// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 5163218893Sdim// :lower16: and :upper16:. 5164226633Sdimbool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 5165280031Sdim MCAsmParser &Parser = getParser(); 5166218893Sdim RefKind = ARMMCExpr::VK_ARM_None; 5167212904Sdim 5168276479Sdim // consume an optional '#' (GNU compatibility) 5169276479Sdim if (getLexer().is(AsmToken::Hash)) 5170276479Sdim Parser.Lex(); 5171276479Sdim 5172218893Sdim // :lower16: and :upper16: modifiers 5173218893Sdim assert(getLexer().is(AsmToken::Colon) && "expected a :"); 5174218893Sdim Parser.Lex(); // Eat ':' 5175212904Sdim 5176218893Sdim if (getLexer().isNot(AsmToken::Identifier)) { 5177218893Sdim Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 5178218893Sdim return true; 5179218893Sdim } 5180218893Sdim 5181280031Sdim enum { 5182280031Sdim COFF = (1 << MCObjectFileInfo::IsCOFF), 5183280031Sdim ELF = (1 << MCObjectFileInfo::IsELF), 5184280031Sdim MACHO = (1 << MCObjectFileInfo::IsMachO) 5185280031Sdim }; 5186280031Sdim static const struct PrefixEntry { 5187280031Sdim const char *Spelling; 5188280031Sdim ARMMCExpr::VariantKind VariantKind; 5189280031Sdim uint8_t SupportedFormats; 5190280031Sdim } PrefixEntries[] = { 5191280031Sdim { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO }, 5192280031Sdim { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO }, 5193280031Sdim }; 5194280031Sdim 5195218893Sdim StringRef IDVal = Parser.getTok().getIdentifier(); 5196280031Sdim 5197280031Sdim const auto &Prefix = 5198280031Sdim std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries), 5199280031Sdim [&IDVal](const PrefixEntry &PE) { 5200280031Sdim return PE.Spelling == IDVal; 5201280031Sdim }); 5202280031Sdim if (Prefix == std::end(PrefixEntries)) { 5203218893Sdim Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 5204218893Sdim return true; 5205218893Sdim } 5206280031Sdim 5207280031Sdim uint8_t CurrentFormat; 5208280031Sdim switch (getContext().getObjectFileInfo()->getObjectFileType()) { 5209280031Sdim case MCObjectFileInfo::IsMachO: 5210280031Sdim CurrentFormat = MACHO; 5211280031Sdim break; 5212280031Sdim case MCObjectFileInfo::IsELF: 5213280031Sdim CurrentFormat = ELF; 5214280031Sdim break; 5215280031Sdim case MCObjectFileInfo::IsCOFF: 5216280031Sdim CurrentFormat = COFF; 5217280031Sdim break; 5218280031Sdim } 5219280031Sdim 5220280031Sdim if (~Prefix->SupportedFormats & CurrentFormat) { 5221280031Sdim Error(Parser.getTok().getLoc(), 5222280031Sdim "cannot represent relocation in the current file format"); 5223280031Sdim return true; 5224280031Sdim } 5225280031Sdim 5226280031Sdim RefKind = Prefix->VariantKind; 5227218893Sdim Parser.Lex(); 5228218893Sdim 5229218893Sdim if (getLexer().isNot(AsmToken::Colon)) { 5230218893Sdim Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 5231218893Sdim return true; 5232218893Sdim } 5233218893Sdim Parser.Lex(); // Eat the last ':' 5234280031Sdim 5235218893Sdim return false; 5236218893Sdim} 5237218893Sdim 5238218893Sdim/// \brief Given a mnemonic, split out possible predication code and carry 5239218893Sdim/// setting letters to form a canonical mnemonic and flags. 5240218893Sdim// 5241218893Sdim// FIXME: Would be nice to autogen this. 5242226633Sdim// FIXME: This is a bit of a maze of special cases. 5243226633SdimStringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 5244226633Sdim unsigned &PredicationCode, 5245226633Sdim bool &CarrySetting, 5246226633Sdim unsigned &ProcessorIMod, 5247226633Sdim StringRef &ITMask) { 5248218893Sdim PredicationCode = ARMCC::AL; 5249218893Sdim CarrySetting = false; 5250218893Sdim ProcessorIMod = 0; 5251218893Sdim 5252218893Sdim // Ignore some mnemonics we know aren't predicated forms. 5253212904Sdim // 5254218893Sdim // FIXME: Would be nice to autogen this. 5255226633Sdim if ((Mnemonic == "movs" && isThumb()) || 5256226633Sdim Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 5257226633Sdim Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 5258226633Sdim Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 5259226633Sdim Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 5260261991Sdim Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" || 5261226633Sdim Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 5262226633Sdim Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 5263234353Sdim Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 5264261991Sdim Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || 5265261991Sdim Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || 5266261991Sdim Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" || 5267280031Sdim Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" || 5268280031Sdim Mnemonic.startswith("vsel")) 5269218893Sdim return Mnemonic; 5270218893Sdim 5271224145Sdim // First, split out any predication code. Ignore mnemonics we know aren't 5272224145Sdim // predicated but do have a carry-set and so weren't caught above. 5273226633Sdim if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 5274226633Sdim Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 5275226633Sdim Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 5276226633Sdim Mnemonic != "sbcs" && Mnemonic != "rscs") { 5277224145Sdim unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 5278224145Sdim .Case("eq", ARMCC::EQ) 5279224145Sdim .Case("ne", ARMCC::NE) 5280224145Sdim .Case("hs", ARMCC::HS) 5281224145Sdim .Case("cs", ARMCC::HS) 5282224145Sdim .Case("lo", ARMCC::LO) 5283224145Sdim .Case("cc", ARMCC::LO) 5284224145Sdim .Case("mi", ARMCC::MI) 5285224145Sdim .Case("pl", ARMCC::PL) 5286224145Sdim .Case("vs", ARMCC::VS) 5287224145Sdim .Case("vc", ARMCC::VC) 5288224145Sdim .Case("hi", ARMCC::HI) 5289224145Sdim .Case("ls", ARMCC::LS) 5290224145Sdim .Case("ge", ARMCC::GE) 5291224145Sdim .Case("lt", ARMCC::LT) 5292224145Sdim .Case("gt", ARMCC::GT) 5293224145Sdim .Case("le", ARMCC::LE) 5294224145Sdim .Case("al", ARMCC::AL) 5295224145Sdim .Default(~0U); 5296224145Sdim if (CC != ~0U) { 5297224145Sdim Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 5298224145Sdim PredicationCode = CC; 5299224145Sdim } 5300218893Sdim } 5301212904Sdim 5302218893Sdim // Next, determine if we have a carry setting bit. We explicitly ignore all 5303218893Sdim // the instructions we know end in 's'. 5304218893Sdim if (Mnemonic.endswith("s") && 5305226633Sdim !(Mnemonic == "cps" || Mnemonic == "mls" || 5306226633Sdim Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 5307226633Sdim Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 5308226633Sdim Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 5309234353Sdim Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 5310234353Sdim Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 5311234353Sdim Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 5312234353Sdim Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 5313276479Sdim Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" || 5314226633Sdim (Mnemonic == "movs" && isThumb()))) { 5315218893Sdim Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 5316218893Sdim CarrySetting = true; 5317218893Sdim } 5318198090Srdivacky 5319218893Sdim // The "cps" instruction can have a interrupt mode operand which is glued into 5320218893Sdim // the mnemonic. Check if this is the case, split it and parse the imod op 5321218893Sdim if (Mnemonic.startswith("cps")) { 5322218893Sdim // Split out any imod code. 5323218893Sdim unsigned IMod = 5324218893Sdim StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 5325218893Sdim .Case("ie", ARM_PROC::IE) 5326218893Sdim .Case("id", ARM_PROC::ID) 5327218893Sdim .Default(~0U); 5328218893Sdim if (IMod != ~0U) { 5329218893Sdim Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 5330218893Sdim ProcessorIMod = IMod; 5331218893Sdim } 5332218893Sdim } 5333212904Sdim 5334226633Sdim // The "it" instruction has the condition mask on the end of the mnemonic. 5335226633Sdim if (Mnemonic.startswith("it")) { 5336226633Sdim ITMask = Mnemonic.slice(2, Mnemonic.size()); 5337226633Sdim Mnemonic = Mnemonic.slice(0, 2); 5338226633Sdim } 5339226633Sdim 5340218893Sdim return Mnemonic; 5341218893Sdim} 5342218893Sdim 5343218893Sdim/// \brief Given a canonical mnemonic, determine if the instruction ever allows 5344218893Sdim/// inclusion of carry set or predication code operands. 5345218893Sdim// 5346218893Sdim// FIXME: It would be nice to autogen this. 5347288943Sdimvoid ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, 5348288943Sdim bool &CanAcceptCarrySet, 5349288943Sdim bool &CanAcceptPredicationCode) { 5350288943Sdim CanAcceptCarrySet = 5351288943Sdim Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 5352218893Sdim Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 5353288943Sdim Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" || 5354288943Sdim Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" || 5355288943Sdim Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" || 5356288943Sdim Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" || 5357288943Sdim Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" || 5358288943Sdim (!isThumb() && 5359288943Sdim (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" || 5360288943Sdim Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull")); 5361218893Sdim 5362261991Sdim if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" || 5363288943Sdim Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" || 5364276479Sdim Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" || 5365276479Sdim Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") || 5366288943Sdim Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" || 5367288943Sdim Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" || 5368288943Sdim Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" || 5369288943Sdim Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" || 5370288943Sdim Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" || 5371261991Sdim Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") || 5372261991Sdim (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) { 5373261991Sdim // These mnemonics are never predicable 5374218893Sdim CanAcceptPredicationCode = false; 5375261991Sdim } else if (!isThumb()) { 5376261991Sdim // Some instructions are only predicable in Thumb mode 5377288943Sdim CanAcceptPredicationCode = 5378288943Sdim Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" && 5379261991Sdim Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" && 5380261991Sdim Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" && 5381261991Sdim Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" && 5382288943Sdim Mnemonic != "ldc2" && Mnemonic != "ldc2l" && Mnemonic != "stc2" && 5383288943Sdim Mnemonic != "stc2l" && !Mnemonic.startswith("rfe") && 5384288943Sdim !Mnemonic.startswith("srs"); 5385261991Sdim } else if (isThumbOne()) { 5386261991Sdim if (hasV6MOps()) 5387261991Sdim CanAcceptPredicationCode = Mnemonic != "movs"; 5388261991Sdim else 5389261991Sdim CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs"; 5390226633Sdim } else 5391218893Sdim CanAcceptPredicationCode = true; 5392218893Sdim} 5393218893Sdim 5394288943Sdim// \brief Some Thumb instructions have two operand forms that are not 5395288943Sdim// available as three operand, convert to two operand form if possible. 5396288943Sdim// 5397288943Sdim// FIXME: We would really like to be able to tablegen'erate this. 5398288943Sdimvoid ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic, 5399288943Sdim bool CarrySetting, 5400288943Sdim OperandVector &Operands) { 5401288943Sdim if (Operands.size() != 6) 5402288943Sdim return; 5403288943Sdim 5404288943Sdim const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); 5405288943Sdim auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); 5406288943Sdim if (!Op3.isReg() || !Op4.isReg()) 5407288943Sdim return; 5408288943Sdim 5409288943Sdim auto Op3Reg = Op3.getReg(); 5410288943Sdim auto Op4Reg = Op4.getReg(); 5411288943Sdim 5412288943Sdim // For most Thumb2 cases we just generate the 3 operand form and reduce 5413288943Sdim // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr) 5414288943Sdim // won't accept SP or PC so we do the transformation here taking care 5415288943Sdim // with immediate range in the 'add sp, sp #imm' case. 5416288943Sdim auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); 5417288943Sdim if (isThumbTwo()) { 5418288943Sdim if (Mnemonic != "add") 5419288943Sdim return; 5420288943Sdim bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC || 5421288943Sdim (Op5.isReg() && Op5.getReg() == ARM::PC); 5422288943Sdim if (!TryTransform) { 5423288943Sdim TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP || 5424288943Sdim (Op5.isReg() && Op5.getReg() == ARM::SP)) && 5425288943Sdim !(Op3Reg == ARM::SP && Op4Reg == ARM::SP && 5426288943Sdim Op5.isImm() && !Op5.isImm0_508s4()); 5427288943Sdim } 5428288943Sdim if (!TryTransform) 5429288943Sdim return; 5430288943Sdim } else if (!isThumbOne()) 5431288943Sdim return; 5432288943Sdim 5433288943Sdim if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" || 5434288943Sdim Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" || 5435288943Sdim Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" || 5436288943Sdim Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic")) 5437288943Sdim return; 5438288943Sdim 5439288943Sdim // If first 2 operands of a 3 operand instruction are the same 5440288943Sdim // then transform to 2 operand version of the same instruction 5441288943Sdim // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1' 5442288943Sdim bool Transform = Op3Reg == Op4Reg; 5443288943Sdim 5444288943Sdim // For communtative operations, we might be able to transform if we swap 5445288943Sdim // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially 5446288943Sdim // as tADDrsp. 5447288943Sdim const ARMOperand *LastOp = &Op5; 5448288943Sdim bool Swap = false; 5449288943Sdim if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() && 5450288943Sdim ((Mnemonic == "add" && Op4Reg != ARM::SP) || 5451288943Sdim Mnemonic == "and" || Mnemonic == "eor" || 5452288943Sdim Mnemonic == "adc" || Mnemonic == "orr")) { 5453288943Sdim Swap = true; 5454288943Sdim LastOp = &Op4; 5455288943Sdim Transform = true; 5456288943Sdim } 5457288943Sdim 5458288943Sdim // If both registers are the same then remove one of them from 5459288943Sdim // the operand list, with certain exceptions. 5460288943Sdim if (Transform) { 5461288943Sdim // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the 5462288943Sdim // 2 operand forms don't exist. 5463288943Sdim if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") && 5464288943Sdim LastOp->isReg()) 5465288943Sdim Transform = false; 5466288943Sdim 5467288943Sdim // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into 5468288943Sdim // 3-bits because the ARMARM says not to. 5469288943Sdim if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7()) 5470288943Sdim Transform = false; 5471288943Sdim } 5472288943Sdim 5473288943Sdim if (Transform) { 5474288943Sdim if (Swap) 5475288943Sdim std::swap(Op4, Op5); 5476288943Sdim Operands.erase(Operands.begin() + 3); 5477288943Sdim } 5478288943Sdim} 5479288943Sdim 5480226633Sdimbool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 5481276479Sdim OperandVector &Operands) { 5482226633Sdim // FIXME: This is all horribly hacky. We really need a better way to deal 5483226633Sdim // with optional operands like this in the matcher table. 5484226633Sdim 5485226633Sdim // The 'mov' mnemonic is special. One variant has a cc_out operand, while 5486226633Sdim // another does not. Specifically, the MOVW instruction does not. So we 5487226633Sdim // special case it here and remove the defaulted (non-setting) cc_out 5488226633Sdim // operand if that's the instruction we're trying to match. 5489226633Sdim // 5490226633Sdim // We do this as post-processing of the explicit operands rather than just 5491226633Sdim // conditionally adding the cc_out in the first place because we need 5492226633Sdim // to check the type of the parsed immediate operand. 5493226633Sdim if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 5494280031Sdim !static_cast<ARMOperand &>(*Operands[4]).isModImm() && 5495276479Sdim static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() && 5496276479Sdim static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) 5497226633Sdim return true; 5498226633Sdim 5499226633Sdim // Register-register 'add' for thumb does not have a cc_out operand 5500226633Sdim // when there are only two register operands. 5501226633Sdim if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 5502276479Sdim static_cast<ARMOperand &>(*Operands[3]).isReg() && 5503276479Sdim static_cast<ARMOperand &>(*Operands[4]).isReg() && 5504276479Sdim static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) 5505226633Sdim return true; 5506226633Sdim // Register-register 'add' for thumb does not have a cc_out operand 5507226633Sdim // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 5508226633Sdim // have to check the immediate range here since Thumb2 has a variant 5509226633Sdim // that can handle a different range and has a cc_out operand. 5510226633Sdim if (((isThumb() && Mnemonic == "add") || 5511226633Sdim (isThumbTwo() && Mnemonic == "sub")) && 5512276479Sdim Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && 5513276479Sdim static_cast<ARMOperand &>(*Operands[4]).isReg() && 5514276479Sdim static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && 5515276479Sdim static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 5516276479Sdim ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) || 5517276479Sdim static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4())) 5518226633Sdim return true; 5519226633Sdim // For Thumb2, add/sub immediate does not have a cc_out operand for the 5520226633Sdim // imm0_4095 variant. That's the least-preferred variant when 5521226633Sdim // selecting via the generic "add" mnemonic, so to know that we 5522226633Sdim // should remove the cc_out operand, we have to explicitly check that 5523226633Sdim // it's not one of the other variants. Ugh. 5524226633Sdim if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 5525276479Sdim Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && 5526276479Sdim static_cast<ARMOperand &>(*Operands[4]).isReg() && 5527276479Sdim static_cast<ARMOperand &>(*Operands[5]).isImm()) { 5528226633Sdim // Nest conditions rather than one big 'if' statement for readability. 5529226633Sdim // 5530226633Sdim // If both registers are low, we're in an IT block, and the immediate is 5531226633Sdim // in range, we should use encoding T1 instead, which has a cc_out. 5532226633Sdim if (inITBlock() && 5533276479Sdim isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && 5534276479Sdim isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && 5535276479Sdim static_cast<ARMOperand &>(*Operands[5]).isImm0_7()) 5536226633Sdim return false; 5537261991Sdim // Check against T3. If the second register is the PC, this is an 5538261991Sdim // alternate form of ADR, which uses encoding T4, so check for that too. 5539276479Sdim if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && 5540276479Sdim static_cast<ARMOperand &>(*Operands[5]).isT2SOImm()) 5541261991Sdim return false; 5542226633Sdim 5543226633Sdim // Otherwise, we use encoding T4, which does not have a cc_out 5544226633Sdim // operand. 5545226633Sdim return true; 5546226633Sdim } 5547226633Sdim 5548226633Sdim // The thumb2 multiply instruction doesn't have a CCOut register, so 5549226633Sdim // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 5550226633Sdim // use the 16-bit encoding or not. 5551226633Sdim if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 5552276479Sdim static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 5553276479Sdim static_cast<ARMOperand &>(*Operands[3]).isReg() && 5554276479Sdim static_cast<ARMOperand &>(*Operands[4]).isReg() && 5555276479Sdim static_cast<ARMOperand &>(*Operands[5]).isReg() && 5556226633Sdim // If the registers aren't low regs, the destination reg isn't the 5557226633Sdim // same as one of the source regs, or the cc_out operand is zero 5558226633Sdim // outside of an IT block, we have to use the 32-bit encoding, so 5559226633Sdim // remove the cc_out operand. 5560276479Sdim (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 5561276479Sdim !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 5562276479Sdim !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || 5563276479Sdim !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() != 5564276479Sdim static_cast<ARMOperand &>(*Operands[5]).getReg() && 5565276479Sdim static_cast<ARMOperand &>(*Operands[3]).getReg() != 5566276479Sdim static_cast<ARMOperand &>(*Operands[4]).getReg()))) 5567226633Sdim return true; 5568226633Sdim 5569234353Sdim // Also check the 'mul' syntax variant that doesn't specify an explicit 5570234353Sdim // destination register. 5571234353Sdim if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 5572276479Sdim static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 5573276479Sdim static_cast<ARMOperand &>(*Operands[3]).isReg() && 5574276479Sdim static_cast<ARMOperand &>(*Operands[4]).isReg() && 5575234353Sdim // If the registers aren't low regs or the cc_out operand is zero 5576234353Sdim // outside of an IT block, we have to use the 32-bit encoding, so 5577234353Sdim // remove the cc_out operand. 5578276479Sdim (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 5579276479Sdim !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 5580234353Sdim !inITBlock())) 5581234353Sdim return true; 5582226633Sdim 5583226633Sdim 5584234353Sdim 5585226633Sdim // Register-register 'add/sub' for thumb does not have a cc_out operand 5586226633Sdim // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 5587226633Sdim // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 5588226633Sdim // right, this will result in better diagnostics (which operand is off) 5589226633Sdim // anyway. 5590226633Sdim if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 5591226633Sdim (Operands.size() == 5 || Operands.size() == 6) && 5592276479Sdim static_cast<ARMOperand &>(*Operands[3]).isReg() && 5593276479Sdim static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && 5594276479Sdim static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 5595276479Sdim (static_cast<ARMOperand &>(*Operands[4]).isImm() || 5596234353Sdim (Operands.size() == 6 && 5597276479Sdim static_cast<ARMOperand &>(*Operands[5]).isImm()))) 5598226633Sdim return true; 5599226633Sdim 5600226633Sdim return false; 5601226633Sdim} 5602226633Sdim 5603276479Sdimbool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic, 5604276479Sdim OperandVector &Operands) { 5605261991Sdim // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON 5606261991Sdim unsigned RegIdx = 3; 5607261991Sdim if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") && 5608296417Sdim (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" || 5609296417Sdim static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) { 5610276479Sdim if (static_cast<ARMOperand &>(*Operands[3]).isToken() && 5611296417Sdim (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" || 5612296417Sdim static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16")) 5613261991Sdim RegIdx = 4; 5614261991Sdim 5615276479Sdim if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && 5616276479Sdim (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( 5617276479Sdim static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || 5618276479Sdim ARMMCRegisterClasses[ARM::QPRRegClassID].contains( 5619276479Sdim static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) 5620261991Sdim return true; 5621261991Sdim } 5622261991Sdim return false; 5623261991Sdim} 5624261991Sdim 5625234353Sdimstatic bool isDataTypeToken(StringRef Tok) { 5626234353Sdim return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 5627234353Sdim Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 5628234353Sdim Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 5629234353Sdim Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 5630234353Sdim Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 5631234353Sdim Tok == ".f" || Tok == ".d"; 5632234353Sdim} 5633234353Sdim 5634234353Sdim// FIXME: This bit should probably be handled via an explicit match class 5635234353Sdim// in the .td files that matches the suffix instead of having it be 5636234353Sdim// a literal string token the way it is now. 5637234353Sdimstatic bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 5638234353Sdim return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 5639234353Sdim} 5640280031Sdimstatic void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, 5641251662Sdim unsigned VariantID); 5642276479Sdim 5643276479Sdimstatic bool RequiresVFPRegListValidation(StringRef Inst, 5644276479Sdim bool &AcceptSinglePrecisionOnly, 5645276479Sdim bool &AcceptDoublePrecisionOnly) { 5646276479Sdim if (Inst.size() < 7) 5647276479Sdim return false; 5648276479Sdim 5649276479Sdim if (Inst.startswith("fldm") || Inst.startswith("fstm")) { 5650276479Sdim StringRef AddressingMode = Inst.substr(4, 2); 5651276479Sdim if (AddressingMode == "ia" || AddressingMode == "db" || 5652276479Sdim AddressingMode == "ea" || AddressingMode == "fd") { 5653276479Sdim AcceptSinglePrecisionOnly = Inst[6] == 's'; 5654276479Sdim AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x'; 5655276479Sdim return true; 5656276479Sdim } 5657276479Sdim } 5658276479Sdim 5659276479Sdim return false; 5660276479Sdim} 5661276479Sdim 5662218893Sdim/// Parse an arm instruction mnemonic followed by its operands. 5663243830Sdimbool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 5664276479Sdim SMLoc NameLoc, OperandVector &Operands) { 5665280031Sdim MCAsmParser &Parser = getParser(); 5666276479Sdim // FIXME: Can this be done via tablegen in some fashion? 5667276479Sdim bool RequireVFPRegisterListCheck; 5668276479Sdim bool AcceptSinglePrecisionOnly; 5669276479Sdim bool AcceptDoublePrecisionOnly; 5670276479Sdim RequireVFPRegisterListCheck = 5671276479Sdim RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly, 5672276479Sdim AcceptDoublePrecisionOnly); 5673276479Sdim 5674234353Sdim // Apply mnemonic aliases before doing anything else, as the destination 5675276479Sdim // mnemonic may include suffices and we want to handle them normally. 5676234353Sdim // The generic tblgen'erated code does this later, at the start of 5677234353Sdim // MatchInstructionImpl(), but that's too late for aliases that include 5678234353Sdim // any sort of suffix. 5679280031Sdim uint64_t AvailableFeatures = getAvailableFeatures(); 5680251662Sdim unsigned AssemblerDialect = getParser().getAssemblerDialect(); 5681251662Sdim applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect); 5682234353Sdim 5683234353Sdim // First check for the ARM-specific .req directive. 5684234353Sdim if (Parser.getTok().is(AsmToken::Identifier) && 5685234353Sdim Parser.getTok().getIdentifier() == ".req") { 5686234353Sdim parseDirectiveReq(Name, NameLoc); 5687234353Sdim // We always return 'error' for this, as we're done with this 5688234353Sdim // statement and don't need to match the 'instruction." 5689234353Sdim return true; 5690234353Sdim } 5691234353Sdim 5692218893Sdim // Create the leading tokens for the mnemonic, split by '.' characters. 5693218893Sdim size_t Start = 0, Next = Name.find('.'); 5694226633Sdim StringRef Mnemonic = Name.slice(Start, Next); 5695218893Sdim 5696218893Sdim // Split out the predication code and carry setting flag from the mnemonic. 5697218893Sdim unsigned PredicationCode; 5698218893Sdim unsigned ProcessorIMod; 5699218893Sdim bool CarrySetting; 5700226633Sdim StringRef ITMask; 5701226633Sdim Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 5702226633Sdim ProcessorIMod, ITMask); 5703218893Sdim 5704226633Sdim // In Thumb1, only the branch (B) instruction can be predicated. 5705226633Sdim if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 5706249423Sdim Parser.eatToEndOfStatement(); 5707226633Sdim return Error(NameLoc, "conditional execution not supported in Thumb1"); 5708226633Sdim } 5709218893Sdim 5710226633Sdim Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 5711226633Sdim 5712226633Sdim // Handle the IT instruction ITMask. Convert it to a bitmask. This 5713226633Sdim // is the mask as it will be for the IT encoding if the conditional 5714226633Sdim // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 5715226633Sdim // where the conditional bit0 is zero, the instruction post-processing 5716226633Sdim // will adjust the mask accordingly. 5717226633Sdim if (Mnemonic == "it") { 5718226633Sdim SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 5719226633Sdim if (ITMask.size() > 3) { 5720249423Sdim Parser.eatToEndOfStatement(); 5721226633Sdim return Error(Loc, "too many conditions on IT instruction"); 5722226633Sdim } 5723226633Sdim unsigned Mask = 8; 5724226633Sdim for (unsigned i = ITMask.size(); i != 0; --i) { 5725226633Sdim char pos = ITMask[i - 1]; 5726226633Sdim if (pos != 't' && pos != 'e') { 5727249423Sdim Parser.eatToEndOfStatement(); 5728226633Sdim return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 5729226633Sdim } 5730226633Sdim Mask >>= 1; 5731226633Sdim if (ITMask[i - 1] == 't') 5732226633Sdim Mask |= 8; 5733226633Sdim } 5734226633Sdim Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 5735226633Sdim } 5736226633Sdim 5737226633Sdim // FIXME: This is all a pretty gross hack. We should automatically handle 5738226633Sdim // optional operands like this via tblgen. 5739226633Sdim 5740218893Sdim // Next, add the CCOut and ConditionCode operands, if needed. 5741218893Sdim // 5742218893Sdim // For mnemonics which can ever incorporate a carry setting bit or predication 5743218893Sdim // code, our matching model involves us always generating CCOut and 5744218893Sdim // ConditionCode operands to match the mnemonic "as written" and then we let 5745218893Sdim // the matcher deal with finding the right instruction or generating an 5746218893Sdim // appropriate error. 5747218893Sdim bool CanAcceptCarrySet, CanAcceptPredicationCode; 5748261991Sdim getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode); 5749218893Sdim 5750224145Sdim // If we had a carry-set on an instruction that can't do that, issue an 5751224145Sdim // error. 5752224145Sdim if (!CanAcceptCarrySet && CarrySetting) { 5753249423Sdim Parser.eatToEndOfStatement(); 5754226633Sdim return Error(NameLoc, "instruction '" + Mnemonic + 5755224145Sdim "' can not set flags, but 's' suffix specified"); 5756224145Sdim } 5757226633Sdim // If we had a predication code on an instruction that can't do that, issue an 5758226633Sdim // error. 5759226633Sdim if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 5760249423Sdim Parser.eatToEndOfStatement(); 5761226633Sdim return Error(NameLoc, "instruction '" + Mnemonic + 5762226633Sdim "' is not predicable, but condition code specified"); 5763226633Sdim } 5764224145Sdim 5765218893Sdim // Add the carry setting operand, if necessary. 5766226633Sdim if (CanAcceptCarrySet) { 5767226633Sdim SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5768218893Sdim Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5769226633Sdim Loc)); 5770226633Sdim } 5771218893Sdim 5772218893Sdim // Add the predication code operand, if necessary. 5773218893Sdim if (CanAcceptPredicationCode) { 5774226633Sdim SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5775226633Sdim CarrySetting); 5776218893Sdim Operands.push_back(ARMOperand::CreateCondCode( 5777226633Sdim ARMCC::CondCodes(PredicationCode), Loc)); 5778218893Sdim } 5779218893Sdim 5780218893Sdim // Add the processor imod operand, if necessary. 5781218893Sdim if (ProcessorIMod) { 5782218893Sdim Operands.push_back(ARMOperand::CreateImm( 5783288943Sdim MCConstantExpr::create(ProcessorIMod, getContext()), 5784218893Sdim NameLoc, NameLoc)); 5785280031Sdim } else if (Mnemonic == "cps" && isMClass()) { 5786280031Sdim return Error(NameLoc, "instruction 'cps' requires effect for M-class"); 5787218893Sdim } 5788218893Sdim 5789212904Sdim // Add the remaining tokens in the mnemonic. 5790212904Sdim while (Next != StringRef::npos) { 5791212904Sdim Start = Next; 5792212904Sdim Next = Name.find('.', Start + 1); 5793218893Sdim StringRef ExtraToken = Name.slice(Start, Next); 5794212904Sdim 5795234353Sdim // Some NEON instructions have an optional datatype suffix that is 5796234353Sdim // completely ignored. Check for that. 5797234353Sdim if (isDataTypeToken(ExtraToken) && 5798234353Sdim doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 5799234353Sdim continue; 5800234353Sdim 5801261991Sdim // For for ARM mode generate an error if the .n qualifier is used. 5802261991Sdim if (ExtraToken == ".n" && !isThumb()) { 5803226633Sdim SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5804276479Sdim Parser.eatToEndOfStatement(); 5805261991Sdim return Error(Loc, "instruction with .n (narrow) qualifier not allowed in " 5806261991Sdim "arm mode"); 5807261991Sdim } 5808261991Sdim 5809261991Sdim // The .n qualifier is always discarded as that is what the tables 5810261991Sdim // and matcher expect. In ARM mode the .w qualifier has no effect, 5811261991Sdim // so discard it to avoid errors that can be caused by the matcher. 5812261991Sdim if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) { 5813261991Sdim SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5814226633Sdim Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 5815226633Sdim } 5816212904Sdim } 5817212904Sdim 5818212904Sdim // Read the remaining operands. 5819198090Srdivacky if (getLexer().isNot(AsmToken::EndOfStatement)) { 5820198090Srdivacky // Read the first operand. 5821226633Sdim if (parseOperand(Operands, Mnemonic)) { 5822249423Sdim Parser.eatToEndOfStatement(); 5823218893Sdim return true; 5824218893Sdim } 5825198090Srdivacky 5826198090Srdivacky while (getLexer().is(AsmToken::Comma)) { 5827202878Srdivacky Parser.Lex(); // Eat the comma. 5828198090Srdivacky 5829198090Srdivacky // Parse and remember the operand. 5830226633Sdim if (parseOperand(Operands, Mnemonic)) { 5831249423Sdim Parser.eatToEndOfStatement(); 5832218893Sdim return true; 5833218893Sdim } 5834198090Srdivacky } 5835198090Srdivacky } 5836218893Sdim 5837218893Sdim if (getLexer().isNot(AsmToken::EndOfStatement)) { 5838226633Sdim SMLoc Loc = getLexer().getLoc(); 5839249423Sdim Parser.eatToEndOfStatement(); 5840226633Sdim return Error(Loc, "unexpected token in argument list"); 5841218893Sdim } 5842218893Sdim 5843218893Sdim Parser.Lex(); // Consume the EndOfStatement 5844226633Sdim 5845276479Sdim if (RequireVFPRegisterListCheck) { 5846276479Sdim ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back()); 5847276479Sdim if (AcceptSinglePrecisionOnly && !Op.isSPRRegList()) 5848276479Sdim return Error(Op.getStartLoc(), 5849276479Sdim "VFP/Neon single precision register expected"); 5850276479Sdim if (AcceptDoublePrecisionOnly && !Op.isDPRRegList()) 5851276479Sdim return Error(Op.getStartLoc(), 5852276479Sdim "VFP/Neon double precision register expected"); 5853276479Sdim } 5854276479Sdim 5855288943Sdim tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands); 5856288943Sdim 5857226633Sdim // Some instructions, mostly Thumb, have forms for the same mnemonic that 5858226633Sdim // do and don't have a cc_out optional-def operand. With some spot-checks 5859226633Sdim // of the operand list, we can figure out which variant we're trying to 5860226633Sdim // parse and adjust accordingly before actually matching. We shouldn't ever 5861288943Sdim // try to remove a cc_out operand that was explicitly set on the 5862226633Sdim // mnemonic, of course (CarrySetting == true). Reason number #317 the 5863226633Sdim // table driven matcher doesn't fit well with the ARM instruction set. 5864276479Sdim if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) 5865226633Sdim Operands.erase(Operands.begin() + 1); 5866226633Sdim 5867261991Sdim // Some instructions have the same mnemonic, but don't always 5868261991Sdim // have a predicate. Distinguish them here and delete the 5869261991Sdim // predicate if needed. 5870276479Sdim if (shouldOmitPredicateOperand(Mnemonic, Operands)) 5871261991Sdim Operands.erase(Operands.begin() + 1); 5872261991Sdim 5873226633Sdim // ARM mode 'blx' need special handling, as the register operand version 5874226633Sdim // is predicable, but the label operand version is not. So, we can't rely 5875226633Sdim // on the Mnemonic based checking to correctly figure out when to put 5876226633Sdim // a k_CondCode operand in the list. If we're trying to match the label 5877226633Sdim // version, remove the k_CondCode operand here. 5878226633Sdim if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5879276479Sdim static_cast<ARMOperand &>(*Operands[2]).isImm()) 5880226633Sdim Operands.erase(Operands.begin() + 1); 5881226633Sdim 5882249423Sdim // Adjust operands of ldrexd/strexd to MCK_GPRPair. 5883249423Sdim // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, 5884249423Sdim // a single GPRPair reg operand is used in the .td file to replace the two 5885249423Sdim // GPRs. However, when parsing from asm, the two GRPs cannot be automatically 5886249423Sdim // expressed as a GPRPair, so we have to manually merge them. 5887249423Sdim // FIXME: We would really like to be able to tablegen'erate this. 5888249423Sdim if (!isThumb() && Operands.size() > 4 && 5889261991Sdim (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" || 5890261991Sdim Mnemonic == "stlexd")) { 5891261991Sdim bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd"); 5892249423Sdim unsigned Idx = isLoad ? 2 : 3; 5893276479Sdim ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]); 5894276479Sdim ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]); 5895249423Sdim 5896249423Sdim const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID); 5897249423Sdim // Adjust only if Op1 and Op2 are GPRs. 5898276479Sdim if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) && 5899276479Sdim MRC.contains(Op2.getReg())) { 5900276479Sdim unsigned Reg1 = Op1.getReg(); 5901276479Sdim unsigned Reg2 = Op2.getReg(); 5902249423Sdim unsigned Rt = MRI->getEncodingValue(Reg1); 5903249423Sdim unsigned Rt2 = MRI->getEncodingValue(Reg2); 5904249423Sdim 5905249423Sdim // Rt2 must be Rt + 1 and Rt must be even. 5906249423Sdim if (Rt + 1 != Rt2 || (Rt & 1)) { 5907276479Sdim Error(Op2.getStartLoc(), isLoad 5908276479Sdim ? "destination operands must be sequential" 5909276479Sdim : "source operands must be sequential"); 5910249423Sdim return true; 5911249423Sdim } 5912249423Sdim unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, 5913249423Sdim &(MRI->getRegClass(ARM::GPRPairRegClassID))); 5914276479Sdim Operands[Idx] = 5915276479Sdim ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc()); 5916276479Sdim Operands.erase(Operands.begin() + Idx + 1); 5917226633Sdim } 5918226633Sdim } 5919226633Sdim 5920276479Sdim // GNU Assembler extension (compatibility) 5921276479Sdim if ((Mnemonic == "ldrd" || Mnemonic == "strd")) { 5922276479Sdim ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); 5923276479Sdim ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); 5924276479Sdim if (Op3.isMem()) { 5925276479Sdim assert(Op2.isReg() && "expected register argument"); 5926276479Sdim 5927276479Sdim unsigned SuperReg = MRI->getMatchingSuperReg( 5928276479Sdim Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID)); 5929276479Sdim 5930276479Sdim assert(SuperReg && "expected register pair"); 5931276479Sdim 5932276479Sdim unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1); 5933276479Sdim 5934276479Sdim Operands.insert( 5935276479Sdim Operands.begin() + 3, 5936276479Sdim ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc())); 5937276479Sdim } 5938276479Sdim } 5939276479Sdim 5940261991Sdim // FIXME: As said above, this is all a pretty gross hack. This instruction 5941261991Sdim // does not fit with other "subs" and tblgen. 5942261991Sdim // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction 5943261991Sdim // so the Mnemonic is the original name "subs" and delete the predicate 5944261991Sdim // operand so it will match the table entry. 5945261991Sdim if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && 5946276479Sdim static_cast<ARMOperand &>(*Operands[3]).isReg() && 5947276479Sdim static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && 5948276479Sdim static_cast<ARMOperand &>(*Operands[4]).isReg() && 5949276479Sdim static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && 5950276479Sdim static_cast<ARMOperand &>(*Operands[5]).isImm()) { 5951276479Sdim Operands.front() = ARMOperand::CreateToken(Name, NameLoc); 5952261991Sdim Operands.erase(Operands.begin() + 1); 5953261991Sdim } 5954202375Srdivacky return false; 5955198090Srdivacky} 5956198090Srdivacky 5957226633Sdim// Validate context-sensitive operand constraints. 5958226633Sdim 5959226633Sdim// return 'true' if register list contains non-low GPR registers, 5960226633Sdim// 'false' otherwise. If Reg is in the register list or is HiReg, set 5961226633Sdim// 'containsReg' to true. 5962288943Sdimstatic bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo, 5963288943Sdim unsigned Reg, unsigned HiReg, 5964288943Sdim bool &containsReg) { 5965226633Sdim containsReg = false; 5966226633Sdim for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5967226633Sdim unsigned OpReg = Inst.getOperand(i).getReg(); 5968226633Sdim if (OpReg == Reg) 5969226633Sdim containsReg = true; 5970226633Sdim // Anything other than a low register isn't legal here. 5971226633Sdim if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5972226633Sdim return true; 5973226633Sdim } 5974226633Sdim return false; 5975226633Sdim} 5976226633Sdim 5977226633Sdim// Check if the specified regisgter is in the register list of the inst, 5978226633Sdim// starting at the indicated operand number. 5979288943Sdimstatic bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) { 5980288943Sdim for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) { 5981226633Sdim unsigned OpReg = Inst.getOperand(i).getReg(); 5982226633Sdim if (OpReg == Reg) 5983226633Sdim return true; 5984226633Sdim } 5985226633Sdim return false; 5986226633Sdim} 5987226633Sdim 5988261991Sdim// Return true if instruction has the interesting property of being 5989261991Sdim// allowed in IT blocks, but not being predicable. 5990261991Sdimstatic bool instIsBreakpoint(const MCInst &Inst) { 5991261991Sdim return Inst.getOpcode() == ARM::tBKPT || 5992261991Sdim Inst.getOpcode() == ARM::BKPT || 5993261991Sdim Inst.getOpcode() == ARM::tHLT || 5994261991Sdim Inst.getOpcode() == ARM::HLT; 5995261991Sdim 5996226633Sdim} 5997226633Sdim 5998288943Sdimbool ARMAsmParser::validatetLDMRegList(const MCInst &Inst, 5999280031Sdim const OperandVector &Operands, 6000280031Sdim unsigned ListNo, bool IsARPop) { 6001280031Sdim const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); 6002280031Sdim bool HasWritebackToken = Op.isToken() && Op.getToken() == "!"; 6003280031Sdim 6004280031Sdim bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); 6005280031Sdim bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR); 6006280031Sdim bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); 6007280031Sdim 6008280031Sdim if (!IsARPop && ListContainsSP) 6009280031Sdim return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 6010280031Sdim "SP may not be in the register list"); 6011280031Sdim else if (ListContainsPC && ListContainsLR) 6012280031Sdim return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 6013280031Sdim "PC and LR may not be in the register list simultaneously"); 6014280031Sdim else if (inITBlock() && !lastInITBlock() && ListContainsPC) 6015280031Sdim return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 6016280031Sdim "instruction must be outside of IT block or the last " 6017280031Sdim "instruction in an IT block"); 6018280031Sdim return false; 6019280031Sdim} 6020280031Sdim 6021288943Sdimbool ARMAsmParser::validatetSTMRegList(const MCInst &Inst, 6022280031Sdim const OperandVector &Operands, 6023280031Sdim unsigned ListNo) { 6024280031Sdim const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); 6025280031Sdim bool HasWritebackToken = Op.isToken() && Op.getToken() == "!"; 6026280031Sdim 6027280031Sdim bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); 6028280031Sdim bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); 6029280031Sdim 6030280031Sdim if (ListContainsSP && ListContainsPC) 6031280031Sdim return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 6032280031Sdim "SP and PC may not be in the register list"); 6033280031Sdim else if (ListContainsSP) 6034280031Sdim return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 6035280031Sdim "SP may not be in the register list"); 6036280031Sdim else if (ListContainsPC) 6037280031Sdim return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 6038280031Sdim "PC may not be in the register list"); 6039280031Sdim return false; 6040280031Sdim} 6041280031Sdim 6042226633Sdim// FIXME: We would really like to be able to tablegen'erate this. 6043276479Sdimbool ARMAsmParser::validateInstruction(MCInst &Inst, 6044276479Sdim const OperandVector &Operands) { 6045261991Sdim const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); 6046226633Sdim SMLoc Loc = Operands[0]->getStartLoc(); 6047261991Sdim 6048226633Sdim // Check the IT block state first. 6049261991Sdim // NOTE: BKPT and HLT instructions have the interesting property of being 6050261991Sdim // allowed in IT blocks, but not being predicable. They just always execute. 6051261991Sdim if (inITBlock() && !instIsBreakpoint(Inst)) { 6052261991Sdim unsigned Bit = 1; 6053226633Sdim if (ITState.FirstCond) 6054226633Sdim ITState.FirstCond = false; 6055226633Sdim else 6056261991Sdim Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 6057226633Sdim // The instruction must be predicable. 6058226633Sdim if (!MCID.isPredicable()) 6059226633Sdim return Error(Loc, "instructions in IT block must be predicable"); 6060226633Sdim unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 6061261991Sdim unsigned ITCond = Bit ? ITState.Cond : 6062226633Sdim ARMCC::getOppositeCondition(ITState.Cond); 6063226633Sdim if (Cond != ITCond) { 6064226633Sdim // Find the condition code Operand to get its SMLoc information. 6065226633Sdim SMLoc CondLoc; 6066261991Sdim for (unsigned I = 1; I < Operands.size(); ++I) 6067276479Sdim if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) 6068261991Sdim CondLoc = Operands[I]->getStartLoc(); 6069226633Sdim return Error(CondLoc, "incorrect condition in IT block; got '" + 6070226633Sdim StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 6071226633Sdim "', but expected '" + 6072226633Sdim ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 6073226633Sdim } 6074226633Sdim // Check for non-'al' condition codes outside of the IT block. 6075226633Sdim } else if (isThumbTwo() && MCID.isPredicable() && 6076226633Sdim Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 6077261991Sdim ARMCC::AL && Inst.getOpcode() != ARM::tBcc && 6078261991Sdim Inst.getOpcode() != ARM::t2Bcc) 6079226633Sdim return Error(Loc, "predicated instructions must be in IT block"); 6080226633Sdim 6081261991Sdim const unsigned Opcode = Inst.getOpcode(); 6082261991Sdim switch (Opcode) { 6083226633Sdim case ARM::LDRD: 6084226633Sdim case ARM::LDRD_PRE: 6085249423Sdim case ARM::LDRD_POST: { 6086261991Sdim const unsigned RtReg = Inst.getOperand(0).getReg(); 6087261991Sdim 6088261991Sdim // Rt can't be R14. 6089261991Sdim if (RtReg == ARM::LR) 6090261991Sdim return Error(Operands[3]->getStartLoc(), 6091261991Sdim "Rt can't be R14"); 6092261991Sdim 6093261991Sdim const unsigned Rt = MRI->getEncodingValue(RtReg); 6094261991Sdim // Rt must be even-numbered. 6095261991Sdim if ((Rt & 1) == 1) 6096261991Sdim return Error(Operands[3]->getStartLoc(), 6097261991Sdim "Rt must be even-numbered"); 6098261991Sdim 6099226633Sdim // Rt2 must be Rt + 1. 6100261991Sdim const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 6101226633Sdim if (Rt2 != Rt + 1) 6102226633Sdim return Error(Operands[3]->getStartLoc(), 6103226633Sdim "destination operands must be sequential"); 6104261991Sdim 6105261991Sdim if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) { 6106261991Sdim const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); 6107261991Sdim // For addressing modes with writeback, the base register needs to be 6108261991Sdim // different from the destination registers. 6109261991Sdim if (Rn == Rt || Rn == Rt2) 6110261991Sdim return Error(Operands[3]->getStartLoc(), 6111261991Sdim "base register needs to be different from destination " 6112261991Sdim "registers"); 6113261991Sdim } 6114261991Sdim 6115226633Sdim return false; 6116226633Sdim } 6117261991Sdim case ARM::t2LDRDi8: 6118261991Sdim case ARM::t2LDRD_PRE: 6119261991Sdim case ARM::t2LDRD_POST: { 6120261991Sdim // Rt2 must be different from Rt. 6121261991Sdim unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 6122261991Sdim unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 6123261991Sdim if (Rt2 == Rt) 6124261991Sdim return Error(Operands[3]->getStartLoc(), 6125261991Sdim "destination operands can't be identical"); 6126261991Sdim return false; 6127261991Sdim } 6128288943Sdim case ARM::t2BXJ: { 6129288943Sdim const unsigned RmReg = Inst.getOperand(0).getReg(); 6130288943Sdim // Rm = SP is no longer unpredictable in v8-A 6131288943Sdim if (RmReg == ARM::SP && !hasV8Ops()) 6132288943Sdim return Error(Operands[2]->getStartLoc(), 6133288943Sdim "r13 (SP) is an unpredictable operand to BXJ"); 6134288943Sdim return false; 6135288943Sdim } 6136226633Sdim case ARM::STRD: { 6137226633Sdim // Rt2 must be Rt + 1. 6138239462Sdim unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 6139239462Sdim unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 6140226633Sdim if (Rt2 != Rt + 1) 6141226633Sdim return Error(Operands[3]->getStartLoc(), 6142226633Sdim "source operands must be sequential"); 6143226633Sdim return false; 6144226633Sdim } 6145226633Sdim case ARM::STRD_PRE: 6146249423Sdim case ARM::STRD_POST: { 6147226633Sdim // Rt2 must be Rt + 1. 6148239462Sdim unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 6149239462Sdim unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 6150226633Sdim if (Rt2 != Rt + 1) 6151226633Sdim return Error(Operands[3]->getStartLoc(), 6152226633Sdim "source operands must be sequential"); 6153226633Sdim return false; 6154226633Sdim } 6155280031Sdim case ARM::STR_PRE_IMM: 6156280031Sdim case ARM::STR_PRE_REG: 6157280031Sdim case ARM::STR_POST_IMM: 6158280031Sdim case ARM::STR_POST_REG: 6159280031Sdim case ARM::STRH_PRE: 6160280031Sdim case ARM::STRH_POST: 6161280031Sdim case ARM::STRB_PRE_IMM: 6162280031Sdim case ARM::STRB_PRE_REG: 6163280031Sdim case ARM::STRB_POST_IMM: 6164280031Sdim case ARM::STRB_POST_REG: { 6165280031Sdim // Rt must be different from Rn. 6166280031Sdim const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 6167280031Sdim const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 6168280031Sdim 6169280031Sdim if (Rt == Rn) 6170280031Sdim return Error(Operands[3]->getStartLoc(), 6171280031Sdim "source register and base register can't be identical"); 6172280031Sdim return false; 6173280031Sdim } 6174280031Sdim case ARM::LDR_PRE_IMM: 6175280031Sdim case ARM::LDR_PRE_REG: 6176280031Sdim case ARM::LDR_POST_IMM: 6177280031Sdim case ARM::LDR_POST_REG: 6178280031Sdim case ARM::LDRH_PRE: 6179280031Sdim case ARM::LDRH_POST: 6180280031Sdim case ARM::LDRSH_PRE: 6181280031Sdim case ARM::LDRSH_POST: 6182280031Sdim case ARM::LDRB_PRE_IMM: 6183280031Sdim case ARM::LDRB_PRE_REG: 6184280031Sdim case ARM::LDRB_POST_IMM: 6185280031Sdim case ARM::LDRB_POST_REG: 6186280031Sdim case ARM::LDRSB_PRE: 6187280031Sdim case ARM::LDRSB_POST: { 6188280031Sdim // Rt must be different from Rn. 6189280031Sdim const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 6190280031Sdim const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 6191280031Sdim 6192280031Sdim if (Rt == Rn) 6193280031Sdim return Error(Operands[3]->getStartLoc(), 6194280031Sdim "destination register and base register can't be identical"); 6195280031Sdim return false; 6196280031Sdim } 6197226633Sdim case ARM::SBFX: 6198226633Sdim case ARM::UBFX: { 6199261991Sdim // Width must be in range [1, 32-lsb]. 6200261991Sdim unsigned LSB = Inst.getOperand(2).getImm(); 6201261991Sdim unsigned Widthm1 = Inst.getOperand(3).getImm(); 6202261991Sdim if (Widthm1 >= 32 - LSB) 6203226633Sdim return Error(Operands[5]->getStartLoc(), 6204226633Sdim "bitfield width must be in range [1,32-lsb]"); 6205226633Sdim return false; 6206226633Sdim } 6207261991Sdim // Notionally handles ARM::tLDMIA_UPD too. 6208226633Sdim case ARM::tLDMIA: { 6209226633Sdim // If we're parsing Thumb2, the .w variant is available and handles 6210261991Sdim // most cases that are normally illegal for a Thumb1 LDM instruction. 6211261991Sdim // We'll make the transformation in processInstruction() if necessary. 6212226633Sdim // 6213226633Sdim // Thumb LDM instructions are writeback iff the base register is not 6214226633Sdim // in the register list. 6215226633Sdim unsigned Rn = Inst.getOperand(0).getReg(); 6216261991Sdim bool HasWritebackToken = 6217276479Sdim (static_cast<ARMOperand &>(*Operands[3]).isToken() && 6218276479Sdim static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); 6219261991Sdim bool ListContainsBase; 6220261991Sdim if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo()) 6221261991Sdim return Error(Operands[3 + HasWritebackToken]->getStartLoc(), 6222226633Sdim "registers must be in range r0-r7"); 6223226633Sdim // If we should have writeback, then there should be a '!' token. 6224261991Sdim if (!ListContainsBase && !HasWritebackToken && !isThumbTwo()) 6225226633Sdim return Error(Operands[2]->getStartLoc(), 6226226633Sdim "writeback operator '!' expected"); 6227226633Sdim // If we should not have writeback, there must not be a '!'. This is 6228226633Sdim // true even for the 32-bit wide encodings. 6229261991Sdim if (ListContainsBase && HasWritebackToken) 6230226633Sdim return Error(Operands[3]->getStartLoc(), 6231226633Sdim "writeback operator '!' not allowed when base register " 6232226633Sdim "in register list"); 6233226633Sdim 6234280031Sdim if (validatetLDMRegList(Inst, Operands, 3)) 6235280031Sdim return true; 6236226633Sdim break; 6237226633Sdim } 6238261991Sdim case ARM::LDMIA_UPD: 6239261991Sdim case ARM::LDMDB_UPD: 6240261991Sdim case ARM::LDMIB_UPD: 6241261991Sdim case ARM::LDMDA_UPD: 6242261991Sdim // ARM variants loading and updating the same register are only officially 6243261991Sdim // UNPREDICTABLE on v7 upwards. Goodness knows what they did before. 6244261991Sdim if (!hasV7Ops()) 6245261991Sdim break; 6246280031Sdim if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 6247280031Sdim return Error(Operands.back()->getStartLoc(), 6248280031Sdim "writeback register not allowed in register list"); 6249280031Sdim break; 6250280031Sdim case ARM::t2LDMIA: 6251280031Sdim case ARM::t2LDMDB: 6252280031Sdim if (validatetLDMRegList(Inst, Operands, 3)) 6253280031Sdim return true; 6254280031Sdim break; 6255280031Sdim case ARM::t2STMIA: 6256280031Sdim case ARM::t2STMDB: 6257280031Sdim if (validatetSTMRegList(Inst, Operands, 3)) 6258280031Sdim return true; 6259280031Sdim break; 6260261991Sdim case ARM::t2LDMIA_UPD: 6261261991Sdim case ARM::t2LDMDB_UPD: 6262261991Sdim case ARM::t2STMIA_UPD: 6263261991Sdim case ARM::t2STMDB_UPD: { 6264226633Sdim if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 6265261991Sdim return Error(Operands.back()->getStartLoc(), 6266261991Sdim "writeback register not allowed in register list"); 6267280031Sdim 6268280031Sdim if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) { 6269280031Sdim if (validatetLDMRegList(Inst, Operands, 3)) 6270280031Sdim return true; 6271280031Sdim } else { 6272280031Sdim if (validatetSTMRegList(Inst, Operands, 3)) 6273280031Sdim return true; 6274280031Sdim } 6275261991Sdim break; 6276261991Sdim } 6277261991Sdim case ARM::sysLDMIA_UPD: 6278261991Sdim case ARM::sysLDMDA_UPD: 6279261991Sdim case ARM::sysLDMDB_UPD: 6280261991Sdim case ARM::sysLDMIB_UPD: 6281261991Sdim if (!listContainsReg(Inst, 3, ARM::PC)) 6282226633Sdim return Error(Operands[4]->getStartLoc(), 6283261991Sdim "writeback register only allowed on system LDM " 6284261991Sdim "if PC in register-list"); 6285226633Sdim break; 6286261991Sdim case ARM::sysSTMIA_UPD: 6287261991Sdim case ARM::sysSTMDA_UPD: 6288261991Sdim case ARM::sysSTMDB_UPD: 6289261991Sdim case ARM::sysSTMIB_UPD: 6290261991Sdim return Error(Operands[2]->getStartLoc(), 6291261991Sdim "system STM cannot have writeback register"); 6292243830Sdim case ARM::tMUL: { 6293243830Sdim // The second source operand must be the same register as the destination 6294243830Sdim // operand. 6295243830Sdim // 6296243830Sdim // In this case, we must directly check the parsed operands because the 6297243830Sdim // cvtThumbMultiply() function is written in such a way that it guarantees 6298243830Sdim // this first statement is always true for the new Inst. Essentially, the 6299243830Sdim // destination is unconditionally copied into the second source operand 6300243830Sdim // without checking to see if it matches what we actually parsed. 6301276479Sdim if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() != 6302276479Sdim ((ARMOperand &)*Operands[5]).getReg()) && 6303276479Sdim (((ARMOperand &)*Operands[3]).getReg() != 6304276479Sdim ((ARMOperand &)*Operands[4]).getReg())) { 6305243830Sdim return Error(Operands[3]->getStartLoc(), 6306243830Sdim "destination register must match source register"); 6307243830Sdim } 6308243830Sdim break; 6309243830Sdim } 6310234353Sdim // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 6311234353Sdim // so only issue a diagnostic for thumb1. The instructions will be 6312234353Sdim // switched to the t2 encodings in processInstruction() if necessary. 6313226633Sdim case ARM::tPOP: { 6314261991Sdim bool ListContainsBase; 6315261991Sdim if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && 6316234353Sdim !isThumbTwo()) 6317226633Sdim return Error(Operands[2]->getStartLoc(), 6318226633Sdim "registers must be in range r0-r7 or pc"); 6319280031Sdim if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) 6320280031Sdim return true; 6321226633Sdim break; 6322226633Sdim } 6323226633Sdim case ARM::tPUSH: { 6324261991Sdim bool ListContainsBase; 6325261991Sdim if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && 6326234353Sdim !isThumbTwo()) 6327226633Sdim return Error(Operands[2]->getStartLoc(), 6328226633Sdim "registers must be in range r0-r7 or lr"); 6329280031Sdim if (validatetSTMRegList(Inst, Operands, 2)) 6330280031Sdim return true; 6331226633Sdim break; 6332226633Sdim } 6333226633Sdim case ARM::tSTMIA_UPD: { 6334261991Sdim bool ListContainsBase, InvalidLowList; 6335261991Sdim InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(), 6336261991Sdim 0, ListContainsBase); 6337261991Sdim if (InvalidLowList && !isThumbTwo()) 6338226633Sdim return Error(Operands[4]->getStartLoc(), 6339226633Sdim "registers must be in range r0-r7"); 6340261991Sdim 6341261991Sdim // This would be converted to a 32-bit stm, but that's not valid if the 6342261991Sdim // writeback register is in the list. 6343261991Sdim if (InvalidLowList && ListContainsBase) 6344261991Sdim return Error(Operands[4]->getStartLoc(), 6345261991Sdim "writeback operator '!' not allowed when base register " 6346261991Sdim "in register list"); 6347280031Sdim 6348280031Sdim if (validatetSTMRegList(Inst, Operands, 4)) 6349280031Sdim return true; 6350226633Sdim break; 6351226633Sdim } 6352239462Sdim case ARM::tADDrSP: { 6353239462Sdim // If the non-SP source operand and the destination operand are not the 6354239462Sdim // same, we need thumb2 (for the wide encoding), or we have an error. 6355239462Sdim if (!isThumbTwo() && 6356239462Sdim Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 6357239462Sdim return Error(Operands[4]->getStartLoc(), 6358239462Sdim "source register must be the same as destination"); 6359239462Sdim } 6360239462Sdim break; 6361226633Sdim } 6362261991Sdim // Final range checking for Thumb unconditional branch instructions. 6363261991Sdim case ARM::tB: 6364276479Sdim if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>()) 6365261991Sdim return Error(Operands[2]->getStartLoc(), "branch target out of range"); 6366261991Sdim break; 6367261991Sdim case ARM::t2B: { 6368261991Sdim int op = (Operands[2]->isImm()) ? 2 : 3; 6369276479Sdim if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>()) 6370261991Sdim return Error(Operands[op]->getStartLoc(), "branch target out of range"); 6371261991Sdim break; 6372239462Sdim } 6373261991Sdim // Final range checking for Thumb conditional branch instructions. 6374261991Sdim case ARM::tBcc: 6375276479Sdim if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>()) 6376261991Sdim return Error(Operands[2]->getStartLoc(), "branch target out of range"); 6377261991Sdim break; 6378261991Sdim case ARM::t2Bcc: { 6379261991Sdim int Op = (Operands[2]->isImm()) ? 2 : 3; 6380276479Sdim if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>()) 6381261991Sdim return Error(Operands[Op]->getStartLoc(), "branch target out of range"); 6382261991Sdim break; 6383261991Sdim } 6384276479Sdim case ARM::MOVi16: 6385276479Sdim case ARM::t2MOVi16: 6386276479Sdim case ARM::t2MOVTi16: 6387276479Sdim { 6388276479Sdim // We want to avoid misleadingly allowing something like "mov r0, <symbol>" 6389276479Sdim // especially when we turn it into a movw and the expression <symbol> does 6390276479Sdim // not have a :lower16: or :upper16 as part of the expression. We don't 6391276479Sdim // want the behavior of silently truncating, which can be unexpected and 6392276479Sdim // lead to bugs that are difficult to find since this is an easy mistake 6393276479Sdim // to make. 6394276479Sdim int i = (Operands[3]->isImm()) ? 3 : 4; 6395276479Sdim ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]); 6396276479Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()); 6397276479Sdim if (CE) break; 6398276479Sdim const MCExpr *E = dyn_cast<MCExpr>(Op.getImm()); 6399276479Sdim if (!E) break; 6400276479Sdim const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E); 6401276479Sdim if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 && 6402276479Sdim ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)) 6403276479Sdim return Error( 6404276479Sdim Op.getStartLoc(), 6405276479Sdim "immediate expression for mov requires :lower16: or :upper16"); 6406276479Sdim break; 6407261991Sdim } 6408276479Sdim } 6409226633Sdim 6410226633Sdim return false; 6411226633Sdim} 6412226633Sdim 6413234353Sdimstatic unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 6414234353Sdim switch(Opc) { 6415234353Sdim default: llvm_unreachable("unexpected opcode!"); 6416234353Sdim // VST1LN 6417234353Sdim case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 6418234353Sdim case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 6419234353Sdim case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 6420234353Sdim case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 6421234353Sdim case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 6422234353Sdim case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 6423234353Sdim case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 6424234353Sdim case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 6425234353Sdim case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 6426234353Sdim 6427234353Sdim // VST2LN 6428234353Sdim case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 6429234353Sdim case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 6430234353Sdim case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 6431234353Sdim case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 6432234353Sdim case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 6433234353Sdim 6434234353Sdim case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 6435234353Sdim case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 6436234353Sdim case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 6437234353Sdim case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 6438234353Sdim case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 6439234353Sdim 6440234353Sdim case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 6441234353Sdim case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 6442234353Sdim case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 6443234353Sdim case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 6444234353Sdim case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 6445234353Sdim 6446234353Sdim // VST3LN 6447234353Sdim case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 6448234353Sdim case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 6449234353Sdim case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 6450234353Sdim case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 6451234353Sdim case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 6452234353Sdim case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 6453234353Sdim case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 6454234353Sdim case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 6455234353Sdim case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 6456234353Sdim case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 6457234353Sdim case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 6458234353Sdim case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 6459234353Sdim case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 6460234353Sdim case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 6461234353Sdim case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 6462234353Sdim 6463234353Sdim // VST3 6464234353Sdim case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 6465234353Sdim case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 6466234353Sdim case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 6467234353Sdim case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 6468234353Sdim case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 6469234353Sdim case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 6470234353Sdim case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 6471234353Sdim case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 6472234353Sdim case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 6473234353Sdim case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 6474234353Sdim case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 6475234353Sdim case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 6476234353Sdim case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 6477234353Sdim case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 6478234353Sdim case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 6479234353Sdim case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 6480234353Sdim case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 6481234353Sdim case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 6482234353Sdim 6483234353Sdim // VST4LN 6484234353Sdim case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 6485234353Sdim case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 6486234353Sdim case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 6487234353Sdim case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 6488234353Sdim case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 6489234353Sdim case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 6490234353Sdim case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 6491234353Sdim case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 6492234353Sdim case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 6493234353Sdim case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 6494234353Sdim case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 6495234353Sdim case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 6496234353Sdim case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 6497234353Sdim case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 6498234353Sdim case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 6499234353Sdim 6500234353Sdim // VST4 6501234353Sdim case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 6502234353Sdim case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 6503234353Sdim case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 6504234353Sdim case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 6505234353Sdim case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 6506234353Sdim case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 6507234353Sdim case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 6508234353Sdim case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 6509234353Sdim case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 6510234353Sdim case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 6511234353Sdim case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 6512234353Sdim case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 6513234353Sdim case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 6514234353Sdim case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 6515234353Sdim case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 6516234353Sdim case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 6517234353Sdim case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 6518234353Sdim case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 6519234353Sdim } 6520234353Sdim} 6521234353Sdim 6522234353Sdimstatic unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 6523234353Sdim switch(Opc) { 6524234353Sdim default: llvm_unreachable("unexpected opcode!"); 6525234353Sdim // VLD1LN 6526234353Sdim case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 6527234353Sdim case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 6528234353Sdim case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 6529234353Sdim case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 6530234353Sdim case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 6531234353Sdim case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 6532234353Sdim case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 6533234353Sdim case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 6534234353Sdim case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 6535234353Sdim 6536234353Sdim // VLD2LN 6537234353Sdim case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 6538234353Sdim case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 6539234353Sdim case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 6540234353Sdim case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 6541234353Sdim case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 6542234353Sdim case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 6543234353Sdim case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 6544234353Sdim case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 6545234353Sdim case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 6546234353Sdim case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 6547234353Sdim case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 6548234353Sdim case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 6549234353Sdim case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 6550234353Sdim case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 6551234353Sdim case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 6552234353Sdim 6553234353Sdim // VLD3DUP 6554234353Sdim case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 6555234353Sdim case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 6556234353Sdim case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 6557234353Sdim case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 6558276479Sdim case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 6559234353Sdim case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 6560234353Sdim case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 6561234353Sdim case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 6562234353Sdim case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 6563234353Sdim case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 6564234353Sdim case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 6565234353Sdim case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 6566234353Sdim case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 6567234353Sdim case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 6568234353Sdim case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 6569234353Sdim case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 6570234353Sdim case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 6571234353Sdim case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 6572234353Sdim 6573234353Sdim // VLD3LN 6574234353Sdim case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 6575234353Sdim case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 6576234353Sdim case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 6577234353Sdim case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 6578234353Sdim case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 6579234353Sdim case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 6580234353Sdim case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 6581234353Sdim case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 6582234353Sdim case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 6583234353Sdim case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 6584234353Sdim case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 6585234353Sdim case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 6586234353Sdim case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 6587234353Sdim case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 6588234353Sdim case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 6589234353Sdim 6590234353Sdim // VLD3 6591234353Sdim case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 6592234353Sdim case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 6593234353Sdim case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 6594234353Sdim case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 6595234353Sdim case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 6596234353Sdim case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 6597234353Sdim case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 6598234353Sdim case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 6599234353Sdim case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 6600234353Sdim case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 6601234353Sdim case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 6602234353Sdim case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 6603234353Sdim case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 6604234353Sdim case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 6605234353Sdim case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 6606234353Sdim case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 6607234353Sdim case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 6608234353Sdim case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 6609234353Sdim 6610234353Sdim // VLD4LN 6611234353Sdim case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 6612234353Sdim case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 6613234353Sdim case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 6614276479Sdim case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 6615234353Sdim case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 6616234353Sdim case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 6617234353Sdim case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 6618234353Sdim case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 6619234353Sdim case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 6620234353Sdim case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 6621234353Sdim case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 6622234353Sdim case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 6623234353Sdim case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 6624234353Sdim case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 6625234353Sdim case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 6626234353Sdim 6627234353Sdim // VLD4DUP 6628234353Sdim case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 6629234353Sdim case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 6630234353Sdim case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 6631234353Sdim case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 6632234353Sdim case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 6633234353Sdim case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 6634234353Sdim case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 6635234353Sdim case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 6636234353Sdim case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 6637234353Sdim case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 6638234353Sdim case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 6639234353Sdim case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 6640234353Sdim case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 6641234353Sdim case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 6642234353Sdim case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 6643234353Sdim case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 6644234353Sdim case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 6645234353Sdim case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 6646234353Sdim 6647234353Sdim // VLD4 6648234353Sdim case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 6649234353Sdim case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 6650234353Sdim case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 6651234353Sdim case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 6652234353Sdim case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 6653234353Sdim case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 6654234353Sdim case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 6655234353Sdim case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 6656234353Sdim case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 6657234353Sdim case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 6658234353Sdim case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 6659234353Sdim case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 6660234353Sdim case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 6661234353Sdim case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 6662234353Sdim case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 6663234353Sdim case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 6664234353Sdim case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 6665234353Sdim case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 6666234353Sdim } 6667234353Sdim} 6668234353Sdim 6669276479Sdimbool ARMAsmParser::processInstruction(MCInst &Inst, 6670276537Sdim const OperandVector &Operands, 6671276537Sdim MCStreamer &Out) { 6672226633Sdim switch (Inst.getOpcode()) { 6673276479Sdim // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction. 6674276479Sdim case ARM::LDRT_POST: 6675276479Sdim case ARM::LDRBT_POST: { 6676276479Sdim const unsigned Opcode = 6677276479Sdim (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM 6678276479Sdim : ARM::LDRBT_POST_IMM; 6679276479Sdim MCInst TmpInst; 6680276479Sdim TmpInst.setOpcode(Opcode); 6681276479Sdim TmpInst.addOperand(Inst.getOperand(0)); 6682276479Sdim TmpInst.addOperand(Inst.getOperand(1)); 6683276479Sdim TmpInst.addOperand(Inst.getOperand(1)); 6684288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); 6685288943Sdim TmpInst.addOperand(MCOperand::createImm(0)); 6686276479Sdim TmpInst.addOperand(Inst.getOperand(2)); 6687276479Sdim TmpInst.addOperand(Inst.getOperand(3)); 6688276479Sdim Inst = TmpInst; 6689276479Sdim return true; 6690276479Sdim } 6691276479Sdim // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction. 6692276479Sdim case ARM::STRT_POST: 6693276479Sdim case ARM::STRBT_POST: { 6694276479Sdim const unsigned Opcode = 6695276479Sdim (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM 6696276479Sdim : ARM::STRBT_POST_IMM; 6697276479Sdim MCInst TmpInst; 6698276479Sdim TmpInst.setOpcode(Opcode); 6699276479Sdim TmpInst.addOperand(Inst.getOperand(1)); 6700276479Sdim TmpInst.addOperand(Inst.getOperand(0)); 6701276479Sdim TmpInst.addOperand(Inst.getOperand(1)); 6702288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); 6703288943Sdim TmpInst.addOperand(MCOperand::createImm(0)); 6704276479Sdim TmpInst.addOperand(Inst.getOperand(2)); 6705276479Sdim TmpInst.addOperand(Inst.getOperand(3)); 6706276479Sdim Inst = TmpInst; 6707276479Sdim return true; 6708276479Sdim } 6709243830Sdim // Alias for alternate form of 'ADR Rd, #imm' instruction. 6710243830Sdim case ARM::ADDri: { 6711243830Sdim if (Inst.getOperand(1).getReg() != ARM::PC || 6712276537Sdim Inst.getOperand(5).getReg() != 0 || 6713276537Sdim !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm())) 6714243830Sdim return false; 6715243830Sdim MCInst TmpInst; 6716243830Sdim TmpInst.setOpcode(ARM::ADR); 6717243830Sdim TmpInst.addOperand(Inst.getOperand(0)); 6718276537Sdim if (Inst.getOperand(2).isImm()) { 6719280031Sdim // Immediate (mod_imm) will be in its encoded form, we must unencode it 6720280031Sdim // before passing it to the ADR instruction. 6721280031Sdim unsigned Enc = Inst.getOperand(2).getImm(); 6722288943Sdim TmpInst.addOperand(MCOperand::createImm( 6723280031Sdim ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7))); 6724276537Sdim } else { 6725276537Sdim // Turn PC-relative expression into absolute expression. 6726276537Sdim // Reading PC provides the start of the current instruction + 8 and 6727276537Sdim // the transform to adr is biased by that. 6728288943Sdim MCSymbol *Dot = getContext().createTempSymbol(); 6729276537Sdim Out.EmitLabel(Dot); 6730276537Sdim const MCExpr *OpExpr = Inst.getOperand(2).getExpr(); 6731288943Sdim const MCExpr *InstPC = MCSymbolRefExpr::create(Dot, 6732276537Sdim MCSymbolRefExpr::VK_None, 6733276537Sdim getContext()); 6734288943Sdim const MCExpr *Const8 = MCConstantExpr::create(8, getContext()); 6735288943Sdim const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8, 6736276537Sdim getContext()); 6737288943Sdim const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr, 6738276537Sdim getContext()); 6739288943Sdim TmpInst.addOperand(MCOperand::createExpr(FixupAddr)); 6740276537Sdim } 6741243830Sdim TmpInst.addOperand(Inst.getOperand(3)); 6742243830Sdim TmpInst.addOperand(Inst.getOperand(4)); 6743243830Sdim Inst = TmpInst; 6744243830Sdim return true; 6745243830Sdim } 6746234353Sdim // Aliases for alternate PC+imm syntax of LDR instructions. 6747234353Sdim case ARM::t2LDRpcrel: 6748249423Sdim // Select the narrow version if the immediate will fit. 6749249423Sdim if (Inst.getOperand(1).getImm() > 0 && 6750261991Sdim Inst.getOperand(1).getImm() <= 0xff && 6751276479Sdim !(static_cast<ARMOperand &>(*Operands[2]).isToken() && 6752276479Sdim static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w")) 6753249423Sdim Inst.setOpcode(ARM::tLDRpci); 6754249423Sdim else 6755249423Sdim Inst.setOpcode(ARM::t2LDRpci); 6756234353Sdim return true; 6757234353Sdim case ARM::t2LDRBpcrel: 6758234353Sdim Inst.setOpcode(ARM::t2LDRBpci); 6759234353Sdim return true; 6760234353Sdim case ARM::t2LDRHpcrel: 6761234353Sdim Inst.setOpcode(ARM::t2LDRHpci); 6762234353Sdim return true; 6763234353Sdim case ARM::t2LDRSBpcrel: 6764234353Sdim Inst.setOpcode(ARM::t2LDRSBpci); 6765234353Sdim return true; 6766234353Sdim case ARM::t2LDRSHpcrel: 6767234353Sdim Inst.setOpcode(ARM::t2LDRSHpci); 6768234353Sdim return true; 6769234353Sdim // Handle NEON VST complex aliases. 6770234353Sdim case ARM::VST1LNdWB_register_Asm_8: 6771234353Sdim case ARM::VST1LNdWB_register_Asm_16: 6772234353Sdim case ARM::VST1LNdWB_register_Asm_32: { 6773234353Sdim MCInst TmpInst; 6774234353Sdim // Shuffle the operands around so the lane index operand is in the 6775234353Sdim // right place. 6776234353Sdim unsigned Spacing; 6777234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6778234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6779234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 6780234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 6781234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // Rm 6782234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 6783234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 6784234353Sdim TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6785234353Sdim TmpInst.addOperand(Inst.getOperand(6)); 6786234353Sdim Inst = TmpInst; 6787234353Sdim return true; 6788234353Sdim } 6789234353Sdim 6790234353Sdim case ARM::VST2LNdWB_register_Asm_8: 6791234353Sdim case ARM::VST2LNdWB_register_Asm_16: 6792234353Sdim case ARM::VST2LNdWB_register_Asm_32: 6793234353Sdim case ARM::VST2LNqWB_register_Asm_16: 6794234353Sdim case ARM::VST2LNqWB_register_Asm_32: { 6795234353Sdim MCInst TmpInst; 6796234353Sdim // Shuffle the operands around so the lane index operand is in the 6797234353Sdim // right place. 6798234353Sdim unsigned Spacing; 6799234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6800234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6801234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 6802234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 6803234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // Rm 6804234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 6805288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6806234353Sdim Spacing)); 6807234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 6808234353Sdim TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6809234353Sdim TmpInst.addOperand(Inst.getOperand(6)); 6810234353Sdim Inst = TmpInst; 6811234353Sdim return true; 6812234353Sdim } 6813234353Sdim 6814234353Sdim case ARM::VST3LNdWB_register_Asm_8: 6815234353Sdim case ARM::VST3LNdWB_register_Asm_16: 6816234353Sdim case ARM::VST3LNdWB_register_Asm_32: 6817234353Sdim case ARM::VST3LNqWB_register_Asm_16: 6818234353Sdim case ARM::VST3LNqWB_register_Asm_32: { 6819234353Sdim MCInst TmpInst; 6820234353Sdim // Shuffle the operands around so the lane index operand is in the 6821234353Sdim // right place. 6822234353Sdim unsigned Spacing; 6823234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6824234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6825234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 6826234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 6827234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // Rm 6828234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 6829288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6830234353Sdim Spacing)); 6831288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6832234353Sdim Spacing * 2)); 6833234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 6834234353Sdim TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6835234353Sdim TmpInst.addOperand(Inst.getOperand(6)); 6836234353Sdim Inst = TmpInst; 6837234353Sdim return true; 6838234353Sdim } 6839234353Sdim 6840234353Sdim case ARM::VST4LNdWB_register_Asm_8: 6841234353Sdim case ARM::VST4LNdWB_register_Asm_16: 6842234353Sdim case ARM::VST4LNdWB_register_Asm_32: 6843234353Sdim case ARM::VST4LNqWB_register_Asm_16: 6844234353Sdim case ARM::VST4LNqWB_register_Asm_32: { 6845234353Sdim MCInst TmpInst; 6846234353Sdim // Shuffle the operands around so the lane index operand is in the 6847234353Sdim // right place. 6848234353Sdim unsigned Spacing; 6849234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6850234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6851234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 6852234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 6853234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // Rm 6854234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 6855288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6856234353Sdim Spacing)); 6857288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6858234353Sdim Spacing * 2)); 6859288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6860234353Sdim Spacing * 3)); 6861234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 6862234353Sdim TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6863234353Sdim TmpInst.addOperand(Inst.getOperand(6)); 6864234353Sdim Inst = TmpInst; 6865234353Sdim return true; 6866234353Sdim } 6867234353Sdim 6868234353Sdim case ARM::VST1LNdWB_fixed_Asm_8: 6869234353Sdim case ARM::VST1LNdWB_fixed_Asm_16: 6870234353Sdim case ARM::VST1LNdWB_fixed_Asm_32: { 6871234353Sdim MCInst TmpInst; 6872234353Sdim // Shuffle the operands around so the lane index operand is in the 6873234353Sdim // right place. 6874234353Sdim unsigned Spacing; 6875234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6876234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6877234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 6878234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 6879288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 6880234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 6881234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 6882234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6883234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 6884234353Sdim Inst = TmpInst; 6885234353Sdim return true; 6886234353Sdim } 6887234353Sdim 6888234353Sdim case ARM::VST2LNdWB_fixed_Asm_8: 6889234353Sdim case ARM::VST2LNdWB_fixed_Asm_16: 6890234353Sdim case ARM::VST2LNdWB_fixed_Asm_32: 6891234353Sdim case ARM::VST2LNqWB_fixed_Asm_16: 6892234353Sdim case ARM::VST2LNqWB_fixed_Asm_32: { 6893234353Sdim MCInst TmpInst; 6894234353Sdim // Shuffle the operands around so the lane index operand is in the 6895234353Sdim // right place. 6896234353Sdim unsigned Spacing; 6897234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6898234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6899234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 6900234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 6901288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 6902234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 6903288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6904234353Sdim Spacing)); 6905234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 6906234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6907234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 6908234353Sdim Inst = TmpInst; 6909234353Sdim return true; 6910234353Sdim } 6911234353Sdim 6912234353Sdim case ARM::VST3LNdWB_fixed_Asm_8: 6913234353Sdim case ARM::VST3LNdWB_fixed_Asm_16: 6914234353Sdim case ARM::VST3LNdWB_fixed_Asm_32: 6915234353Sdim case ARM::VST3LNqWB_fixed_Asm_16: 6916234353Sdim case ARM::VST3LNqWB_fixed_Asm_32: { 6917234353Sdim MCInst TmpInst; 6918234353Sdim // Shuffle the operands around so the lane index operand is in the 6919234353Sdim // right place. 6920234353Sdim unsigned Spacing; 6921234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6922234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6923234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 6924234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 6925288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 6926234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 6927288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6928234353Sdim Spacing)); 6929288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6930234353Sdim Spacing * 2)); 6931234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 6932234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6933234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 6934234353Sdim Inst = TmpInst; 6935234353Sdim return true; 6936234353Sdim } 6937234353Sdim 6938234353Sdim case ARM::VST4LNdWB_fixed_Asm_8: 6939234353Sdim case ARM::VST4LNdWB_fixed_Asm_16: 6940234353Sdim case ARM::VST4LNdWB_fixed_Asm_32: 6941234353Sdim case ARM::VST4LNqWB_fixed_Asm_16: 6942234353Sdim case ARM::VST4LNqWB_fixed_Asm_32: { 6943234353Sdim MCInst TmpInst; 6944234353Sdim // Shuffle the operands around so the lane index operand is in the 6945234353Sdim // right place. 6946234353Sdim unsigned Spacing; 6947234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6948234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6949234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 6950234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 6951288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 6952234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 6953288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6954234353Sdim Spacing)); 6955288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6956234353Sdim Spacing * 2)); 6957288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6958234353Sdim Spacing * 3)); 6959234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 6960234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6961234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 6962234353Sdim Inst = TmpInst; 6963234353Sdim return true; 6964234353Sdim } 6965234353Sdim 6966234353Sdim case ARM::VST1LNdAsm_8: 6967234353Sdim case ARM::VST1LNdAsm_16: 6968234353Sdim case ARM::VST1LNdAsm_32: { 6969234353Sdim MCInst TmpInst; 6970234353Sdim // Shuffle the operands around so the lane index operand is in the 6971234353Sdim // right place. 6972234353Sdim unsigned Spacing; 6973234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6974234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 6975234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 6976234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 6977234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 6978234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6979234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 6980234353Sdim Inst = TmpInst; 6981234353Sdim return true; 6982234353Sdim } 6983234353Sdim 6984234353Sdim case ARM::VST2LNdAsm_8: 6985234353Sdim case ARM::VST2LNdAsm_16: 6986234353Sdim case ARM::VST2LNdAsm_32: 6987234353Sdim case ARM::VST2LNqAsm_16: 6988234353Sdim case ARM::VST2LNqAsm_32: { 6989234353Sdim MCInst TmpInst; 6990234353Sdim // Shuffle the operands around so the lane index operand is in the 6991234353Sdim // right place. 6992234353Sdim unsigned Spacing; 6993234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6994234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 6995234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 6996234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 6997288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6998234353Sdim Spacing)); 6999234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7000234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7001234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7002234353Sdim Inst = TmpInst; 7003234353Sdim return true; 7004234353Sdim } 7005234353Sdim 7006234353Sdim case ARM::VST3LNdAsm_8: 7007234353Sdim case ARM::VST3LNdAsm_16: 7008234353Sdim case ARM::VST3LNdAsm_32: 7009234353Sdim case ARM::VST3LNqAsm_16: 7010234353Sdim case ARM::VST3LNqAsm_32: { 7011234353Sdim MCInst TmpInst; 7012234353Sdim // Shuffle the operands around so the lane index operand is in the 7013234353Sdim // right place. 7014234353Sdim unsigned Spacing; 7015234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7016234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7017234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7018234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7019288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7020234353Sdim Spacing)); 7021288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7022234353Sdim Spacing * 2)); 7023234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7024234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7025234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7026234353Sdim Inst = TmpInst; 7027234353Sdim return true; 7028234353Sdim } 7029234353Sdim 7030234353Sdim case ARM::VST4LNdAsm_8: 7031234353Sdim case ARM::VST4LNdAsm_16: 7032234353Sdim case ARM::VST4LNdAsm_32: 7033234353Sdim case ARM::VST4LNqAsm_16: 7034234353Sdim case ARM::VST4LNqAsm_32: { 7035234353Sdim MCInst TmpInst; 7036234353Sdim // Shuffle the operands around so the lane index operand is in the 7037234353Sdim // right place. 7038234353Sdim unsigned Spacing; 7039234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7040234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7041234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7042234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7043288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7044234353Sdim Spacing)); 7045288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7046234353Sdim Spacing * 2)); 7047288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7048234353Sdim Spacing * 3)); 7049234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7050234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7051234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7052234353Sdim Inst = TmpInst; 7053234353Sdim return true; 7054234353Sdim } 7055234353Sdim 7056234353Sdim // Handle NEON VLD complex aliases. 7057234353Sdim case ARM::VLD1LNdWB_register_Asm_8: 7058234353Sdim case ARM::VLD1LNdWB_register_Asm_16: 7059234353Sdim case ARM::VLD1LNdWB_register_Asm_32: { 7060234353Sdim MCInst TmpInst; 7061234353Sdim // Shuffle the operands around so the lane index operand is in the 7062234353Sdim // right place. 7063234353Sdim unsigned Spacing; 7064234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7065234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7066234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7067234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7068234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7069234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // Rm 7070234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7071234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7072234353Sdim TmpInst.addOperand(Inst.getOperand(5)); // CondCode 7073234353Sdim TmpInst.addOperand(Inst.getOperand(6)); 7074234353Sdim Inst = TmpInst; 7075234353Sdim return true; 7076234353Sdim } 7077234353Sdim 7078234353Sdim case ARM::VLD2LNdWB_register_Asm_8: 7079234353Sdim case ARM::VLD2LNdWB_register_Asm_16: 7080234353Sdim case ARM::VLD2LNdWB_register_Asm_32: 7081234353Sdim case ARM::VLD2LNqWB_register_Asm_16: 7082234353Sdim case ARM::VLD2LNqWB_register_Asm_32: { 7083234353Sdim MCInst TmpInst; 7084234353Sdim // Shuffle the operands around so the lane index operand is in the 7085234353Sdim // right place. 7086234353Sdim unsigned Spacing; 7087234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7088234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7089288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7090234353Sdim Spacing)); 7091234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7092234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7093234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7094234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // Rm 7095234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7096288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7097234353Sdim Spacing)); 7098234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7099234353Sdim TmpInst.addOperand(Inst.getOperand(5)); // CondCode 7100234353Sdim TmpInst.addOperand(Inst.getOperand(6)); 7101234353Sdim Inst = TmpInst; 7102234353Sdim return true; 7103234353Sdim } 7104234353Sdim 7105234353Sdim case ARM::VLD3LNdWB_register_Asm_8: 7106234353Sdim case ARM::VLD3LNdWB_register_Asm_16: 7107234353Sdim case ARM::VLD3LNdWB_register_Asm_32: 7108234353Sdim case ARM::VLD3LNqWB_register_Asm_16: 7109234353Sdim case ARM::VLD3LNqWB_register_Asm_32: { 7110234353Sdim MCInst TmpInst; 7111234353Sdim // Shuffle the operands around so the lane index operand is in the 7112234353Sdim // right place. 7113234353Sdim unsigned Spacing; 7114234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7115234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7116288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7117234353Sdim Spacing)); 7118288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7119234353Sdim Spacing * 2)); 7120234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7121234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7122234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7123234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // Rm 7124234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7125288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7126234353Sdim Spacing)); 7127288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7128234353Sdim Spacing * 2)); 7129234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7130234353Sdim TmpInst.addOperand(Inst.getOperand(5)); // CondCode 7131234353Sdim TmpInst.addOperand(Inst.getOperand(6)); 7132234353Sdim Inst = TmpInst; 7133234353Sdim return true; 7134234353Sdim } 7135234353Sdim 7136234353Sdim case ARM::VLD4LNdWB_register_Asm_8: 7137234353Sdim case ARM::VLD4LNdWB_register_Asm_16: 7138234353Sdim case ARM::VLD4LNdWB_register_Asm_32: 7139234353Sdim case ARM::VLD4LNqWB_register_Asm_16: 7140234353Sdim case ARM::VLD4LNqWB_register_Asm_32: { 7141234353Sdim MCInst TmpInst; 7142234353Sdim // Shuffle the operands around so the lane index operand is in the 7143234353Sdim // right place. 7144234353Sdim unsigned Spacing; 7145234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7146234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7147288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7148234353Sdim Spacing)); 7149288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7150234353Sdim Spacing * 2)); 7151288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7152234353Sdim Spacing * 3)); 7153234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7154234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7155234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7156234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // Rm 7157234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7158288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7159234353Sdim Spacing)); 7160288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7161234353Sdim Spacing * 2)); 7162288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7163234353Sdim Spacing * 3)); 7164234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7165234353Sdim TmpInst.addOperand(Inst.getOperand(5)); // CondCode 7166234353Sdim TmpInst.addOperand(Inst.getOperand(6)); 7167234353Sdim Inst = TmpInst; 7168234353Sdim return true; 7169234353Sdim } 7170234353Sdim 7171234353Sdim case ARM::VLD1LNdWB_fixed_Asm_8: 7172234353Sdim case ARM::VLD1LNdWB_fixed_Asm_16: 7173234353Sdim case ARM::VLD1LNdWB_fixed_Asm_32: { 7174234353Sdim MCInst TmpInst; 7175234353Sdim // Shuffle the operands around so the lane index operand is in the 7176234353Sdim // right place. 7177234353Sdim unsigned Spacing; 7178234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7179234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7180234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7181234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7182234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7183288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7184234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7185234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7186234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7187234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7188234353Sdim Inst = TmpInst; 7189234353Sdim return true; 7190234353Sdim } 7191234353Sdim 7192234353Sdim case ARM::VLD2LNdWB_fixed_Asm_8: 7193234353Sdim case ARM::VLD2LNdWB_fixed_Asm_16: 7194234353Sdim case ARM::VLD2LNdWB_fixed_Asm_32: 7195234353Sdim case ARM::VLD2LNqWB_fixed_Asm_16: 7196234353Sdim case ARM::VLD2LNqWB_fixed_Asm_32: { 7197234353Sdim MCInst TmpInst; 7198234353Sdim // Shuffle the operands around so the lane index operand is in the 7199234353Sdim // right place. 7200234353Sdim unsigned Spacing; 7201234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7202234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7203288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7204234353Sdim Spacing)); 7205234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7206234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7207234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7208288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7209234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7210288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7211234353Sdim Spacing)); 7212234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7213234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7214234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7215234353Sdim Inst = TmpInst; 7216234353Sdim return true; 7217234353Sdim } 7218234353Sdim 7219234353Sdim case ARM::VLD3LNdWB_fixed_Asm_8: 7220234353Sdim case ARM::VLD3LNdWB_fixed_Asm_16: 7221234353Sdim case ARM::VLD3LNdWB_fixed_Asm_32: 7222234353Sdim case ARM::VLD3LNqWB_fixed_Asm_16: 7223234353Sdim case ARM::VLD3LNqWB_fixed_Asm_32: { 7224234353Sdim MCInst TmpInst; 7225234353Sdim // Shuffle the operands around so the lane index operand is in the 7226234353Sdim // right place. 7227234353Sdim unsigned Spacing; 7228234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7229234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7230288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7231234353Sdim Spacing)); 7232288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7233234353Sdim Spacing * 2)); 7234234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7235234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7236234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7237288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7238234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7239288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7240234353Sdim Spacing)); 7241288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7242234353Sdim Spacing * 2)); 7243234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7244234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7245234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7246234353Sdim Inst = TmpInst; 7247234353Sdim return true; 7248234353Sdim } 7249234353Sdim 7250234353Sdim case ARM::VLD4LNdWB_fixed_Asm_8: 7251234353Sdim case ARM::VLD4LNdWB_fixed_Asm_16: 7252234353Sdim case ARM::VLD4LNdWB_fixed_Asm_32: 7253234353Sdim case ARM::VLD4LNqWB_fixed_Asm_16: 7254234353Sdim case ARM::VLD4LNqWB_fixed_Asm_32: { 7255234353Sdim MCInst TmpInst; 7256234353Sdim // Shuffle the operands around so the lane index operand is in the 7257234353Sdim // right place. 7258234353Sdim unsigned Spacing; 7259234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7260234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7261288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7262234353Sdim Spacing)); 7263288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7264234353Sdim Spacing * 2)); 7265288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7266234353Sdim Spacing * 3)); 7267234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7268234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7269234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7270288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7271234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7272288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7273234353Sdim Spacing)); 7274288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7275234353Sdim Spacing * 2)); 7276288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7277234353Sdim Spacing * 3)); 7278234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7279234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7280234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7281234353Sdim Inst = TmpInst; 7282234353Sdim return true; 7283234353Sdim } 7284234353Sdim 7285234353Sdim case ARM::VLD1LNdAsm_8: 7286234353Sdim case ARM::VLD1LNdAsm_16: 7287234353Sdim case ARM::VLD1LNdAsm_32: { 7288234353Sdim MCInst TmpInst; 7289234353Sdim // Shuffle the operands around so the lane index operand is in the 7290234353Sdim // right place. 7291234353Sdim unsigned Spacing; 7292234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7293234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7294234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7295234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7296234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7297234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7298234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7299234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7300234353Sdim Inst = TmpInst; 7301234353Sdim return true; 7302234353Sdim } 7303234353Sdim 7304234353Sdim case ARM::VLD2LNdAsm_8: 7305234353Sdim case ARM::VLD2LNdAsm_16: 7306234353Sdim case ARM::VLD2LNdAsm_32: 7307234353Sdim case ARM::VLD2LNqAsm_16: 7308234353Sdim case ARM::VLD2LNqAsm_32: { 7309234353Sdim MCInst TmpInst; 7310234353Sdim // Shuffle the operands around so the lane index operand is in the 7311234353Sdim // right place. 7312234353Sdim unsigned Spacing; 7313234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7314234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7315288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7316234353Sdim Spacing)); 7317234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7318234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7319234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7320288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7321234353Sdim Spacing)); 7322234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7323234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7324234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7325234353Sdim Inst = TmpInst; 7326234353Sdim return true; 7327234353Sdim } 7328234353Sdim 7329234353Sdim case ARM::VLD3LNdAsm_8: 7330234353Sdim case ARM::VLD3LNdAsm_16: 7331234353Sdim case ARM::VLD3LNdAsm_32: 7332234353Sdim case ARM::VLD3LNqAsm_16: 7333234353Sdim case ARM::VLD3LNqAsm_32: { 7334234353Sdim MCInst TmpInst; 7335234353Sdim // Shuffle the operands around so the lane index operand is in the 7336234353Sdim // right place. 7337234353Sdim unsigned Spacing; 7338234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7339234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7340288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7341234353Sdim Spacing)); 7342288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7343234353Sdim Spacing * 2)); 7344234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7345234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7346234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7347288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7348234353Sdim Spacing)); 7349288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7350234353Sdim Spacing * 2)); 7351234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7352234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7353234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7354234353Sdim Inst = TmpInst; 7355234353Sdim return true; 7356234353Sdim } 7357234353Sdim 7358234353Sdim case ARM::VLD4LNdAsm_8: 7359234353Sdim case ARM::VLD4LNdAsm_16: 7360234353Sdim case ARM::VLD4LNdAsm_32: 7361234353Sdim case ARM::VLD4LNqAsm_16: 7362234353Sdim case ARM::VLD4LNqAsm_32: { 7363234353Sdim MCInst TmpInst; 7364234353Sdim // Shuffle the operands around so the lane index operand is in the 7365234353Sdim // right place. 7366234353Sdim unsigned Spacing; 7367234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7368234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7369288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7370234353Sdim Spacing)); 7371288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7372234353Sdim Spacing * 2)); 7373288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7374234353Sdim Spacing * 3)); 7375234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rn 7376234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // alignment 7377234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7378288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7379234353Sdim Spacing)); 7380288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7381234353Sdim Spacing * 2)); 7382288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7383234353Sdim Spacing * 3)); 7384234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // lane 7385234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7386234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7387234353Sdim Inst = TmpInst; 7388234353Sdim return true; 7389234353Sdim } 7390234353Sdim 7391234353Sdim // VLD3DUP single 3-element structure to all lanes instructions. 7392234353Sdim case ARM::VLD3DUPdAsm_8: 7393234353Sdim case ARM::VLD3DUPdAsm_16: 7394234353Sdim case ARM::VLD3DUPdAsm_32: 7395234353Sdim case ARM::VLD3DUPqAsm_8: 7396234353Sdim case ARM::VLD3DUPqAsm_16: 7397234353Sdim case ARM::VLD3DUPqAsm_32: { 7398234353Sdim MCInst TmpInst; 7399234353Sdim unsigned Spacing; 7400234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7401234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7402288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7403234353Sdim Spacing)); 7404288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7405234353Sdim Spacing * 2)); 7406234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7407234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7408234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7409234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7410234353Sdim Inst = TmpInst; 7411234353Sdim return true; 7412234353Sdim } 7413234353Sdim 7414234353Sdim case ARM::VLD3DUPdWB_fixed_Asm_8: 7415234353Sdim case ARM::VLD3DUPdWB_fixed_Asm_16: 7416234353Sdim case ARM::VLD3DUPdWB_fixed_Asm_32: 7417234353Sdim case ARM::VLD3DUPqWB_fixed_Asm_8: 7418234353Sdim case ARM::VLD3DUPqWB_fixed_Asm_16: 7419234353Sdim case ARM::VLD3DUPqWB_fixed_Asm_32: { 7420234353Sdim MCInst TmpInst; 7421234353Sdim unsigned Spacing; 7422234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7423234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7424288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7425234353Sdim Spacing)); 7426288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7427234353Sdim Spacing * 2)); 7428234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7429234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7430234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7431288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7432234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7433234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7434234353Sdim Inst = TmpInst; 7435234353Sdim return true; 7436234353Sdim } 7437234353Sdim 7438234353Sdim case ARM::VLD3DUPdWB_register_Asm_8: 7439234353Sdim case ARM::VLD3DUPdWB_register_Asm_16: 7440234353Sdim case ARM::VLD3DUPdWB_register_Asm_32: 7441234353Sdim case ARM::VLD3DUPqWB_register_Asm_8: 7442234353Sdim case ARM::VLD3DUPqWB_register_Asm_16: 7443234353Sdim case ARM::VLD3DUPqWB_register_Asm_32: { 7444234353Sdim MCInst TmpInst; 7445234353Sdim unsigned Spacing; 7446234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7447234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7448288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7449234353Sdim Spacing)); 7450288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7451234353Sdim Spacing * 2)); 7452234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7453234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7454234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7455234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // Rm 7456234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7457234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7458234353Sdim Inst = TmpInst; 7459234353Sdim return true; 7460234353Sdim } 7461234353Sdim 7462234353Sdim // VLD3 multiple 3-element structure instructions. 7463234353Sdim case ARM::VLD3dAsm_8: 7464234353Sdim case ARM::VLD3dAsm_16: 7465234353Sdim case ARM::VLD3dAsm_32: 7466234353Sdim case ARM::VLD3qAsm_8: 7467234353Sdim case ARM::VLD3qAsm_16: 7468234353Sdim case ARM::VLD3qAsm_32: { 7469234353Sdim MCInst TmpInst; 7470234353Sdim unsigned Spacing; 7471234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7472234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7473288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7474234353Sdim Spacing)); 7475288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7476234353Sdim Spacing * 2)); 7477234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7478234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7479234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7480234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7481234353Sdim Inst = TmpInst; 7482234353Sdim return true; 7483234353Sdim } 7484234353Sdim 7485234353Sdim case ARM::VLD3dWB_fixed_Asm_8: 7486234353Sdim case ARM::VLD3dWB_fixed_Asm_16: 7487234353Sdim case ARM::VLD3dWB_fixed_Asm_32: 7488234353Sdim case ARM::VLD3qWB_fixed_Asm_8: 7489234353Sdim case ARM::VLD3qWB_fixed_Asm_16: 7490234353Sdim case ARM::VLD3qWB_fixed_Asm_32: { 7491234353Sdim MCInst TmpInst; 7492234353Sdim unsigned Spacing; 7493234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7494234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7495288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7496234353Sdim Spacing)); 7497288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7498234353Sdim Spacing * 2)); 7499234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7500234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7501234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7502288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7503234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7504234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7505234353Sdim Inst = TmpInst; 7506234353Sdim return true; 7507234353Sdim } 7508234353Sdim 7509234353Sdim case ARM::VLD3dWB_register_Asm_8: 7510234353Sdim case ARM::VLD3dWB_register_Asm_16: 7511234353Sdim case ARM::VLD3dWB_register_Asm_32: 7512234353Sdim case ARM::VLD3qWB_register_Asm_8: 7513234353Sdim case ARM::VLD3qWB_register_Asm_16: 7514234353Sdim case ARM::VLD3qWB_register_Asm_32: { 7515234353Sdim MCInst TmpInst; 7516234353Sdim unsigned Spacing; 7517234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7518234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7519288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7520234353Sdim Spacing)); 7521288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7522234353Sdim Spacing * 2)); 7523234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7524234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7525234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7526234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // Rm 7527234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7528234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7529234353Sdim Inst = TmpInst; 7530234353Sdim return true; 7531234353Sdim } 7532234353Sdim 7533234353Sdim // VLD4DUP single 3-element structure to all lanes instructions. 7534234353Sdim case ARM::VLD4DUPdAsm_8: 7535234353Sdim case ARM::VLD4DUPdAsm_16: 7536234353Sdim case ARM::VLD4DUPdAsm_32: 7537234353Sdim case ARM::VLD4DUPqAsm_8: 7538234353Sdim case ARM::VLD4DUPqAsm_16: 7539234353Sdim case ARM::VLD4DUPqAsm_32: { 7540234353Sdim MCInst TmpInst; 7541234353Sdim unsigned Spacing; 7542234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7543234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7544288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7545234353Sdim Spacing)); 7546288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7547234353Sdim Spacing * 2)); 7548288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7549234353Sdim Spacing * 3)); 7550234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7551234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7552234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7553234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7554234353Sdim Inst = TmpInst; 7555234353Sdim return true; 7556234353Sdim } 7557234353Sdim 7558234353Sdim case ARM::VLD4DUPdWB_fixed_Asm_8: 7559234353Sdim case ARM::VLD4DUPdWB_fixed_Asm_16: 7560234353Sdim case ARM::VLD4DUPdWB_fixed_Asm_32: 7561234353Sdim case ARM::VLD4DUPqWB_fixed_Asm_8: 7562234353Sdim case ARM::VLD4DUPqWB_fixed_Asm_16: 7563234353Sdim case ARM::VLD4DUPqWB_fixed_Asm_32: { 7564234353Sdim MCInst TmpInst; 7565234353Sdim unsigned Spacing; 7566234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7567234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7568288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7569234353Sdim Spacing)); 7570288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7571234353Sdim Spacing * 2)); 7572288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7573234353Sdim Spacing * 3)); 7574234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7575234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7576234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7577288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7578234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7579234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7580234353Sdim Inst = TmpInst; 7581234353Sdim return true; 7582234353Sdim } 7583234353Sdim 7584234353Sdim case ARM::VLD4DUPdWB_register_Asm_8: 7585234353Sdim case ARM::VLD4DUPdWB_register_Asm_16: 7586234353Sdim case ARM::VLD4DUPdWB_register_Asm_32: 7587234353Sdim case ARM::VLD4DUPqWB_register_Asm_8: 7588234353Sdim case ARM::VLD4DUPqWB_register_Asm_16: 7589234353Sdim case ARM::VLD4DUPqWB_register_Asm_32: { 7590234353Sdim MCInst TmpInst; 7591234353Sdim unsigned Spacing; 7592234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7593234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7594288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7595234353Sdim Spacing)); 7596288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7597234353Sdim Spacing * 2)); 7598288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7599234353Sdim Spacing * 3)); 7600234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7601234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7602234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7603234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // Rm 7604234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7605234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7606234353Sdim Inst = TmpInst; 7607234353Sdim return true; 7608234353Sdim } 7609234353Sdim 7610234353Sdim // VLD4 multiple 4-element structure instructions. 7611234353Sdim case ARM::VLD4dAsm_8: 7612234353Sdim case ARM::VLD4dAsm_16: 7613234353Sdim case ARM::VLD4dAsm_32: 7614234353Sdim case ARM::VLD4qAsm_8: 7615234353Sdim case ARM::VLD4qAsm_16: 7616234353Sdim case ARM::VLD4qAsm_32: { 7617234353Sdim MCInst TmpInst; 7618234353Sdim unsigned Spacing; 7619234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7620234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7621288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7622234353Sdim Spacing)); 7623288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7624234353Sdim Spacing * 2)); 7625288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7626234353Sdim Spacing * 3)); 7627234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7628234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7629234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7630234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7631234353Sdim Inst = TmpInst; 7632234353Sdim return true; 7633234353Sdim } 7634234353Sdim 7635234353Sdim case ARM::VLD4dWB_fixed_Asm_8: 7636234353Sdim case ARM::VLD4dWB_fixed_Asm_16: 7637234353Sdim case ARM::VLD4dWB_fixed_Asm_32: 7638234353Sdim case ARM::VLD4qWB_fixed_Asm_8: 7639234353Sdim case ARM::VLD4qWB_fixed_Asm_16: 7640234353Sdim case ARM::VLD4qWB_fixed_Asm_32: { 7641234353Sdim MCInst TmpInst; 7642234353Sdim unsigned Spacing; 7643234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7644234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7645288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7646234353Sdim Spacing)); 7647288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7648234353Sdim Spacing * 2)); 7649288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7650234353Sdim Spacing * 3)); 7651234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7652234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7653234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7654288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7655234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7656234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7657234353Sdim Inst = TmpInst; 7658234353Sdim return true; 7659234353Sdim } 7660234353Sdim 7661234353Sdim case ARM::VLD4dWB_register_Asm_8: 7662234353Sdim case ARM::VLD4dWB_register_Asm_16: 7663234353Sdim case ARM::VLD4dWB_register_Asm_32: 7664234353Sdim case ARM::VLD4qWB_register_Asm_8: 7665234353Sdim case ARM::VLD4qWB_register_Asm_16: 7666234353Sdim case ARM::VLD4qWB_register_Asm_32: { 7667234353Sdim MCInst TmpInst; 7668234353Sdim unsigned Spacing; 7669234353Sdim TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7670234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7671288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7672234353Sdim Spacing)); 7673288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7674234353Sdim Spacing * 2)); 7675288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7676234353Sdim Spacing * 3)); 7677234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7678234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7679234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7680234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // Rm 7681234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7682234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7683234353Sdim Inst = TmpInst; 7684234353Sdim return true; 7685234353Sdim } 7686234353Sdim 7687234353Sdim // VST3 multiple 3-element structure instructions. 7688234353Sdim case ARM::VST3dAsm_8: 7689234353Sdim case ARM::VST3dAsm_16: 7690234353Sdim case ARM::VST3dAsm_32: 7691234353Sdim case ARM::VST3qAsm_8: 7692234353Sdim case ARM::VST3qAsm_16: 7693234353Sdim case ARM::VST3qAsm_32: { 7694234353Sdim MCInst TmpInst; 7695234353Sdim unsigned Spacing; 7696234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7697234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7698234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7699234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7700288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7701234353Sdim Spacing)); 7702288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7703234353Sdim Spacing * 2)); 7704234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7705234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7706234353Sdim Inst = TmpInst; 7707234353Sdim return true; 7708234353Sdim } 7709234353Sdim 7710234353Sdim case ARM::VST3dWB_fixed_Asm_8: 7711234353Sdim case ARM::VST3dWB_fixed_Asm_16: 7712234353Sdim case ARM::VST3dWB_fixed_Asm_32: 7713234353Sdim case ARM::VST3qWB_fixed_Asm_8: 7714234353Sdim case ARM::VST3qWB_fixed_Asm_16: 7715234353Sdim case ARM::VST3qWB_fixed_Asm_32: { 7716234353Sdim MCInst TmpInst; 7717234353Sdim unsigned Spacing; 7718234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7719234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7720234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7721234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7722288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7723234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7724288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7725234353Sdim Spacing)); 7726288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7727234353Sdim Spacing * 2)); 7728234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7729234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7730234353Sdim Inst = TmpInst; 7731234353Sdim return true; 7732234353Sdim } 7733234353Sdim 7734234353Sdim case ARM::VST3dWB_register_Asm_8: 7735234353Sdim case ARM::VST3dWB_register_Asm_16: 7736234353Sdim case ARM::VST3dWB_register_Asm_32: 7737234353Sdim case ARM::VST3qWB_register_Asm_8: 7738234353Sdim case ARM::VST3qWB_register_Asm_16: 7739234353Sdim case ARM::VST3qWB_register_Asm_32: { 7740234353Sdim MCInst TmpInst; 7741234353Sdim unsigned Spacing; 7742234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7743234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7744234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7745234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7746234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // Rm 7747234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7748288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7749234353Sdim Spacing)); 7750288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7751234353Sdim Spacing * 2)); 7752234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7753234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7754234353Sdim Inst = TmpInst; 7755234353Sdim return true; 7756234353Sdim } 7757234353Sdim 7758234353Sdim // VST4 multiple 3-element structure instructions. 7759234353Sdim case ARM::VST4dAsm_8: 7760234353Sdim case ARM::VST4dAsm_16: 7761234353Sdim case ARM::VST4dAsm_32: 7762234353Sdim case ARM::VST4qAsm_8: 7763234353Sdim case ARM::VST4qAsm_16: 7764234353Sdim case ARM::VST4qAsm_32: { 7765234353Sdim MCInst TmpInst; 7766234353Sdim unsigned Spacing; 7767234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7768234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7769234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7770234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7771288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7772234353Sdim Spacing)); 7773288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7774234353Sdim Spacing * 2)); 7775288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7776234353Sdim Spacing * 3)); 7777234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7778234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7779234353Sdim Inst = TmpInst; 7780234353Sdim return true; 7781234353Sdim } 7782234353Sdim 7783234353Sdim case ARM::VST4dWB_fixed_Asm_8: 7784234353Sdim case ARM::VST4dWB_fixed_Asm_16: 7785234353Sdim case ARM::VST4dWB_fixed_Asm_32: 7786234353Sdim case ARM::VST4qWB_fixed_Asm_8: 7787234353Sdim case ARM::VST4qWB_fixed_Asm_16: 7788234353Sdim case ARM::VST4qWB_fixed_Asm_32: { 7789234353Sdim MCInst TmpInst; 7790234353Sdim unsigned Spacing; 7791234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7792234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7793234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7794234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7795288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7796234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7797288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7798234353Sdim Spacing)); 7799288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7800234353Sdim Spacing * 2)); 7801288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7802234353Sdim Spacing * 3)); 7803234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7804234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7805234353Sdim Inst = TmpInst; 7806234353Sdim return true; 7807234353Sdim } 7808234353Sdim 7809234353Sdim case ARM::VST4dWB_register_Asm_8: 7810234353Sdim case ARM::VST4dWB_register_Asm_16: 7811234353Sdim case ARM::VST4dWB_register_Asm_32: 7812234353Sdim case ARM::VST4qWB_register_Asm_8: 7813234353Sdim case ARM::VST4qWB_register_Asm_16: 7814234353Sdim case ARM::VST4qWB_register_Asm_32: { 7815234353Sdim MCInst TmpInst; 7816234353Sdim unsigned Spacing; 7817234353Sdim TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7818234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7819234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7820234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // alignment 7821234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // Rm 7822234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Vd 7823288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7824234353Sdim Spacing)); 7825288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7826234353Sdim Spacing * 2)); 7827288943Sdim TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7828234353Sdim Spacing * 3)); 7829234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7830234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7831234353Sdim Inst = TmpInst; 7832234353Sdim return true; 7833234353Sdim } 7834234353Sdim 7835234353Sdim // Handle encoding choice for the shift-immediate instructions. 7836234353Sdim case ARM::t2LSLri: 7837234353Sdim case ARM::t2LSRri: 7838234353Sdim case ARM::t2ASRri: { 7839234353Sdim if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7840234353Sdim Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7841234353Sdim Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 7842276479Sdim !(static_cast<ARMOperand &>(*Operands[3]).isToken() && 7843276479Sdim static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) { 7844234353Sdim unsigned NewOpc; 7845234353Sdim switch (Inst.getOpcode()) { 7846234353Sdim default: llvm_unreachable("unexpected opcode"); 7847234353Sdim case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 7848234353Sdim case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 7849234353Sdim case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 7850234353Sdim } 7851234353Sdim // The Thumb1 operands aren't in the same order. Awesome, eh? 7852234353Sdim MCInst TmpInst; 7853234353Sdim TmpInst.setOpcode(NewOpc); 7854234353Sdim TmpInst.addOperand(Inst.getOperand(0)); 7855234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7856234353Sdim TmpInst.addOperand(Inst.getOperand(1)); 7857234353Sdim TmpInst.addOperand(Inst.getOperand(2)); 7858234353Sdim TmpInst.addOperand(Inst.getOperand(3)); 7859234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7860234353Sdim Inst = TmpInst; 7861234353Sdim return true; 7862234353Sdim } 7863234353Sdim return false; 7864234353Sdim } 7865234353Sdim 7866234353Sdim // Handle the Thumb2 mode MOV complex aliases. 7867234353Sdim case ARM::t2MOVsr: 7868234353Sdim case ARM::t2MOVSsr: { 7869234353Sdim // Which instruction to expand to depends on the CCOut operand and 7870234353Sdim // whether we're in an IT block if the register operands are low 7871234353Sdim // registers. 7872234353Sdim bool isNarrow = false; 7873234353Sdim if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7874234353Sdim isARMLowRegister(Inst.getOperand(1).getReg()) && 7875234353Sdim isARMLowRegister(Inst.getOperand(2).getReg()) && 7876234353Sdim Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7877234353Sdim inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 7878234353Sdim isNarrow = true; 7879234353Sdim MCInst TmpInst; 7880234353Sdim unsigned newOpc; 7881234353Sdim switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 7882234353Sdim default: llvm_unreachable("unexpected opcode!"); 7883234353Sdim case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 7884234353Sdim case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 7885234353Sdim case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 7886234353Sdim case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 7887234353Sdim } 7888234353Sdim TmpInst.setOpcode(newOpc); 7889234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Rd 7890234353Sdim if (isNarrow) 7891288943Sdim TmpInst.addOperand(MCOperand::createReg( 7892234353Sdim Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7893234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7894234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rm 7895234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7896234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 7897234353Sdim if (!isNarrow) 7898288943Sdim TmpInst.addOperand(MCOperand::createReg( 7899234353Sdim Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7900234353Sdim Inst = TmpInst; 7901234353Sdim return true; 7902234353Sdim } 7903234353Sdim case ARM::t2MOVsi: 7904234353Sdim case ARM::t2MOVSsi: { 7905234353Sdim // Which instruction to expand to depends on the CCOut operand and 7906234353Sdim // whether we're in an IT block if the register operands are low 7907234353Sdim // registers. 7908234353Sdim bool isNarrow = false; 7909234353Sdim if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7910234353Sdim isARMLowRegister(Inst.getOperand(1).getReg()) && 7911234353Sdim inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 7912234353Sdim isNarrow = true; 7913234353Sdim MCInst TmpInst; 7914234353Sdim unsigned newOpc; 7915234353Sdim switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 7916234353Sdim default: llvm_unreachable("unexpected opcode!"); 7917234353Sdim case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 7918234353Sdim case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 7919234353Sdim case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 7920234353Sdim case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 7921234353Sdim case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 7922234353Sdim } 7923239462Sdim unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 7924239462Sdim if (Amount == 32) Amount = 0; 7925234353Sdim TmpInst.setOpcode(newOpc); 7926234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Rd 7927234353Sdim if (isNarrow) 7928288943Sdim TmpInst.addOperand(MCOperand::createReg( 7929234353Sdim Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7930234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7931234353Sdim if (newOpc != ARM::t2RRX) 7932288943Sdim TmpInst.addOperand(MCOperand::createImm(Amount)); 7933234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7934234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7935234353Sdim if (!isNarrow) 7936288943Sdim TmpInst.addOperand(MCOperand::createReg( 7937234353Sdim Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7938234353Sdim Inst = TmpInst; 7939234353Sdim return true; 7940234353Sdim } 7941234353Sdim // Handle the ARM mode MOV complex aliases. 7942234353Sdim case ARM::ASRr: 7943234353Sdim case ARM::LSRr: 7944234353Sdim case ARM::LSLr: 7945234353Sdim case ARM::RORr: { 7946234353Sdim ARM_AM::ShiftOpc ShiftTy; 7947234353Sdim switch(Inst.getOpcode()) { 7948234353Sdim default: llvm_unreachable("unexpected opcode!"); 7949234353Sdim case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 7950234353Sdim case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 7951234353Sdim case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 7952234353Sdim case ARM::RORr: ShiftTy = ARM_AM::ror; break; 7953234353Sdim } 7954234353Sdim unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 7955234353Sdim MCInst TmpInst; 7956234353Sdim TmpInst.setOpcode(ARM::MOVsr); 7957234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Rd 7958234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7959234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // Rm 7960288943Sdim TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty 7961234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7962234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7963234353Sdim TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7964234353Sdim Inst = TmpInst; 7965234353Sdim return true; 7966234353Sdim } 7967234353Sdim case ARM::ASRi: 7968234353Sdim case ARM::LSRi: 7969234353Sdim case ARM::LSLi: 7970234353Sdim case ARM::RORi: { 7971234353Sdim ARM_AM::ShiftOpc ShiftTy; 7972234353Sdim switch(Inst.getOpcode()) { 7973234353Sdim default: llvm_unreachable("unexpected opcode!"); 7974234353Sdim case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 7975234353Sdim case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 7976234353Sdim case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 7977234353Sdim case ARM::RORi: ShiftTy = ARM_AM::ror; break; 7978234353Sdim } 7979234353Sdim // A shift by zero is a plain MOVr, not a MOVsi. 7980234353Sdim unsigned Amt = Inst.getOperand(2).getImm(); 7981234353Sdim unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 7982239462Sdim // A shift by 32 should be encoded as 0 when permitted 7983239462Sdim if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 7984239462Sdim Amt = 0; 7985234353Sdim unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 7986234353Sdim MCInst TmpInst; 7987234353Sdim TmpInst.setOpcode(Opc); 7988234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Rd 7989234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 7990234353Sdim if (Opc == ARM::MOVsi) 7991288943Sdim TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty 7992234353Sdim TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7993234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 7994234353Sdim TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7995234353Sdim Inst = TmpInst; 7996234353Sdim return true; 7997234353Sdim } 7998234353Sdim case ARM::RRXi: { 7999234353Sdim unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 8000234353Sdim MCInst TmpInst; 8001234353Sdim TmpInst.setOpcode(ARM::MOVsi); 8002234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Rd 8003234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 8004288943Sdim TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty 8005234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8006234353Sdim TmpInst.addOperand(Inst.getOperand(3)); 8007234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // cc_out 8008234353Sdim Inst = TmpInst; 8009234353Sdim return true; 8010234353Sdim } 8011234353Sdim case ARM::t2LDMIA_UPD: { 8012234353Sdim // If this is a load of a single register, then we should use 8013234353Sdim // a post-indexed LDR instruction instead, per the ARM ARM. 8014234353Sdim if (Inst.getNumOperands() != 5) 8015234353Sdim return false; 8016234353Sdim MCInst TmpInst; 8017234353Sdim TmpInst.setOpcode(ARM::t2LDR_POST); 8018234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // Rt 8019234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 8020234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 8021288943Sdim TmpInst.addOperand(MCOperand::createImm(4)); 8022234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8023234353Sdim TmpInst.addOperand(Inst.getOperand(3)); 8024234353Sdim Inst = TmpInst; 8025234353Sdim return true; 8026234353Sdim } 8027234353Sdim case ARM::t2STMDB_UPD: { 8028234353Sdim // If this is a store of a single register, then we should use 8029234353Sdim // a pre-indexed STR instruction instead, per the ARM ARM. 8030234353Sdim if (Inst.getNumOperands() != 5) 8031234353Sdim return false; 8032234353Sdim MCInst TmpInst; 8033234353Sdim TmpInst.setOpcode(ARM::t2STR_PRE); 8034234353Sdim TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 8035234353Sdim TmpInst.addOperand(Inst.getOperand(4)); // Rt 8036234353Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 8037288943Sdim TmpInst.addOperand(MCOperand::createImm(-4)); 8038234353Sdim TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8039234353Sdim TmpInst.addOperand(Inst.getOperand(3)); 8040234353Sdim Inst = TmpInst; 8041234353Sdim return true; 8042234353Sdim } 8043226633Sdim case ARM::LDMIA_UPD: 8044226633Sdim // If this is a load of a single register via a 'pop', then we should use 8045226633Sdim // a post-indexed LDR instruction instead, per the ARM ARM. 8046276479Sdim if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" && 8047226633Sdim Inst.getNumOperands() == 5) { 8048226633Sdim MCInst TmpInst; 8049226633Sdim TmpInst.setOpcode(ARM::LDR_POST_IMM); 8050226633Sdim TmpInst.addOperand(Inst.getOperand(4)); // Rt 8051226633Sdim TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 8052226633Sdim TmpInst.addOperand(Inst.getOperand(1)); // Rn 8053288943Sdim TmpInst.addOperand(MCOperand::createReg(0)); // am2offset 8054288943Sdim TmpInst.addOperand(MCOperand::createImm(4)); 8055226633Sdim TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8056226633Sdim TmpInst.addOperand(Inst.getOperand(3)); 8057226633Sdim Inst = TmpInst; 8058234353Sdim return true; 8059226633Sdim } 8060226633Sdim break; 8061226633Sdim case ARM::STMDB_UPD: 8062226633Sdim // If this is a store of a single register via a 'push', then we should use 8063226633Sdim // a pre-indexed STR instruction instead, per the ARM ARM. 8064276479Sdim if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" && 8065226633Sdim Inst.getNumOperands() == 5) { 8066226633Sdim MCInst TmpInst; 8067226633Sdim TmpInst.setOpcode(ARM::STR_PRE_IMM); 8068226633Sdim TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 8069226633Sdim TmpInst.addOperand(Inst.getOperand(4)); // Rt 8070226633Sdim TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 8071288943Sdim TmpInst.addOperand(MCOperand::createImm(-4)); 8072226633Sdim TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8073226633Sdim TmpInst.addOperand(Inst.getOperand(3)); 8074226633Sdim Inst = TmpInst; 8075226633Sdim } 8076226633Sdim break; 8077234353Sdim case ARM::t2ADDri12: 8078234353Sdim // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 8079234353Sdim // mnemonic was used (not "addw"), encoding T3 is preferred. 8080276479Sdim if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" || 8081234353Sdim ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 8082234353Sdim break; 8083234353Sdim Inst.setOpcode(ARM::t2ADDri); 8084288943Sdim Inst.addOperand(MCOperand::createReg(0)); // cc_out 8085234353Sdim break; 8086234353Sdim case ARM::t2SUBri12: 8087234353Sdim // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 8088234353Sdim // mnemonic was used (not "subw"), encoding T3 is preferred. 8089276479Sdim if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" || 8090234353Sdim ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 8091234353Sdim break; 8092234353Sdim Inst.setOpcode(ARM::t2SUBri); 8093288943Sdim Inst.addOperand(MCOperand::createReg(0)); // cc_out 8094234353Sdim break; 8095226633Sdim case ARM::tADDi8: 8096226633Sdim // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 8097226633Sdim // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 8098226633Sdim // to encoding T2 if <Rd> is specified and encoding T2 is preferred 8099226633Sdim // to encoding T1 if <Rd> is omitted." 8100234353Sdim if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 8101226633Sdim Inst.setOpcode(ARM::tADDi3); 8102234353Sdim return true; 8103234353Sdim } 8104226633Sdim break; 8105226633Sdim case ARM::tSUBi8: 8106226633Sdim // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 8107226633Sdim // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 8108226633Sdim // to encoding T2 if <Rd> is specified and encoding T2 is preferred 8109226633Sdim // to encoding T1 if <Rd> is omitted." 8110234353Sdim if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 8111226633Sdim Inst.setOpcode(ARM::tSUBi3); 8112234353Sdim return true; 8113234353Sdim } 8114226633Sdim break; 8115234353Sdim case ARM::t2ADDri: 8116234353Sdim case ARM::t2SUBri: { 8117234353Sdim // If the destination and first source operand are the same, and 8118234353Sdim // the flags are compatible with the current IT status, use encoding T2 8119234353Sdim // instead of T3. For compatibility with the system 'as'. Make sure the 8120234353Sdim // wide encoding wasn't explicit. 8121234353Sdim if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 8122234353Sdim !isARMLowRegister(Inst.getOperand(0).getReg()) || 8123234353Sdim (unsigned)Inst.getOperand(2).getImm() > 255 || 8124234353Sdim ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || 8125276479Sdim (inITBlock() && Inst.getOperand(5).getReg() != 0)) || 8126276479Sdim (static_cast<ARMOperand &>(*Operands[3]).isToken() && 8127276479Sdim static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) 8128234353Sdim break; 8129234353Sdim MCInst TmpInst; 8130234353Sdim TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 8131234353Sdim ARM::tADDi8 : ARM::tSUBi8); 8132234353Sdim TmpInst.addOperand(Inst.getOperand(0)); 8133234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 8134234353Sdim TmpInst.addOperand(Inst.getOperand(0)); 8135234353Sdim TmpInst.addOperand(Inst.getOperand(2)); 8136234353Sdim TmpInst.addOperand(Inst.getOperand(3)); 8137234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 8138234353Sdim Inst = TmpInst; 8139234353Sdim return true; 8140234353Sdim } 8141234353Sdim case ARM::t2ADDrr: { 8142234353Sdim // If the destination and first source operand are the same, and 8143234353Sdim // there's no setting of the flags, use encoding T2 instead of T3. 8144234353Sdim // Note that this is only for ADD, not SUB. This mirrors the system 8145288943Sdim // 'as' behaviour. Also take advantage of ADD being commutative. 8146288943Sdim // Make sure the wide encoding wasn't explicit. 8147288943Sdim bool Swap = false; 8148288943Sdim auto DestReg = Inst.getOperand(0).getReg(); 8149288943Sdim bool Transform = DestReg == Inst.getOperand(1).getReg(); 8150288943Sdim if (!Transform && DestReg == Inst.getOperand(2).getReg()) { 8151288943Sdim Transform = true; 8152288943Sdim Swap = true; 8153288943Sdim } 8154288943Sdim if (!Transform || 8155234353Sdim Inst.getOperand(5).getReg() != 0 || 8156276479Sdim (static_cast<ARMOperand &>(*Operands[3]).isToken() && 8157276479Sdim static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) 8158234353Sdim break; 8159234353Sdim MCInst TmpInst; 8160234353Sdim TmpInst.setOpcode(ARM::tADDhirr); 8161234353Sdim TmpInst.addOperand(Inst.getOperand(0)); 8162234353Sdim TmpInst.addOperand(Inst.getOperand(0)); 8163288943Sdim TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2)); 8164234353Sdim TmpInst.addOperand(Inst.getOperand(3)); 8165234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 8166234353Sdim Inst = TmpInst; 8167234353Sdim return true; 8168234353Sdim } 8169239462Sdim case ARM::tADDrSP: { 8170239462Sdim // If the non-SP source operand and the destination operand are not the 8171239462Sdim // same, we need to use the 32-bit encoding if it's available. 8172239462Sdim if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 8173239462Sdim Inst.setOpcode(ARM::t2ADDrr); 8174288943Sdim Inst.addOperand(MCOperand::createReg(0)); // cc_out 8175239462Sdim return true; 8176239462Sdim } 8177239462Sdim break; 8178239462Sdim } 8179226633Sdim case ARM::tB: 8180226633Sdim // A Thumb conditional branch outside of an IT block is a tBcc. 8181234353Sdim if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 8182226633Sdim Inst.setOpcode(ARM::tBcc); 8183234353Sdim return true; 8184234353Sdim } 8185226633Sdim break; 8186226633Sdim case ARM::t2B: 8187226633Sdim // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 8188234353Sdim if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 8189226633Sdim Inst.setOpcode(ARM::t2Bcc); 8190234353Sdim return true; 8191234353Sdim } 8192226633Sdim break; 8193226633Sdim case ARM::t2Bcc: 8194226633Sdim // If the conditional is AL or we're in an IT block, we really want t2B. 8195234353Sdim if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 8196226633Sdim Inst.setOpcode(ARM::t2B); 8197234353Sdim return true; 8198234353Sdim } 8199226633Sdim break; 8200226633Sdim case ARM::tBcc: 8201226633Sdim // If the conditional is AL, we really want tB. 8202234353Sdim if (Inst.getOperand(1).getImm() == ARMCC::AL) { 8203226633Sdim Inst.setOpcode(ARM::tB); 8204234353Sdim return true; 8205234353Sdim } 8206226633Sdim break; 8207226633Sdim case ARM::tLDMIA: { 8208226633Sdim // If the register list contains any high registers, or if the writeback 8209226633Sdim // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 8210226633Sdim // instead if we're in Thumb2. Otherwise, this should have generated 8211226633Sdim // an error in validateInstruction(). 8212226633Sdim unsigned Rn = Inst.getOperand(0).getReg(); 8213226633Sdim bool hasWritebackToken = 8214276479Sdim (static_cast<ARMOperand &>(*Operands[3]).isToken() && 8215276479Sdim static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); 8216226633Sdim bool listContainsBase; 8217226633Sdim if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 8218226633Sdim (!listContainsBase && !hasWritebackToken) || 8219226633Sdim (listContainsBase && hasWritebackToken)) { 8220226633Sdim // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 8221226633Sdim assert (isThumbTwo()); 8222226633Sdim Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 8223226633Sdim // If we're switching to the updating version, we need to insert 8224226633Sdim // the writeback tied operand. 8225226633Sdim if (hasWritebackToken) 8226226633Sdim Inst.insert(Inst.begin(), 8227288943Sdim MCOperand::createReg(Inst.getOperand(0).getReg())); 8228234353Sdim return true; 8229226633Sdim } 8230226633Sdim break; 8231226633Sdim } 8232226633Sdim case ARM::tSTMIA_UPD: { 8233226633Sdim // If the register list contains any high registers, we need to use 8234226633Sdim // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 8235226633Sdim // should have generated an error in validateInstruction(). 8236226633Sdim unsigned Rn = Inst.getOperand(0).getReg(); 8237226633Sdim bool listContainsBase; 8238226633Sdim if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 8239226633Sdim // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 8240226633Sdim assert (isThumbTwo()); 8241226633Sdim Inst.setOpcode(ARM::t2STMIA_UPD); 8242234353Sdim return true; 8243226633Sdim } 8244226633Sdim break; 8245226633Sdim } 8246234353Sdim case ARM::tPOP: { 8247234353Sdim bool listContainsBase; 8248234353Sdim // If the register list contains any high registers, we need to use 8249234353Sdim // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 8250234353Sdim // should have generated an error in validateInstruction(). 8251234353Sdim if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 8252234353Sdim return false; 8253234353Sdim assert (isThumbTwo()); 8254234353Sdim Inst.setOpcode(ARM::t2LDMIA_UPD); 8255234353Sdim // Add the base register and writeback operands. 8256288943Sdim Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 8257288943Sdim Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 8258234353Sdim return true; 8259234353Sdim } 8260234353Sdim case ARM::tPUSH: { 8261234353Sdim bool listContainsBase; 8262234353Sdim if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 8263234353Sdim return false; 8264234353Sdim assert (isThumbTwo()); 8265234353Sdim Inst.setOpcode(ARM::t2STMDB_UPD); 8266234353Sdim // Add the base register and writeback operands. 8267288943Sdim Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 8268288943Sdim Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 8269234353Sdim return true; 8270234353Sdim } 8271226633Sdim case ARM::t2MOVi: { 8272226633Sdim // If we can use the 16-bit encoding and the user didn't explicitly 8273226633Sdim // request the 32-bit variant, transform it here. 8274226633Sdim if (isARMLowRegister(Inst.getOperand(0).getReg()) && 8275234353Sdim (unsigned)Inst.getOperand(1).getImm() <= 255 && 8276226633Sdim ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 8277276479Sdim Inst.getOperand(4).getReg() == ARM::CPSR) || 8278276479Sdim (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 8279276479Sdim (!static_cast<ARMOperand &>(*Operands[2]).isToken() || 8280276479Sdim static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) { 8281226633Sdim // The operands aren't in the same order for tMOVi8... 8282226633Sdim MCInst TmpInst; 8283226633Sdim TmpInst.setOpcode(ARM::tMOVi8); 8284226633Sdim TmpInst.addOperand(Inst.getOperand(0)); 8285226633Sdim TmpInst.addOperand(Inst.getOperand(4)); 8286226633Sdim TmpInst.addOperand(Inst.getOperand(1)); 8287226633Sdim TmpInst.addOperand(Inst.getOperand(2)); 8288226633Sdim TmpInst.addOperand(Inst.getOperand(3)); 8289226633Sdim Inst = TmpInst; 8290234353Sdim return true; 8291226633Sdim } 8292226633Sdim break; 8293226633Sdim } 8294226633Sdim case ARM::t2MOVr: { 8295226633Sdim // If we can use the 16-bit encoding and the user didn't explicitly 8296226633Sdim // request the 32-bit variant, transform it here. 8297226633Sdim if (isARMLowRegister(Inst.getOperand(0).getReg()) && 8298226633Sdim isARMLowRegister(Inst.getOperand(1).getReg()) && 8299226633Sdim Inst.getOperand(2).getImm() == ARMCC::AL && 8300226633Sdim Inst.getOperand(4).getReg() == ARM::CPSR && 8301276479Sdim (!static_cast<ARMOperand &>(*Operands[2]).isToken() || 8302276479Sdim static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) { 8303226633Sdim // The operands aren't the same for tMOV[S]r... (no cc_out) 8304226633Sdim MCInst TmpInst; 8305226633Sdim TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 8306226633Sdim TmpInst.addOperand(Inst.getOperand(0)); 8307226633Sdim TmpInst.addOperand(Inst.getOperand(1)); 8308226633Sdim TmpInst.addOperand(Inst.getOperand(2)); 8309226633Sdim TmpInst.addOperand(Inst.getOperand(3)); 8310226633Sdim Inst = TmpInst; 8311234353Sdim return true; 8312226633Sdim } 8313226633Sdim break; 8314226633Sdim } 8315226633Sdim case ARM::t2SXTH: 8316226633Sdim case ARM::t2SXTB: 8317226633Sdim case ARM::t2UXTH: 8318226633Sdim case ARM::t2UXTB: { 8319226633Sdim // If we can use the 16-bit encoding and the user didn't explicitly 8320226633Sdim // request the 32-bit variant, transform it here. 8321226633Sdim if (isARMLowRegister(Inst.getOperand(0).getReg()) && 8322226633Sdim isARMLowRegister(Inst.getOperand(1).getReg()) && 8323226633Sdim Inst.getOperand(2).getImm() == 0 && 8324276479Sdim (!static_cast<ARMOperand &>(*Operands[2]).isToken() || 8325276479Sdim static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) { 8326226633Sdim unsigned NewOpc; 8327226633Sdim switch (Inst.getOpcode()) { 8328226633Sdim default: llvm_unreachable("Illegal opcode!"); 8329226633Sdim case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 8330226633Sdim case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 8331226633Sdim case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 8332226633Sdim case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 8333226633Sdim } 8334226633Sdim // The operands aren't the same for thumb1 (no rotate operand). 8335226633Sdim MCInst TmpInst; 8336226633Sdim TmpInst.setOpcode(NewOpc); 8337226633Sdim TmpInst.addOperand(Inst.getOperand(0)); 8338226633Sdim TmpInst.addOperand(Inst.getOperand(1)); 8339226633Sdim TmpInst.addOperand(Inst.getOperand(3)); 8340226633Sdim TmpInst.addOperand(Inst.getOperand(4)); 8341226633Sdim Inst = TmpInst; 8342234353Sdim return true; 8343226633Sdim } 8344226633Sdim break; 8345226633Sdim } 8346234353Sdim case ARM::MOVsi: { 8347234353Sdim ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 8348239462Sdim // rrx shifts and asr/lsr of #32 is encoded as 0 8349239462Sdim if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 8350239462Sdim return false; 8351234353Sdim if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 8352234353Sdim // Shifting by zero is accepted as a vanilla 'MOVr' 8353234353Sdim MCInst TmpInst; 8354234353Sdim TmpInst.setOpcode(ARM::MOVr); 8355234353Sdim TmpInst.addOperand(Inst.getOperand(0)); 8356234353Sdim TmpInst.addOperand(Inst.getOperand(1)); 8357234353Sdim TmpInst.addOperand(Inst.getOperand(3)); 8358234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 8359234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 8360234353Sdim Inst = TmpInst; 8361234353Sdim return true; 8362234353Sdim } 8363234353Sdim return false; 8364234353Sdim } 8365234353Sdim case ARM::ANDrsi: 8366234353Sdim case ARM::ORRrsi: 8367234353Sdim case ARM::EORrsi: 8368234353Sdim case ARM::BICrsi: 8369234353Sdim case ARM::SUBrsi: 8370234353Sdim case ARM::ADDrsi: { 8371234353Sdim unsigned newOpc; 8372234353Sdim ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 8373234353Sdim if (SOpc == ARM_AM::rrx) return false; 8374234353Sdim switch (Inst.getOpcode()) { 8375234353Sdim default: llvm_unreachable("unexpected opcode!"); 8376234353Sdim case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 8377234353Sdim case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 8378234353Sdim case ARM::EORrsi: newOpc = ARM::EORrr; break; 8379234353Sdim case ARM::BICrsi: newOpc = ARM::BICrr; break; 8380234353Sdim case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 8381234353Sdim case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 8382234353Sdim } 8383234353Sdim // If the shift is by zero, use the non-shifted instruction definition. 8384239462Sdim // The exception is for right shifts, where 0 == 32 8385239462Sdim if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 8386239462Sdim !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { 8387234353Sdim MCInst TmpInst; 8388234353Sdim TmpInst.setOpcode(newOpc); 8389234353Sdim TmpInst.addOperand(Inst.getOperand(0)); 8390234353Sdim TmpInst.addOperand(Inst.getOperand(1)); 8391234353Sdim TmpInst.addOperand(Inst.getOperand(2)); 8392234353Sdim TmpInst.addOperand(Inst.getOperand(4)); 8393234353Sdim TmpInst.addOperand(Inst.getOperand(5)); 8394234353Sdim TmpInst.addOperand(Inst.getOperand(6)); 8395234353Sdim Inst = TmpInst; 8396234353Sdim return true; 8397234353Sdim } 8398234353Sdim return false; 8399234353Sdim } 8400234353Sdim case ARM::ITasm: 8401226633Sdim case ARM::t2IT: { 8402226633Sdim // The mask bits for all but the first condition are represented as 8403226633Sdim // the low bit of the condition code value implies 't'. We currently 8404226633Sdim // always have 1 implies 't', so XOR toggle the bits if the low bit 8405239462Sdim // of the condition code is zero. 8406226633Sdim MCOperand &MO = Inst.getOperand(1); 8407226633Sdim unsigned Mask = MO.getImm(); 8408226633Sdim unsigned OrigMask = Mask; 8409261991Sdim unsigned TZ = countTrailingZeros(Mask); 8410226633Sdim if ((Inst.getOperand(0).getImm() & 1) == 0) { 8411226633Sdim assert(Mask && TZ <= 3 && "illegal IT mask value!"); 8412261991Sdim Mask ^= (0xE << TZ) & 0xF; 8413239462Sdim } 8414226633Sdim MO.setImm(Mask); 8415226633Sdim 8416226633Sdim // Set up the IT block state according to the IT instruction we just 8417226633Sdim // matched. 8418226633Sdim assert(!inITBlock() && "nested IT blocks?!"); 8419226633Sdim ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 8420226633Sdim ITState.Mask = OrigMask; // Use the original mask, not the updated one. 8421226633Sdim ITState.CurPosition = 0; 8422226633Sdim ITState.FirstCond = true; 8423226633Sdim break; 8424226633Sdim } 8425239462Sdim case ARM::t2LSLrr: 8426239462Sdim case ARM::t2LSRrr: 8427239462Sdim case ARM::t2ASRrr: 8428239462Sdim case ARM::t2SBCrr: 8429239462Sdim case ARM::t2RORrr: 8430239462Sdim case ARM::t2BICrr: 8431239462Sdim { 8432239462Sdim // Assemblers should use the narrow encodings of these instructions when permissible. 8433239462Sdim if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 8434239462Sdim isARMLowRegister(Inst.getOperand(2).getReg())) && 8435239462Sdim Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 8436239462Sdim ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 8437276479Sdim (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 8438276479Sdim (!static_cast<ARMOperand &>(*Operands[3]).isToken() || 8439276479Sdim !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower( 8440276479Sdim ".w"))) { 8441239462Sdim unsigned NewOpc; 8442239462Sdim switch (Inst.getOpcode()) { 8443239462Sdim default: llvm_unreachable("unexpected opcode"); 8444239462Sdim case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; 8445239462Sdim case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; 8446239462Sdim case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; 8447239462Sdim case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; 8448239462Sdim case ARM::t2RORrr: NewOpc = ARM::tROR; break; 8449239462Sdim case ARM::t2BICrr: NewOpc = ARM::tBIC; break; 8450239462Sdim } 8451239462Sdim MCInst TmpInst; 8452239462Sdim TmpInst.setOpcode(NewOpc); 8453239462Sdim TmpInst.addOperand(Inst.getOperand(0)); 8454239462Sdim TmpInst.addOperand(Inst.getOperand(5)); 8455239462Sdim TmpInst.addOperand(Inst.getOperand(1)); 8456239462Sdim TmpInst.addOperand(Inst.getOperand(2)); 8457239462Sdim TmpInst.addOperand(Inst.getOperand(3)); 8458239462Sdim TmpInst.addOperand(Inst.getOperand(4)); 8459239462Sdim Inst = TmpInst; 8460239462Sdim return true; 8461239462Sdim } 8462239462Sdim return false; 8463226633Sdim } 8464239462Sdim case ARM::t2ANDrr: 8465239462Sdim case ARM::t2EORrr: 8466239462Sdim case ARM::t2ADCrr: 8467239462Sdim case ARM::t2ORRrr: 8468239462Sdim { 8469239462Sdim // Assemblers should use the narrow encodings of these instructions when permissible. 8470239462Sdim // These instructions are special in that they are commutable, so shorter encodings 8471239462Sdim // are available more often. 8472239462Sdim if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 8473239462Sdim isARMLowRegister(Inst.getOperand(2).getReg())) && 8474239462Sdim (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 8475239462Sdim Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 8476239462Sdim ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 8477276479Sdim (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 8478276479Sdim (!static_cast<ARMOperand &>(*Operands[3]).isToken() || 8479276479Sdim !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower( 8480276479Sdim ".w"))) { 8481239462Sdim unsigned NewOpc; 8482239462Sdim switch (Inst.getOpcode()) { 8483239462Sdim default: llvm_unreachable("unexpected opcode"); 8484239462Sdim case ARM::t2ADCrr: NewOpc = ARM::tADC; break; 8485239462Sdim case ARM::t2ANDrr: NewOpc = ARM::tAND; break; 8486239462Sdim case ARM::t2EORrr: NewOpc = ARM::tEOR; break; 8487239462Sdim case ARM::t2ORRrr: NewOpc = ARM::tORR; break; 8488239462Sdim } 8489239462Sdim MCInst TmpInst; 8490239462Sdim TmpInst.setOpcode(NewOpc); 8491239462Sdim TmpInst.addOperand(Inst.getOperand(0)); 8492239462Sdim TmpInst.addOperand(Inst.getOperand(5)); 8493239462Sdim if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 8494239462Sdim TmpInst.addOperand(Inst.getOperand(1)); 8495239462Sdim TmpInst.addOperand(Inst.getOperand(2)); 8496239462Sdim } else { 8497239462Sdim TmpInst.addOperand(Inst.getOperand(2)); 8498239462Sdim TmpInst.addOperand(Inst.getOperand(1)); 8499239462Sdim } 8500239462Sdim TmpInst.addOperand(Inst.getOperand(3)); 8501239462Sdim TmpInst.addOperand(Inst.getOperand(4)); 8502239462Sdim Inst = TmpInst; 8503239462Sdim return true; 8504239462Sdim } 8505239462Sdim return false; 8506239462Sdim } 8507239462Sdim } 8508234353Sdim return false; 8509226633Sdim} 8510226633Sdim 8511226633Sdimunsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 8512226633Sdim // 16-bit thumb arithmetic instructions either require or preclude the 'S' 8513226633Sdim // suffix depending on whether they're in an IT block or not. 8514226633Sdim unsigned Opc = Inst.getOpcode(); 8515261991Sdim const MCInstrDesc &MCID = MII.get(Opc); 8516226633Sdim if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 8517226633Sdim assert(MCID.hasOptionalDef() && 8518226633Sdim "optionally flag setting instruction missing optional def operand"); 8519226633Sdim assert(MCID.NumOperands == Inst.getNumOperands() && 8520226633Sdim "operand count mismatch!"); 8521226633Sdim // Find the optional-def operand (cc_out). 8522226633Sdim unsigned OpNo; 8523226633Sdim for (OpNo = 0; 8524226633Sdim !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 8525226633Sdim ++OpNo) 8526226633Sdim ; 8527226633Sdim // If we're parsing Thumb1, reject it completely. 8528226633Sdim if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 8529226633Sdim return Match_MnemonicFail; 8530226633Sdim // If we're parsing Thumb2, which form is legal depends on whether we're 8531226633Sdim // in an IT block. 8532226633Sdim if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 8533226633Sdim !inITBlock()) 8534226633Sdim return Match_RequiresITBlock; 8535226633Sdim if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 8536226633Sdim inITBlock()) 8537226633Sdim return Match_RequiresNotITBlock; 8538296417Sdim } else if (isThumbOne()) { 8539296417Sdim // Some high-register supporting Thumb1 encodings only allow both registers 8540296417Sdim // to be from r0-r7 when in Thumb2. 8541296417Sdim if (Opc == ARM::tADDhirr && !hasV6MOps() && 8542296417Sdim isARMLowRegister(Inst.getOperand(1).getReg()) && 8543296417Sdim isARMLowRegister(Inst.getOperand(2).getReg())) 8544296417Sdim return Match_RequiresThumb2; 8545296417Sdim // Others only require ARMv6 or later. 8546296417Sdim else if (Opc == ARM::tMOVr && !hasV6Ops() && 8547296417Sdim isARMLowRegister(Inst.getOperand(0).getReg()) && 8548296417Sdim isARMLowRegister(Inst.getOperand(1).getReg())) 8549296417Sdim return Match_RequiresV6; 8550226633Sdim } 8551296417Sdim 8552296417Sdim for (unsigned I = 0; I < MCID.NumOperands; ++I) 8553296417Sdim if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) { 8554296417Sdim // rGPRRegClass excludes PC, and also excluded SP before ARMv8 8555296417Sdim if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops()) 8556296417Sdim return Match_RequiresV8; 8557296417Sdim else if (Inst.getOperand(I).getReg() == ARM::PC) 8558296417Sdim return Match_InvalidOperand; 8559296417Sdim } 8560296417Sdim 8561226633Sdim return Match_Success; 8562226633Sdim} 8563226633Sdim 8564276479Sdimnamespace llvm { 8565276479Sdimtemplate <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) { 8566276479Sdim return true; // In an assembly source, no need to second-guess 8567276479Sdim} 8568276479Sdim} 8569276479Sdim 8570280031Sdimstatic const char *getSubtargetFeatureName(uint64_t Val); 8571276479Sdimbool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 8572276479Sdim OperandVector &Operands, 8573280031Sdim MCStreamer &Out, uint64_t &ErrorInfo, 8574276479Sdim bool MatchingInlineAsm) { 8575218893Sdim MCInst Inst; 8576226633Sdim unsigned MatchResult; 8577249423Sdim 8578243830Sdim MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, 8579243830Sdim MatchingInlineAsm); 8580218893Sdim switch (MatchResult) { 8581218893Sdim case Match_Success: 8582226633Sdim // Context sensitive operand constraints aren't handled by the matcher, 8583226633Sdim // so check them here. 8584226633Sdim if (validateInstruction(Inst, Operands)) { 8585226633Sdim // Still progress the IT block, otherwise one wrong condition causes 8586226633Sdim // nasty cascading errors. 8587226633Sdim forwardITPosition(); 8588226633Sdim return true; 8589226633Sdim } 8590226633Sdim 8591261991Sdim { // processInstruction() updates inITBlock state, we need to save it away 8592261991Sdim bool wasInITBlock = inITBlock(); 8593226633Sdim 8594261991Sdim // Some instructions need post-processing to, for example, tweak which 8595261991Sdim // encoding is selected. Loop on it while changes happen so the 8596261991Sdim // individual transformations can chain off each other. E.g., 8597261991Sdim // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 8598276537Sdim while (processInstruction(Inst, Operands, Out)) 8599261991Sdim ; 8600261991Sdim 8601261991Sdim // Only after the instruction is fully processed, we can validate it 8602261991Sdim if (wasInITBlock && hasV8Ops() && isThumb() && 8603276479Sdim !isV8EligibleForIT(&Inst)) { 8604261991Sdim Warning(IDLoc, "deprecated instruction in IT block"); 8605261991Sdim } 8606261991Sdim } 8607261991Sdim 8608226633Sdim // Only move forward at the very end so that everything in validate 8609226633Sdim // and process gets a consistent answer about whether we're in an IT 8610226633Sdim // block. 8611226633Sdim forwardITPosition(); 8612226633Sdim 8613234353Sdim // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 8614234353Sdim // doesn't actually encode. 8615234353Sdim if (Inst.getOpcode() == ARM::ITasm) 8616234353Sdim return false; 8617234353Sdim 8618234353Sdim Inst.setLoc(IDLoc); 8619296417Sdim Out.EmitInstruction(Inst, getSTI()); 8620218893Sdim return false; 8621239462Sdim case Match_MissingFeature: { 8622239462Sdim assert(ErrorInfo && "Unknown missing feature!"); 8623239462Sdim // Special case the error message for the very common case where only 8624239462Sdim // a single subtarget feature is missing (Thumb vs. ARM, e.g.). 8625239462Sdim std::string Msg = "instruction requires:"; 8626280031Sdim uint64_t Mask = 1; 8627239462Sdim for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { 8628239462Sdim if (ErrorInfo & Mask) { 8629239462Sdim Msg += " "; 8630239462Sdim Msg += getSubtargetFeatureName(ErrorInfo & Mask); 8631239462Sdim } 8632239462Sdim Mask <<= 1; 8633239462Sdim } 8634239462Sdim return Error(IDLoc, Msg); 8635239462Sdim } 8636218893Sdim case Match_InvalidOperand: { 8637218893Sdim SMLoc ErrorLoc = IDLoc; 8638280031Sdim if (ErrorInfo != ~0ULL) { 8639218893Sdim if (ErrorInfo >= Operands.size()) 8640218893Sdim return Error(IDLoc, "too few operands for instruction"); 8641218893Sdim 8642276479Sdim ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); 8643218893Sdim if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 8644218893Sdim } 8645218893Sdim 8646218893Sdim return Error(ErrorLoc, "invalid operand for instruction"); 8647218893Sdim } 8648218893Sdim case Match_MnemonicFail: 8649234982Sdim return Error(IDLoc, "invalid instruction", 8650276479Sdim ((ARMOperand &)*Operands[0]).getLocRange()); 8651226633Sdim case Match_RequiresNotITBlock: 8652226633Sdim return Error(IDLoc, "flag setting instruction only valid outside IT block"); 8653226633Sdim case Match_RequiresITBlock: 8654226633Sdim return Error(IDLoc, "instruction only valid inside IT block"); 8655226633Sdim case Match_RequiresV6: 8656226633Sdim return Error(IDLoc, "instruction variant requires ARMv6 or later"); 8657226633Sdim case Match_RequiresThumb2: 8658226633Sdim return Error(IDLoc, "instruction variant requires Thumb2"); 8659296417Sdim case Match_RequiresV8: 8660296417Sdim return Error(IDLoc, "instruction variant requires ARMv8 or later"); 8661261991Sdim case Match_ImmRange0_15: { 8662276479Sdim SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); 8663251662Sdim if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 8664261991Sdim return Error(ErrorLoc, "immediate operand must be in the range [0,15]"); 8665251662Sdim } 8666261991Sdim case Match_ImmRange0_239: { 8667276479Sdim SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); 8668239462Sdim if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 8669261991Sdim return Error(ErrorLoc, "immediate operand must be in the range [0,239]"); 8670218893Sdim } 8671276479Sdim case Match_AlignedMemoryRequiresNone: 8672276479Sdim case Match_DupAlignedMemoryRequiresNone: 8673276479Sdim case Match_AlignedMemoryRequires16: 8674276479Sdim case Match_DupAlignedMemoryRequires16: 8675276479Sdim case Match_AlignedMemoryRequires32: 8676276479Sdim case Match_DupAlignedMemoryRequires32: 8677276479Sdim case Match_AlignedMemoryRequires64: 8678276479Sdim case Match_DupAlignedMemoryRequires64: 8679276479Sdim case Match_AlignedMemoryRequires64or128: 8680276479Sdim case Match_DupAlignedMemoryRequires64or128: 8681276479Sdim case Match_AlignedMemoryRequires64or128or256: 8682276479Sdim { 8683276479Sdim SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc(); 8684276479Sdim if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 8685276479Sdim switch (MatchResult) { 8686276479Sdim default: 8687276479Sdim llvm_unreachable("Missing Match_Aligned type"); 8688276479Sdim case Match_AlignedMemoryRequiresNone: 8689276479Sdim case Match_DupAlignedMemoryRequiresNone: 8690276479Sdim return Error(ErrorLoc, "alignment must be omitted"); 8691276479Sdim case Match_AlignedMemoryRequires16: 8692276479Sdim case Match_DupAlignedMemoryRequires16: 8693276479Sdim return Error(ErrorLoc, "alignment must be 16 or omitted"); 8694276479Sdim case Match_AlignedMemoryRequires32: 8695276479Sdim case Match_DupAlignedMemoryRequires32: 8696276479Sdim return Error(ErrorLoc, "alignment must be 32 or omitted"); 8697276479Sdim case Match_AlignedMemoryRequires64: 8698276479Sdim case Match_DupAlignedMemoryRequires64: 8699276479Sdim return Error(ErrorLoc, "alignment must be 64 or omitted"); 8700276479Sdim case Match_AlignedMemoryRequires64or128: 8701276479Sdim case Match_DupAlignedMemoryRequires64or128: 8702276479Sdim return Error(ErrorLoc, "alignment must be 64, 128 or omitted"); 8703276479Sdim case Match_AlignedMemoryRequires64or128or256: 8704276479Sdim return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted"); 8705276479Sdim } 8706239462Sdim } 8707276479Sdim } 8708218893Sdim 8709218893Sdim llvm_unreachable("Implement any new match types added!"); 8710218893Sdim} 8711218893Sdim 8712226633Sdim/// parseDirective parses the arm specific directives 8713198090Srdivackybool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 8714276479Sdim const MCObjectFileInfo::Environment Format = 8715276479Sdim getContext().getObjectFileInfo()->getObjectFileType(); 8716276479Sdim bool IsMachO = Format == MCObjectFileInfo::IsMachO; 8717280031Sdim bool IsCOFF = Format == MCObjectFileInfo::IsCOFF; 8718276479Sdim 8719198090Srdivacky StringRef IDVal = DirectiveID.getIdentifier(); 8720198090Srdivacky if (IDVal == ".word") 8721276479Sdim return parseLiteralValues(4, DirectiveID.getLoc()); 8722276479Sdim else if (IDVal == ".short" || IDVal == ".hword") 8723276479Sdim return parseLiteralValues(2, DirectiveID.getLoc()); 8724198396Srdivacky else if (IDVal == ".thumb") 8725226633Sdim return parseDirectiveThumb(DirectiveID.getLoc()); 8726234353Sdim else if (IDVal == ".arm") 8727234353Sdim return parseDirectiveARM(DirectiveID.getLoc()); 8728198396Srdivacky else if (IDVal == ".thumb_func") 8729226633Sdim return parseDirectiveThumbFunc(DirectiveID.getLoc()); 8730198396Srdivacky else if (IDVal == ".code") 8731226633Sdim return parseDirectiveCode(DirectiveID.getLoc()); 8732198396Srdivacky else if (IDVal == ".syntax") 8733226633Sdim return parseDirectiveSyntax(DirectiveID.getLoc()); 8734234353Sdim else if (IDVal == ".unreq") 8735234353Sdim return parseDirectiveUnreq(DirectiveID.getLoc()); 8736261991Sdim else if (IDVal == ".fnend") 8737261991Sdim return parseDirectiveFnEnd(DirectiveID.getLoc()); 8738261991Sdim else if (IDVal == ".cantunwind") 8739261991Sdim return parseDirectiveCantUnwind(DirectiveID.getLoc()); 8740261991Sdim else if (IDVal == ".personality") 8741261991Sdim return parseDirectivePersonality(DirectiveID.getLoc()); 8742261991Sdim else if (IDVal == ".handlerdata") 8743261991Sdim return parseDirectiveHandlerData(DirectiveID.getLoc()); 8744261991Sdim else if (IDVal == ".setfp") 8745261991Sdim return parseDirectiveSetFP(DirectiveID.getLoc()); 8746261991Sdim else if (IDVal == ".pad") 8747261991Sdim return parseDirectivePad(DirectiveID.getLoc()); 8748261991Sdim else if (IDVal == ".save") 8749261991Sdim return parseDirectiveRegSave(DirectiveID.getLoc(), false); 8750261991Sdim else if (IDVal == ".vsave") 8751261991Sdim return parseDirectiveRegSave(DirectiveID.getLoc(), true); 8752276479Sdim else if (IDVal == ".ltorg" || IDVal == ".pool") 8753276479Sdim return parseDirectiveLtorg(DirectiveID.getLoc()); 8754276479Sdim else if (IDVal == ".even") 8755276479Sdim return parseDirectiveEven(DirectiveID.getLoc()); 8756276479Sdim else if (IDVal == ".personalityindex") 8757276479Sdim return parseDirectivePersonalityIndex(DirectiveID.getLoc()); 8758276479Sdim else if (IDVal == ".unwind_raw") 8759276479Sdim return parseDirectiveUnwindRaw(DirectiveID.getLoc()); 8760276479Sdim else if (IDVal == ".movsp") 8761276479Sdim return parseDirectiveMovSP(DirectiveID.getLoc()); 8762276479Sdim else if (IDVal == ".arch_extension") 8763276479Sdim return parseDirectiveArchExtension(DirectiveID.getLoc()); 8764276479Sdim else if (IDVal == ".align") 8765276479Sdim return parseDirectiveAlign(DirectiveID.getLoc()); 8766276479Sdim else if (IDVal == ".thumb_set") 8767276479Sdim return parseDirectiveThumbSet(DirectiveID.getLoc()); 8768276479Sdim 8769280031Sdim if (!IsMachO && !IsCOFF) { 8770276479Sdim if (IDVal == ".arch") 8771276479Sdim return parseDirectiveArch(DirectiveID.getLoc()); 8772276479Sdim else if (IDVal == ".cpu") 8773276479Sdim return parseDirectiveCPU(DirectiveID.getLoc()); 8774276479Sdim else if (IDVal == ".eabi_attribute") 8775276479Sdim return parseDirectiveEabiAttr(DirectiveID.getLoc()); 8776276479Sdim else if (IDVal == ".fpu") 8777276479Sdim return parseDirectiveFPU(DirectiveID.getLoc()); 8778276479Sdim else if (IDVal == ".fnstart") 8779276479Sdim return parseDirectiveFnStart(DirectiveID.getLoc()); 8780276479Sdim else if (IDVal == ".inst") 8781276479Sdim return parseDirectiveInst(DirectiveID.getLoc()); 8782276479Sdim else if (IDVal == ".inst.n") 8783276479Sdim return parseDirectiveInst(DirectiveID.getLoc(), 'n'); 8784276479Sdim else if (IDVal == ".inst.w") 8785276479Sdim return parseDirectiveInst(DirectiveID.getLoc(), 'w'); 8786276479Sdim else if (IDVal == ".object_arch") 8787276479Sdim return parseDirectiveObjectArch(DirectiveID.getLoc()); 8788276479Sdim else if (IDVal == ".tlsdescseq") 8789276479Sdim return parseDirectiveTLSDescSeq(DirectiveID.getLoc()); 8790276479Sdim } 8791276479Sdim 8792198090Srdivacky return true; 8793198090Srdivacky} 8794198090Srdivacky 8795276479Sdim/// parseLiteralValues 8796276479Sdim/// ::= .hword expression [, expression]* 8797276479Sdim/// ::= .short expression [, expression]* 8798276479Sdim/// ::= .word expression [, expression]* 8799276479Sdimbool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) { 8800280031Sdim MCAsmParser &Parser = getParser(); 8801198090Srdivacky if (getLexer().isNot(AsmToken::EndOfStatement)) { 8802198090Srdivacky for (;;) { 8803198090Srdivacky const MCExpr *Value; 8804276479Sdim if (getParser().parseExpression(Value)) { 8805276479Sdim Parser.eatToEndOfStatement(); 8806276479Sdim return false; 8807276479Sdim } 8808198090Srdivacky 8809296417Sdim getParser().getStreamer().EmitValue(Value, Size, L); 8810198090Srdivacky 8811198090Srdivacky if (getLexer().is(AsmToken::EndOfStatement)) 8812198090Srdivacky break; 8813218893Sdim 8814198090Srdivacky // FIXME: Improve diagnostic. 8815276479Sdim if (getLexer().isNot(AsmToken::Comma)) { 8816276479Sdim Error(L, "unexpected token in directive"); 8817276479Sdim return false; 8818276479Sdim } 8819202878Srdivacky Parser.Lex(); 8820198090Srdivacky } 8821198090Srdivacky } 8822198090Srdivacky 8823202878Srdivacky Parser.Lex(); 8824198090Srdivacky return false; 8825198090Srdivacky} 8826198090Srdivacky 8827226633Sdim/// parseDirectiveThumb 8828198396Srdivacky/// ::= .thumb 8829226633Sdimbool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 8830280031Sdim MCAsmParser &Parser = getParser(); 8831276479Sdim if (getLexer().isNot(AsmToken::EndOfStatement)) { 8832276479Sdim Error(L, "unexpected token in directive"); 8833276479Sdim return false; 8834276479Sdim } 8835202878Srdivacky Parser.Lex(); 8836198396Srdivacky 8837276479Sdim if (!hasThumb()) { 8838276479Sdim Error(L, "target does not support Thumb mode"); 8839276479Sdim return false; 8840276479Sdim } 8841261991Sdim 8842234353Sdim if (!isThumb()) 8843234353Sdim SwitchMode(); 8844276479Sdim 8845234353Sdim getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 8846198396Srdivacky return false; 8847198396Srdivacky} 8848198396Srdivacky 8849234353Sdim/// parseDirectiveARM 8850234353Sdim/// ::= .arm 8851234353Sdimbool ARMAsmParser::parseDirectiveARM(SMLoc L) { 8852280031Sdim MCAsmParser &Parser = getParser(); 8853276479Sdim if (getLexer().isNot(AsmToken::EndOfStatement)) { 8854276479Sdim Error(L, "unexpected token in directive"); 8855276479Sdim return false; 8856276479Sdim } 8857234353Sdim Parser.Lex(); 8858234353Sdim 8859276479Sdim if (!hasARM()) { 8860276479Sdim Error(L, "target does not support ARM mode"); 8861276479Sdim return false; 8862276479Sdim } 8863261991Sdim 8864234353Sdim if (isThumb()) 8865234353Sdim SwitchMode(); 8866276479Sdim 8867234353Sdim getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 8868234353Sdim return false; 8869234353Sdim} 8870234353Sdim 8871261991Sdimvoid ARMAsmParser::onLabelParsed(MCSymbol *Symbol) { 8872261991Sdim if (NextSymbolIsThumb) { 8873261991Sdim getParser().getStreamer().EmitThumbFunc(Symbol); 8874261991Sdim NextSymbolIsThumb = false; 8875261991Sdim } 8876261991Sdim} 8877261991Sdim 8878226633Sdim/// parseDirectiveThumbFunc 8879198396Srdivacky/// ::= .thumbfunc symbol_name 8880226633Sdimbool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 8881280031Sdim MCAsmParser &Parser = getParser(); 8882280031Sdim const auto Format = getContext().getObjectFileInfo()->getObjectFileType(); 8883280031Sdim bool IsMachO = Format == MCObjectFileInfo::IsMachO; 8884223017Sdim 8885234353Sdim // Darwin asm has (optionally) function name after .thumb_func direction 8886223017Sdim // ELF doesn't 8887280031Sdim if (IsMachO) { 8888223017Sdim const AsmToken &Tok = Parser.getTok(); 8889234353Sdim if (Tok.isNot(AsmToken::EndOfStatement)) { 8890276479Sdim if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) { 8891276479Sdim Error(L, "unexpected token in .thumb_func directive"); 8892276479Sdim return false; 8893276479Sdim } 8894276479Sdim 8895261991Sdim MCSymbol *Func = 8896288943Sdim getParser().getContext().getOrCreateSymbol(Tok.getIdentifier()); 8897261991Sdim getParser().getStreamer().EmitThumbFunc(Func); 8898234353Sdim Parser.Lex(); // Consume the identifier token. 8899261991Sdim return false; 8900234353Sdim } 8901223017Sdim } 8902223017Sdim 8903276479Sdim if (getLexer().isNot(AsmToken::EndOfStatement)) { 8904280031Sdim Error(Parser.getTok().getLoc(), "unexpected token in directive"); 8905280031Sdim Parser.eatToEndOfStatement(); 8906276479Sdim return false; 8907276479Sdim } 8908198396Srdivacky 8909261991Sdim NextSymbolIsThumb = true; 8910198396Srdivacky return false; 8911198396Srdivacky} 8912198396Srdivacky 8913226633Sdim/// parseDirectiveSyntax 8914198396Srdivacky/// ::= .syntax unified | divided 8915226633Sdimbool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 8916280031Sdim MCAsmParser &Parser = getParser(); 8917202878Srdivacky const AsmToken &Tok = Parser.getTok(); 8918276479Sdim if (Tok.isNot(AsmToken::Identifier)) { 8919276479Sdim Error(L, "unexpected token in .syntax directive"); 8920276479Sdim return false; 8921276479Sdim } 8922276479Sdim 8923210299Sed StringRef Mode = Tok.getString(); 8924276479Sdim if (Mode == "unified" || Mode == "UNIFIED") { 8925202878Srdivacky Parser.Lex(); 8926276479Sdim } else if (Mode == "divided" || Mode == "DIVIDED") { 8927276479Sdim Error(L, "'.syntax divided' arm asssembly not supported"); 8928276479Sdim return false; 8929276479Sdim } else { 8930276479Sdim Error(L, "unrecognized syntax mode in .syntax directive"); 8931276479Sdim return false; 8932276479Sdim } 8933198396Srdivacky 8934276479Sdim if (getLexer().isNot(AsmToken::EndOfStatement)) { 8935276479Sdim Error(Parser.getTok().getLoc(), "unexpected token in directive"); 8936276479Sdim return false; 8937276479Sdim } 8938202878Srdivacky Parser.Lex(); 8939198396Srdivacky 8940198396Srdivacky // TODO tell the MC streamer the mode 8941198396Srdivacky // getParser().getStreamer().Emit???(); 8942198396Srdivacky return false; 8943198396Srdivacky} 8944198396Srdivacky 8945226633Sdim/// parseDirectiveCode 8946198396Srdivacky/// ::= .code 16 | 32 8947226633Sdimbool ARMAsmParser::parseDirectiveCode(SMLoc L) { 8948280031Sdim MCAsmParser &Parser = getParser(); 8949202878Srdivacky const AsmToken &Tok = Parser.getTok(); 8950276479Sdim if (Tok.isNot(AsmToken::Integer)) { 8951276479Sdim Error(L, "unexpected token in .code directive"); 8952276479Sdim return false; 8953276479Sdim } 8954202878Srdivacky int64_t Val = Parser.getTok().getIntVal(); 8955276479Sdim if (Val != 16 && Val != 32) { 8956276479Sdim Error(L, "invalid operand to .code directive"); 8957276479Sdim return false; 8958276479Sdim } 8959276479Sdim Parser.Lex(); 8960198396Srdivacky 8961276479Sdim if (getLexer().isNot(AsmToken::EndOfStatement)) { 8962276479Sdim Error(Parser.getTok().getLoc(), "unexpected token in directive"); 8963276479Sdim return false; 8964276479Sdim } 8965202878Srdivacky Parser.Lex(); 8966198396Srdivacky 8967224145Sdim if (Val == 16) { 8968276479Sdim if (!hasThumb()) { 8969276479Sdim Error(L, "target does not support Thumb mode"); 8970276479Sdim return false; 8971276479Sdim } 8972261991Sdim 8973224145Sdim if (!isThumb()) 8974224145Sdim SwitchMode(); 8975218893Sdim getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 8976224145Sdim } else { 8977276479Sdim if (!hasARM()) { 8978276479Sdim Error(L, "target does not support ARM mode"); 8979276479Sdim return false; 8980276479Sdim } 8981261991Sdim 8982224145Sdim if (isThumb()) 8983224145Sdim SwitchMode(); 8984224145Sdim getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 8985218893Sdim } 8986218893Sdim 8987198396Srdivacky return false; 8988198396Srdivacky} 8989198396Srdivacky 8990234353Sdim/// parseDirectiveReq 8991234353Sdim/// ::= name .req registername 8992234353Sdimbool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 8993280031Sdim MCAsmParser &Parser = getParser(); 8994234353Sdim Parser.Lex(); // Eat the '.req' token. 8995234353Sdim unsigned Reg; 8996234353Sdim SMLoc SRegLoc, ERegLoc; 8997234353Sdim if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 8998249423Sdim Parser.eatToEndOfStatement(); 8999276479Sdim Error(SRegLoc, "register name expected"); 9000276479Sdim return false; 9001234353Sdim } 9002234353Sdim 9003234353Sdim // Shouldn't be anything else. 9004234353Sdim if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 9005249423Sdim Parser.eatToEndOfStatement(); 9006276479Sdim Error(Parser.getTok().getLoc(), "unexpected input in .req directive."); 9007276479Sdim return false; 9008234353Sdim } 9009234353Sdim 9010234353Sdim Parser.Lex(); // Consume the EndOfStatement 9011234353Sdim 9012288943Sdim if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg) { 9013276479Sdim Error(SRegLoc, "redefinition of '" + Name + "' does not match original."); 9014276479Sdim return false; 9015276479Sdim } 9016234353Sdim 9017234353Sdim return false; 9018234353Sdim} 9019234353Sdim 9020234353Sdim/// parseDirectiveUneq 9021234353Sdim/// ::= .unreq registername 9022234353Sdimbool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 9023280031Sdim MCAsmParser &Parser = getParser(); 9024234353Sdim if (Parser.getTok().isNot(AsmToken::Identifier)) { 9025249423Sdim Parser.eatToEndOfStatement(); 9026276479Sdim Error(L, "unexpected input in .unreq directive."); 9027276479Sdim return false; 9028234353Sdim } 9029276479Sdim RegisterReqs.erase(Parser.getTok().getIdentifier().lower()); 9030234353Sdim Parser.Lex(); // Eat the identifier. 9031234353Sdim return false; 9032234353Sdim} 9033234353Sdim 9034234353Sdim/// parseDirectiveArch 9035234353Sdim/// ::= .arch token 9036234353Sdimbool ARMAsmParser::parseDirectiveArch(SMLoc L) { 9037276479Sdim StringRef Arch = getParser().parseStringToEndOfStatement().trim(); 9038276479Sdim 9039296417Sdim unsigned ID = ARM::parseArch(Arch); 9040276479Sdim 9041288943Sdim if (ID == ARM::AK_INVALID) { 9042276479Sdim Error(L, "Unknown arch name"); 9043276479Sdim return false; 9044276479Sdim } 9045276479Sdim 9046292735Sdim Triple T; 9047296417Sdim MCSubtargetInfo &STI = copySTI(); 9048296417Sdim STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str()); 9049292735Sdim setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 9050292735Sdim 9051276479Sdim getTargetStreamer().emitArch(ID); 9052276479Sdim return false; 9053234353Sdim} 9054234353Sdim 9055234353Sdim/// parseDirectiveEabiAttr 9056276479Sdim/// ::= .eabi_attribute int, int [, "str"] 9057276479Sdim/// ::= .eabi_attribute Tag_name, int [, "str"] 9058234353Sdimbool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 9059280031Sdim MCAsmParser &Parser = getParser(); 9060276479Sdim int64_t Tag; 9061276479Sdim SMLoc TagLoc; 9062276479Sdim TagLoc = Parser.getTok().getLoc(); 9063276479Sdim if (Parser.getTok().is(AsmToken::Identifier)) { 9064276479Sdim StringRef Name = Parser.getTok().getIdentifier(); 9065276479Sdim Tag = ARMBuildAttrs::AttrTypeFromString(Name); 9066276479Sdim if (Tag == -1) { 9067276479Sdim Error(TagLoc, "attribute name not recognised: " + Name); 9068276479Sdim Parser.eatToEndOfStatement(); 9069276479Sdim return false; 9070276479Sdim } 9071276479Sdim Parser.Lex(); 9072276479Sdim } else { 9073276479Sdim const MCExpr *AttrExpr; 9074261991Sdim 9075276479Sdim TagLoc = Parser.getTok().getLoc(); 9076276479Sdim if (Parser.parseExpression(AttrExpr)) { 9077276479Sdim Parser.eatToEndOfStatement(); 9078276479Sdim return false; 9079276479Sdim } 9080276479Sdim 9081276479Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr); 9082276479Sdim if (!CE) { 9083276479Sdim Error(TagLoc, "expected numeric constant"); 9084276479Sdim Parser.eatToEndOfStatement(); 9085276479Sdim return false; 9086276479Sdim } 9087276479Sdim 9088276479Sdim Tag = CE->getValue(); 9089276479Sdim } 9090276479Sdim 9091276479Sdim if (Parser.getTok().isNot(AsmToken::Comma)) { 9092276479Sdim Error(Parser.getTok().getLoc(), "comma expected"); 9093276479Sdim Parser.eatToEndOfStatement(); 9094276479Sdim return false; 9095276479Sdim } 9096261991Sdim Parser.Lex(); // skip comma 9097261991Sdim 9098276479Sdim StringRef StringValue = ""; 9099276479Sdim bool IsStringValue = false; 9100261991Sdim 9101276479Sdim int64_t IntegerValue = 0; 9102276479Sdim bool IsIntegerValue = false; 9103276479Sdim 9104276479Sdim if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name) 9105276479Sdim IsStringValue = true; 9106276479Sdim else if (Tag == ARMBuildAttrs::compatibility) { 9107276479Sdim IsStringValue = true; 9108276479Sdim IsIntegerValue = true; 9109276479Sdim } else if (Tag < 32 || Tag % 2 == 0) 9110276479Sdim IsIntegerValue = true; 9111276479Sdim else if (Tag % 2 == 1) 9112276479Sdim IsStringValue = true; 9113276479Sdim else 9114276479Sdim llvm_unreachable("invalid tag type"); 9115276479Sdim 9116276479Sdim if (IsIntegerValue) { 9117276479Sdim const MCExpr *ValueExpr; 9118276479Sdim SMLoc ValueExprLoc = Parser.getTok().getLoc(); 9119276479Sdim if (Parser.parseExpression(ValueExpr)) { 9120276479Sdim Parser.eatToEndOfStatement(); 9121276479Sdim return false; 9122276479Sdim } 9123276479Sdim 9124276479Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr); 9125276479Sdim if (!CE) { 9126276479Sdim Error(ValueExprLoc, "expected numeric constant"); 9127276479Sdim Parser.eatToEndOfStatement(); 9128276479Sdim return false; 9129276479Sdim } 9130276479Sdim 9131276479Sdim IntegerValue = CE->getValue(); 9132276479Sdim } 9133276479Sdim 9134276479Sdim if (Tag == ARMBuildAttrs::compatibility) { 9135276479Sdim if (Parser.getTok().isNot(AsmToken::Comma)) 9136276479Sdim IsStringValue = false; 9137280031Sdim if (Parser.getTok().isNot(AsmToken::Comma)) { 9138280031Sdim Error(Parser.getTok().getLoc(), "comma expected"); 9139280031Sdim Parser.eatToEndOfStatement(); 9140280031Sdim return false; 9141280031Sdim } else { 9142280031Sdim Parser.Lex(); 9143280031Sdim } 9144276479Sdim } 9145276479Sdim 9146276479Sdim if (IsStringValue) { 9147276479Sdim if (Parser.getTok().isNot(AsmToken::String)) { 9148276479Sdim Error(Parser.getTok().getLoc(), "bad string constant"); 9149276479Sdim Parser.eatToEndOfStatement(); 9150276479Sdim return false; 9151276479Sdim } 9152276479Sdim 9153276479Sdim StringValue = Parser.getTok().getStringContents(); 9154276479Sdim Parser.Lex(); 9155276479Sdim } 9156276479Sdim 9157276479Sdim if (IsIntegerValue && IsStringValue) { 9158276479Sdim assert(Tag == ARMBuildAttrs::compatibility); 9159276479Sdim getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue); 9160276479Sdim } else if (IsIntegerValue) 9161276479Sdim getTargetStreamer().emitAttribute(Tag, IntegerValue); 9162276479Sdim else if (IsStringValue) 9163276479Sdim getTargetStreamer().emitTextAttribute(Tag, StringValue); 9164261991Sdim return false; 9165234353Sdim} 9166234353Sdim 9167261991Sdim/// parseDirectiveCPU 9168261991Sdim/// ::= .cpu str 9169261991Sdimbool ARMAsmParser::parseDirectiveCPU(SMLoc L) { 9170261991Sdim StringRef CPU = getParser().parseStringToEndOfStatement().trim(); 9171261991Sdim getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU); 9172276479Sdim 9173288943Sdim // FIXME: This is using table-gen data, but should be moved to 9174288943Sdim // ARMTargetParser once that is table-gen'd. 9175296417Sdim if (!getSTI().isCPUStringValid(CPU)) { 9176276479Sdim Error(L, "Unknown CPU name"); 9177276479Sdim return false; 9178276479Sdim } 9179276479Sdim 9180296417Sdim MCSubtargetInfo &STI = copySTI(); 9181296417Sdim STI.setDefaultFeatures(CPU, ""); 9182288943Sdim setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 9183276479Sdim 9184261991Sdim return false; 9185261991Sdim} 9186261991Sdim/// parseDirectiveFPU 9187261991Sdim/// ::= .fpu str 9188261991Sdimbool ARMAsmParser::parseDirectiveFPU(SMLoc L) { 9189288943Sdim SMLoc FPUNameLoc = getTok().getLoc(); 9190261991Sdim StringRef FPU = getParser().parseStringToEndOfStatement().trim(); 9191261991Sdim 9192296417Sdim unsigned ID = ARM::parseFPU(FPU); 9193288943Sdim std::vector<const char *> Features; 9194296417Sdim if (!ARM::getFPUFeatures(ID, Features)) { 9195288943Sdim Error(FPUNameLoc, "Unknown FPU name"); 9196276479Sdim return false; 9197276479Sdim } 9198261991Sdim 9199296417Sdim MCSubtargetInfo &STI = copySTI(); 9200288943Sdim for (auto Feature : Features) 9201288943Sdim STI.ApplyFeatureFlag(Feature); 9202288943Sdim setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 9203276479Sdim 9204261991Sdim getTargetStreamer().emitFPU(ID); 9205261991Sdim return false; 9206261991Sdim} 9207261991Sdim 9208261991Sdim/// parseDirectiveFnStart 9209261991Sdim/// ::= .fnstart 9210261991Sdimbool ARMAsmParser::parseDirectiveFnStart(SMLoc L) { 9211276479Sdim if (UC.hasFnStart()) { 9212261991Sdim Error(L, ".fnstart starts before the end of previous one"); 9213276479Sdim UC.emitFnStartLocNotes(); 9214276479Sdim return false; 9215261991Sdim } 9216261991Sdim 9217276479Sdim // Reset the unwind directives parser state 9218276479Sdim UC.reset(); 9219276479Sdim 9220261991Sdim getTargetStreamer().emitFnStart(); 9221276479Sdim 9222276479Sdim UC.recordFnStart(L); 9223261991Sdim return false; 9224261991Sdim} 9225261991Sdim 9226261991Sdim/// parseDirectiveFnEnd 9227261991Sdim/// ::= .fnend 9228261991Sdimbool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) { 9229261991Sdim // Check the ordering of unwind directives 9230276479Sdim if (!UC.hasFnStart()) { 9231276479Sdim Error(L, ".fnstart must precede .fnend directive"); 9232276479Sdim return false; 9233276479Sdim } 9234261991Sdim 9235261991Sdim // Reset the unwind directives parser state 9236261991Sdim getTargetStreamer().emitFnEnd(); 9237276479Sdim 9238276479Sdim UC.reset(); 9239261991Sdim return false; 9240261991Sdim} 9241261991Sdim 9242261991Sdim/// parseDirectiveCantUnwind 9243261991Sdim/// ::= .cantunwind 9244261991Sdimbool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) { 9245276479Sdim UC.recordCantUnwind(L); 9246276479Sdim 9247261991Sdim // Check the ordering of unwind directives 9248276479Sdim if (!UC.hasFnStart()) { 9249276479Sdim Error(L, ".fnstart must precede .cantunwind directive"); 9250276479Sdim return false; 9251276479Sdim } 9252276479Sdim if (UC.hasHandlerData()) { 9253261991Sdim Error(L, ".cantunwind can't be used with .handlerdata directive"); 9254276479Sdim UC.emitHandlerDataLocNotes(); 9255276479Sdim return false; 9256261991Sdim } 9257276479Sdim if (UC.hasPersonality()) { 9258261991Sdim Error(L, ".cantunwind can't be used with .personality directive"); 9259276479Sdim UC.emitPersonalityLocNotes(); 9260276479Sdim return false; 9261261991Sdim } 9262261991Sdim 9263261991Sdim getTargetStreamer().emitCantUnwind(); 9264261991Sdim return false; 9265261991Sdim} 9266261991Sdim 9267261991Sdim/// parseDirectivePersonality 9268261991Sdim/// ::= .personality name 9269261991Sdimbool ARMAsmParser::parseDirectivePersonality(SMLoc L) { 9270280031Sdim MCAsmParser &Parser = getParser(); 9271276479Sdim bool HasExistingPersonality = UC.hasPersonality(); 9272276479Sdim 9273276479Sdim UC.recordPersonality(L); 9274276479Sdim 9275261991Sdim // Check the ordering of unwind directives 9276276479Sdim if (!UC.hasFnStart()) { 9277276479Sdim Error(L, ".fnstart must precede .personality directive"); 9278276479Sdim return false; 9279276479Sdim } 9280276479Sdim if (UC.cantUnwind()) { 9281261991Sdim Error(L, ".personality can't be used with .cantunwind directive"); 9282276479Sdim UC.emitCantUnwindLocNotes(); 9283276479Sdim return false; 9284261991Sdim } 9285276479Sdim if (UC.hasHandlerData()) { 9286261991Sdim Error(L, ".personality must precede .handlerdata directive"); 9287276479Sdim UC.emitHandlerDataLocNotes(); 9288276479Sdim return false; 9289261991Sdim } 9290276479Sdim if (HasExistingPersonality) { 9291276479Sdim Parser.eatToEndOfStatement(); 9292276479Sdim Error(L, "multiple personality directives"); 9293276479Sdim UC.emitPersonalityLocNotes(); 9294276479Sdim return false; 9295276479Sdim } 9296261991Sdim 9297261991Sdim // Parse the name of the personality routine 9298261991Sdim if (Parser.getTok().isNot(AsmToken::Identifier)) { 9299261991Sdim Parser.eatToEndOfStatement(); 9300276479Sdim Error(L, "unexpected input in .personality directive."); 9301276479Sdim return false; 9302261991Sdim } 9303261991Sdim StringRef Name(Parser.getTok().getIdentifier()); 9304261991Sdim Parser.Lex(); 9305261991Sdim 9306288943Sdim MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name); 9307261991Sdim getTargetStreamer().emitPersonality(PR); 9308261991Sdim return false; 9309261991Sdim} 9310261991Sdim 9311261991Sdim/// parseDirectiveHandlerData 9312261991Sdim/// ::= .handlerdata 9313261991Sdimbool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) { 9314276479Sdim UC.recordHandlerData(L); 9315276479Sdim 9316261991Sdim // Check the ordering of unwind directives 9317276479Sdim if (!UC.hasFnStart()) { 9318276479Sdim Error(L, ".fnstart must precede .personality directive"); 9319276479Sdim return false; 9320276479Sdim } 9321276479Sdim if (UC.cantUnwind()) { 9322261991Sdim Error(L, ".handlerdata can't be used with .cantunwind directive"); 9323276479Sdim UC.emitCantUnwindLocNotes(); 9324276479Sdim return false; 9325261991Sdim } 9326261991Sdim 9327261991Sdim getTargetStreamer().emitHandlerData(); 9328261991Sdim return false; 9329261991Sdim} 9330261991Sdim 9331261991Sdim/// parseDirectiveSetFP 9332261991Sdim/// ::= .setfp fpreg, spreg [, offset] 9333261991Sdimbool ARMAsmParser::parseDirectiveSetFP(SMLoc L) { 9334280031Sdim MCAsmParser &Parser = getParser(); 9335261991Sdim // Check the ordering of unwind directives 9336276479Sdim if (!UC.hasFnStart()) { 9337276479Sdim Error(L, ".fnstart must precede .setfp directive"); 9338276479Sdim return false; 9339276479Sdim } 9340276479Sdim if (UC.hasHandlerData()) { 9341276479Sdim Error(L, ".setfp must precede .handlerdata directive"); 9342276479Sdim return false; 9343276479Sdim } 9344261991Sdim 9345261991Sdim // Parse fpreg 9346276479Sdim SMLoc FPRegLoc = Parser.getTok().getLoc(); 9347276479Sdim int FPReg = tryParseRegister(); 9348276479Sdim if (FPReg == -1) { 9349276479Sdim Error(FPRegLoc, "frame pointer register expected"); 9350276479Sdim return false; 9351276479Sdim } 9352261991Sdim 9353261991Sdim // Consume comma 9354276479Sdim if (Parser.getTok().isNot(AsmToken::Comma)) { 9355276479Sdim Error(Parser.getTok().getLoc(), "comma expected"); 9356276479Sdim return false; 9357276479Sdim } 9358261991Sdim Parser.Lex(); // skip comma 9359261991Sdim 9360261991Sdim // Parse spreg 9361276479Sdim SMLoc SPRegLoc = Parser.getTok().getLoc(); 9362276479Sdim int SPReg = tryParseRegister(); 9363276479Sdim if (SPReg == -1) { 9364276479Sdim Error(SPRegLoc, "stack pointer register expected"); 9365276479Sdim return false; 9366276479Sdim } 9367261991Sdim 9368276479Sdim if (SPReg != ARM::SP && SPReg != UC.getFPReg()) { 9369276479Sdim Error(SPRegLoc, "register should be either $sp or the latest fp register"); 9370276479Sdim return false; 9371276479Sdim } 9372261991Sdim 9373261991Sdim // Update the frame pointer register 9374276479Sdim UC.saveFPReg(FPReg); 9375261991Sdim 9376261991Sdim // Parse offset 9377261991Sdim int64_t Offset = 0; 9378261991Sdim if (Parser.getTok().is(AsmToken::Comma)) { 9379261991Sdim Parser.Lex(); // skip comma 9380261991Sdim 9381261991Sdim if (Parser.getTok().isNot(AsmToken::Hash) && 9382261991Sdim Parser.getTok().isNot(AsmToken::Dollar)) { 9383276479Sdim Error(Parser.getTok().getLoc(), "'#' expected"); 9384276479Sdim return false; 9385261991Sdim } 9386261991Sdim Parser.Lex(); // skip hash token. 9387261991Sdim 9388261991Sdim const MCExpr *OffsetExpr; 9389261991Sdim SMLoc ExLoc = Parser.getTok().getLoc(); 9390261991Sdim SMLoc EndLoc; 9391276479Sdim if (getParser().parseExpression(OffsetExpr, EndLoc)) { 9392276479Sdim Error(ExLoc, "malformed setfp offset"); 9393276479Sdim return false; 9394276479Sdim } 9395261991Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9396276479Sdim if (!CE) { 9397276479Sdim Error(ExLoc, "setfp offset must be an immediate"); 9398276479Sdim return false; 9399276479Sdim } 9400261991Sdim 9401261991Sdim Offset = CE->getValue(); 9402261991Sdim } 9403261991Sdim 9404276479Sdim getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg), 9405276479Sdim static_cast<unsigned>(SPReg), Offset); 9406261991Sdim return false; 9407261991Sdim} 9408261991Sdim 9409261991Sdim/// parseDirective 9410261991Sdim/// ::= .pad offset 9411261991Sdimbool ARMAsmParser::parseDirectivePad(SMLoc L) { 9412280031Sdim MCAsmParser &Parser = getParser(); 9413261991Sdim // Check the ordering of unwind directives 9414276479Sdim if (!UC.hasFnStart()) { 9415276479Sdim Error(L, ".fnstart must precede .pad directive"); 9416276479Sdim return false; 9417276479Sdim } 9418276479Sdim if (UC.hasHandlerData()) { 9419276479Sdim Error(L, ".pad must precede .handlerdata directive"); 9420276479Sdim return false; 9421276479Sdim } 9422261991Sdim 9423261991Sdim // Parse the offset 9424261991Sdim if (Parser.getTok().isNot(AsmToken::Hash) && 9425261991Sdim Parser.getTok().isNot(AsmToken::Dollar)) { 9426276479Sdim Error(Parser.getTok().getLoc(), "'#' expected"); 9427276479Sdim return false; 9428261991Sdim } 9429261991Sdim Parser.Lex(); // skip hash token. 9430261991Sdim 9431261991Sdim const MCExpr *OffsetExpr; 9432261991Sdim SMLoc ExLoc = Parser.getTok().getLoc(); 9433261991Sdim SMLoc EndLoc; 9434276479Sdim if (getParser().parseExpression(OffsetExpr, EndLoc)) { 9435276479Sdim Error(ExLoc, "malformed pad offset"); 9436276479Sdim return false; 9437276479Sdim } 9438261991Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9439276479Sdim if (!CE) { 9440276479Sdim Error(ExLoc, "pad offset must be an immediate"); 9441276479Sdim return false; 9442276479Sdim } 9443261991Sdim 9444261991Sdim getTargetStreamer().emitPad(CE->getValue()); 9445261991Sdim return false; 9446261991Sdim} 9447261991Sdim 9448261991Sdim/// parseDirectiveRegSave 9449261991Sdim/// ::= .save { registers } 9450261991Sdim/// ::= .vsave { registers } 9451261991Sdimbool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { 9452261991Sdim // Check the ordering of unwind directives 9453276479Sdim if (!UC.hasFnStart()) { 9454276479Sdim Error(L, ".fnstart must precede .save or .vsave directives"); 9455276479Sdim return false; 9456276479Sdim } 9457276479Sdim if (UC.hasHandlerData()) { 9458276479Sdim Error(L, ".save or .vsave must precede .handlerdata directive"); 9459276479Sdim return false; 9460276479Sdim } 9461261991Sdim 9462261991Sdim // RAII object to make sure parsed operands are deleted. 9463276479Sdim SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; 9464276479Sdim 9465276479Sdim // Parse the register list 9466276479Sdim if (parseRegisterList(Operands)) 9467276479Sdim return false; 9468276479Sdim ARMOperand &Op = (ARMOperand &)*Operands[0]; 9469276479Sdim if (!IsVector && !Op.isRegList()) { 9470276479Sdim Error(L, ".save expects GPR registers"); 9471276479Sdim return false; 9472276479Sdim } 9473276479Sdim if (IsVector && !Op.isDPRRegList()) { 9474276479Sdim Error(L, ".vsave expects DPR registers"); 9475276479Sdim return false; 9476276479Sdim } 9477276479Sdim 9478276479Sdim getTargetStreamer().emitRegSave(Op.getRegList(), IsVector); 9479276479Sdim return false; 9480276479Sdim} 9481276479Sdim 9482276479Sdim/// parseDirectiveInst 9483276479Sdim/// ::= .inst opcode [, ...] 9484276479Sdim/// ::= .inst.n opcode [, ...] 9485276479Sdim/// ::= .inst.w opcode [, ...] 9486276479Sdimbool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) { 9487280031Sdim MCAsmParser &Parser = getParser(); 9488276479Sdim int Width; 9489276479Sdim 9490276479Sdim if (isThumb()) { 9491276479Sdim switch (Suffix) { 9492276479Sdim case 'n': 9493276479Sdim Width = 2; 9494276479Sdim break; 9495276479Sdim case 'w': 9496276479Sdim Width = 4; 9497276479Sdim break; 9498276479Sdim default: 9499276479Sdim Parser.eatToEndOfStatement(); 9500276479Sdim Error(Loc, "cannot determine Thumb instruction size, " 9501276479Sdim "use inst.n/inst.w instead"); 9502276479Sdim return false; 9503261991Sdim } 9504276479Sdim } else { 9505276479Sdim if (Suffix) { 9506276479Sdim Parser.eatToEndOfStatement(); 9507276479Sdim Error(Loc, "width suffixes are invalid in ARM mode"); 9508276479Sdim return false; 9509276479Sdim } 9510276479Sdim Width = 4; 9511276479Sdim } 9512261991Sdim 9513276479Sdim if (getLexer().is(AsmToken::EndOfStatement)) { 9514276479Sdim Parser.eatToEndOfStatement(); 9515276479Sdim Error(Loc, "expected expression following directive"); 9516276479Sdim return false; 9517276479Sdim } 9518276479Sdim 9519276479Sdim for (;;) { 9520276479Sdim const MCExpr *Expr; 9521276479Sdim 9522276479Sdim if (getParser().parseExpression(Expr)) { 9523276479Sdim Error(Loc, "expected expression"); 9524276479Sdim return false; 9525276479Sdim } 9526276479Sdim 9527276479Sdim const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr); 9528276479Sdim if (!Value) { 9529276479Sdim Error(Loc, "expected constant expression"); 9530276479Sdim return false; 9531276479Sdim } 9532276479Sdim 9533276479Sdim switch (Width) { 9534276479Sdim case 2: 9535276479Sdim if (Value->getValue() > 0xffff) { 9536276479Sdim Error(Loc, "inst.n operand is too big, use inst.w instead"); 9537276479Sdim return false; 9538276479Sdim } 9539276479Sdim break; 9540276479Sdim case 4: 9541276479Sdim if (Value->getValue() > 0xffffffff) { 9542276479Sdim Error(Loc, 9543276479Sdim StringRef(Suffix ? "inst.w" : "inst") + " operand is too big"); 9544276479Sdim return false; 9545276479Sdim } 9546276479Sdim break; 9547276479Sdim default: 9548276479Sdim llvm_unreachable("only supported widths are 2 and 4"); 9549276479Sdim } 9550276479Sdim 9551276479Sdim getTargetStreamer().emitInst(Value->getValue(), Suffix); 9552276479Sdim 9553276479Sdim if (getLexer().is(AsmToken::EndOfStatement)) 9554276479Sdim break; 9555276479Sdim 9556276479Sdim if (getLexer().isNot(AsmToken::Comma)) { 9557276479Sdim Error(Loc, "unexpected token in directive"); 9558276479Sdim return false; 9559276479Sdim } 9560276479Sdim 9561276479Sdim Parser.Lex(); 9562276479Sdim } 9563276479Sdim 9564276479Sdim Parser.Lex(); 9565276479Sdim return false; 9566276479Sdim} 9567276479Sdim 9568276479Sdim/// parseDirectiveLtorg 9569276479Sdim/// ::= .ltorg | .pool 9570276479Sdimbool ARMAsmParser::parseDirectiveLtorg(SMLoc L) { 9571276479Sdim getTargetStreamer().emitCurrentConstantPool(); 9572276479Sdim return false; 9573276479Sdim} 9574276479Sdim 9575276479Sdimbool ARMAsmParser::parseDirectiveEven(SMLoc L) { 9576276479Sdim const MCSection *Section = getStreamer().getCurrentSection().first; 9577276479Sdim 9578276479Sdim if (getLexer().isNot(AsmToken::EndOfStatement)) { 9579276479Sdim TokError("unexpected token in directive"); 9580276479Sdim return false; 9581276479Sdim } 9582276479Sdim 9583276479Sdim if (!Section) { 9584280031Sdim getStreamer().InitSections(false); 9585276479Sdim Section = getStreamer().getCurrentSection().first; 9586276479Sdim } 9587276479Sdim 9588276479Sdim assert(Section && "must have section to emit alignment"); 9589276479Sdim if (Section->UseCodeAlign()) 9590276479Sdim getStreamer().EmitCodeAlignment(2); 9591276479Sdim else 9592276479Sdim getStreamer().EmitValueToAlignment(2); 9593276479Sdim 9594276479Sdim return false; 9595276479Sdim} 9596276479Sdim 9597276479Sdim/// parseDirectivePersonalityIndex 9598276479Sdim/// ::= .personalityindex index 9599276479Sdimbool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) { 9600280031Sdim MCAsmParser &Parser = getParser(); 9601276479Sdim bool HasExistingPersonality = UC.hasPersonality(); 9602276479Sdim 9603276479Sdim UC.recordPersonalityIndex(L); 9604276479Sdim 9605276479Sdim if (!UC.hasFnStart()) { 9606276479Sdim Parser.eatToEndOfStatement(); 9607276479Sdim Error(L, ".fnstart must precede .personalityindex directive"); 9608276479Sdim return false; 9609276479Sdim } 9610276479Sdim if (UC.cantUnwind()) { 9611276479Sdim Parser.eatToEndOfStatement(); 9612276479Sdim Error(L, ".personalityindex cannot be used with .cantunwind"); 9613276479Sdim UC.emitCantUnwindLocNotes(); 9614276479Sdim return false; 9615276479Sdim } 9616276479Sdim if (UC.hasHandlerData()) { 9617276479Sdim Parser.eatToEndOfStatement(); 9618276479Sdim Error(L, ".personalityindex must precede .handlerdata directive"); 9619276479Sdim UC.emitHandlerDataLocNotes(); 9620276479Sdim return false; 9621276479Sdim } 9622276479Sdim if (HasExistingPersonality) { 9623276479Sdim Parser.eatToEndOfStatement(); 9624276479Sdim Error(L, "multiple personality directives"); 9625276479Sdim UC.emitPersonalityLocNotes(); 9626276479Sdim return false; 9627276479Sdim } 9628276479Sdim 9629276479Sdim const MCExpr *IndexExpression; 9630276479Sdim SMLoc IndexLoc = Parser.getTok().getLoc(); 9631276479Sdim if (Parser.parseExpression(IndexExpression)) { 9632276479Sdim Parser.eatToEndOfStatement(); 9633276479Sdim return false; 9634276479Sdim } 9635276479Sdim 9636276479Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression); 9637276479Sdim if (!CE) { 9638276479Sdim Parser.eatToEndOfStatement(); 9639276479Sdim Error(IndexLoc, "index must be a constant number"); 9640276479Sdim return false; 9641276479Sdim } 9642276479Sdim if (CE->getValue() < 0 || 9643276479Sdim CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) { 9644276479Sdim Parser.eatToEndOfStatement(); 9645276479Sdim Error(IndexLoc, "personality routine index should be in range [0-3]"); 9646276479Sdim return false; 9647276479Sdim } 9648276479Sdim 9649276479Sdim getTargetStreamer().emitPersonalityIndex(CE->getValue()); 9650276479Sdim return false; 9651276479Sdim} 9652276479Sdim 9653276479Sdim/// parseDirectiveUnwindRaw 9654276479Sdim/// ::= .unwind_raw offset, opcode [, opcode...] 9655276479Sdimbool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) { 9656280031Sdim MCAsmParser &Parser = getParser(); 9657276479Sdim if (!UC.hasFnStart()) { 9658276479Sdim Parser.eatToEndOfStatement(); 9659276479Sdim Error(L, ".fnstart must precede .unwind_raw directives"); 9660276479Sdim return false; 9661276479Sdim } 9662276479Sdim 9663276479Sdim int64_t StackOffset; 9664276479Sdim 9665276479Sdim const MCExpr *OffsetExpr; 9666276479Sdim SMLoc OffsetLoc = getLexer().getLoc(); 9667276479Sdim if (getLexer().is(AsmToken::EndOfStatement) || 9668276479Sdim getParser().parseExpression(OffsetExpr)) { 9669276479Sdim Error(OffsetLoc, "expected expression"); 9670276479Sdim Parser.eatToEndOfStatement(); 9671276479Sdim return false; 9672276479Sdim } 9673276479Sdim 9674276479Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9675276479Sdim if (!CE) { 9676276479Sdim Error(OffsetLoc, "offset must be a constant"); 9677276479Sdim Parser.eatToEndOfStatement(); 9678276479Sdim return false; 9679276479Sdim } 9680276479Sdim 9681276479Sdim StackOffset = CE->getValue(); 9682276479Sdim 9683276479Sdim if (getLexer().isNot(AsmToken::Comma)) { 9684276479Sdim Error(getLexer().getLoc(), "expected comma"); 9685276479Sdim Parser.eatToEndOfStatement(); 9686276479Sdim return false; 9687276479Sdim } 9688276479Sdim Parser.Lex(); 9689276479Sdim 9690276479Sdim SmallVector<uint8_t, 16> Opcodes; 9691276479Sdim for (;;) { 9692276479Sdim const MCExpr *OE; 9693276479Sdim 9694276479Sdim SMLoc OpcodeLoc = getLexer().getLoc(); 9695276479Sdim if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) { 9696276479Sdim Error(OpcodeLoc, "expected opcode expression"); 9697276479Sdim Parser.eatToEndOfStatement(); 9698276479Sdim return false; 9699276479Sdim } 9700276479Sdim 9701276479Sdim const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE); 9702276479Sdim if (!OC) { 9703276479Sdim Error(OpcodeLoc, "opcode value must be a constant"); 9704276479Sdim Parser.eatToEndOfStatement(); 9705276479Sdim return false; 9706276479Sdim } 9707276479Sdim 9708276479Sdim const int64_t Opcode = OC->getValue(); 9709276479Sdim if (Opcode & ~0xff) { 9710276479Sdim Error(OpcodeLoc, "invalid opcode"); 9711276479Sdim Parser.eatToEndOfStatement(); 9712276479Sdim return false; 9713276479Sdim } 9714276479Sdim 9715276479Sdim Opcodes.push_back(uint8_t(Opcode)); 9716276479Sdim 9717276479Sdim if (getLexer().is(AsmToken::EndOfStatement)) 9718276479Sdim break; 9719276479Sdim 9720276479Sdim if (getLexer().isNot(AsmToken::Comma)) { 9721276479Sdim Error(getLexer().getLoc(), "unexpected token in directive"); 9722276479Sdim Parser.eatToEndOfStatement(); 9723276479Sdim return false; 9724276479Sdim } 9725276479Sdim 9726276479Sdim Parser.Lex(); 9727276479Sdim } 9728276479Sdim 9729276479Sdim getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes); 9730276479Sdim 9731276479Sdim Parser.Lex(); 9732276479Sdim return false; 9733276479Sdim} 9734276479Sdim 9735276479Sdim/// parseDirectiveTLSDescSeq 9736276479Sdim/// ::= .tlsdescseq tls-variable 9737276479Sdimbool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) { 9738280031Sdim MCAsmParser &Parser = getParser(); 9739280031Sdim 9740276479Sdim if (getLexer().isNot(AsmToken::Identifier)) { 9741276479Sdim TokError("expected variable after '.tlsdescseq' directive"); 9742276479Sdim Parser.eatToEndOfStatement(); 9743276479Sdim return false; 9744276479Sdim } 9745276479Sdim 9746276479Sdim const MCSymbolRefExpr *SRE = 9747288943Sdim MCSymbolRefExpr::create(Parser.getTok().getIdentifier(), 9748276479Sdim MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext()); 9749276479Sdim Lex(); 9750276479Sdim 9751276479Sdim if (getLexer().isNot(AsmToken::EndOfStatement)) { 9752276479Sdim Error(Parser.getTok().getLoc(), "unexpected token"); 9753276479Sdim Parser.eatToEndOfStatement(); 9754276479Sdim return false; 9755276479Sdim } 9756276479Sdim 9757276479Sdim getTargetStreamer().AnnotateTLSDescriptorSequence(SRE); 9758276479Sdim return false; 9759276479Sdim} 9760276479Sdim 9761276479Sdim/// parseDirectiveMovSP 9762276479Sdim/// ::= .movsp reg [, #offset] 9763276479Sdimbool ARMAsmParser::parseDirectiveMovSP(SMLoc L) { 9764280031Sdim MCAsmParser &Parser = getParser(); 9765276479Sdim if (!UC.hasFnStart()) { 9766276479Sdim Parser.eatToEndOfStatement(); 9767276479Sdim Error(L, ".fnstart must precede .movsp directives"); 9768276479Sdim return false; 9769276479Sdim } 9770276479Sdim if (UC.getFPReg() != ARM::SP) { 9771276479Sdim Parser.eatToEndOfStatement(); 9772276479Sdim Error(L, "unexpected .movsp directive"); 9773276479Sdim return false; 9774276479Sdim } 9775276479Sdim 9776276479Sdim SMLoc SPRegLoc = Parser.getTok().getLoc(); 9777276479Sdim int SPReg = tryParseRegister(); 9778276479Sdim if (SPReg == -1) { 9779276479Sdim Parser.eatToEndOfStatement(); 9780276479Sdim Error(SPRegLoc, "register expected"); 9781276479Sdim return false; 9782276479Sdim } 9783276479Sdim 9784276479Sdim if (SPReg == ARM::SP || SPReg == ARM::PC) { 9785276479Sdim Parser.eatToEndOfStatement(); 9786276479Sdim Error(SPRegLoc, "sp and pc are not permitted in .movsp directive"); 9787276479Sdim return false; 9788276479Sdim } 9789276479Sdim 9790276479Sdim int64_t Offset = 0; 9791276479Sdim if (Parser.getTok().is(AsmToken::Comma)) { 9792276479Sdim Parser.Lex(); 9793276479Sdim 9794276479Sdim if (Parser.getTok().isNot(AsmToken::Hash)) { 9795276479Sdim Error(Parser.getTok().getLoc(), "expected #constant"); 9796276479Sdim Parser.eatToEndOfStatement(); 9797276479Sdim return false; 9798276479Sdim } 9799276479Sdim Parser.Lex(); 9800276479Sdim 9801276479Sdim const MCExpr *OffsetExpr; 9802276479Sdim SMLoc OffsetLoc = Parser.getTok().getLoc(); 9803276479Sdim if (Parser.parseExpression(OffsetExpr)) { 9804276479Sdim Parser.eatToEndOfStatement(); 9805276479Sdim Error(OffsetLoc, "malformed offset expression"); 9806276479Sdim return false; 9807276479Sdim } 9808276479Sdim 9809276479Sdim const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9810276479Sdim if (!CE) { 9811276479Sdim Parser.eatToEndOfStatement(); 9812276479Sdim Error(OffsetLoc, "offset must be an immediate constant"); 9813276479Sdim return false; 9814276479Sdim } 9815276479Sdim 9816276479Sdim Offset = CE->getValue(); 9817276479Sdim } 9818276479Sdim 9819276479Sdim getTargetStreamer().emitMovSP(SPReg, Offset); 9820276479Sdim UC.saveFPReg(SPReg); 9821276479Sdim 9822276479Sdim return false; 9823276479Sdim} 9824276479Sdim 9825276479Sdim/// parseDirectiveObjectArch 9826276479Sdim/// ::= .object_arch name 9827276479Sdimbool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) { 9828280031Sdim MCAsmParser &Parser = getParser(); 9829276479Sdim if (getLexer().isNot(AsmToken::Identifier)) { 9830276479Sdim Error(getLexer().getLoc(), "unexpected token"); 9831276479Sdim Parser.eatToEndOfStatement(); 9832276479Sdim return false; 9833276479Sdim } 9834276479Sdim 9835276479Sdim StringRef Arch = Parser.getTok().getString(); 9836276479Sdim SMLoc ArchLoc = Parser.getTok().getLoc(); 9837276479Sdim getLexer().Lex(); 9838276479Sdim 9839296417Sdim unsigned ID = ARM::parseArch(Arch); 9840276479Sdim 9841288943Sdim if (ID == ARM::AK_INVALID) { 9842276479Sdim Error(ArchLoc, "unknown architecture '" + Arch + "'"); 9843276479Sdim Parser.eatToEndOfStatement(); 9844276479Sdim return false; 9845276479Sdim } 9846276479Sdim 9847276479Sdim getTargetStreamer().emitObjectArch(ID); 9848276479Sdim 9849276479Sdim if (getLexer().isNot(AsmToken::EndOfStatement)) { 9850276479Sdim Error(getLexer().getLoc(), "unexpected token"); 9851276479Sdim Parser.eatToEndOfStatement(); 9852276479Sdim } 9853276479Sdim 9854276479Sdim return false; 9855276479Sdim} 9856276479Sdim 9857276479Sdim/// parseDirectiveAlign 9858276479Sdim/// ::= .align 9859276479Sdimbool ARMAsmParser::parseDirectiveAlign(SMLoc L) { 9860276479Sdim // NOTE: if this is not the end of the statement, fall back to the target 9861276479Sdim // agnostic handling for this directive which will correctly handle this. 9862276479Sdim if (getLexer().isNot(AsmToken::EndOfStatement)) 9863261991Sdim return true; 9864261991Sdim 9865276479Sdim // '.align' is target specifically handled to mean 2**2 byte alignment. 9866276479Sdim if (getStreamer().getCurrentSection().first->UseCodeAlign()) 9867276479Sdim getStreamer().EmitCodeAlignment(4, 0); 9868276479Sdim else 9869276479Sdim getStreamer().EmitValueToAlignment(4, 0, 1, 0); 9870276479Sdim 9871261991Sdim return false; 9872261991Sdim} 9873261991Sdim 9874276479Sdim/// parseDirectiveThumbSet 9875276479Sdim/// ::= .thumb_set name, value 9876276479Sdimbool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) { 9877280031Sdim MCAsmParser &Parser = getParser(); 9878280031Sdim 9879276479Sdim StringRef Name; 9880276479Sdim if (Parser.parseIdentifier(Name)) { 9881276479Sdim TokError("expected identifier after '.thumb_set'"); 9882276479Sdim Parser.eatToEndOfStatement(); 9883276479Sdim return false; 9884276479Sdim } 9885276479Sdim 9886276479Sdim if (getLexer().isNot(AsmToken::Comma)) { 9887276479Sdim TokError("expected comma after name '" + Name + "'"); 9888276479Sdim Parser.eatToEndOfStatement(); 9889276479Sdim return false; 9890276479Sdim } 9891276479Sdim Lex(); 9892276479Sdim 9893288943Sdim MCSymbol *Sym; 9894276479Sdim const MCExpr *Value; 9895288943Sdim if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true, 9896288943Sdim Parser, Sym, Value)) 9897288943Sdim return true; 9898276479Sdim 9899288943Sdim getTargetStreamer().emitThumbSet(Sym, Value); 9900276479Sdim return false; 9901276479Sdim} 9902276479Sdim 9903198892Srdivacky/// Force static initialization. 9904198090Srdivackyextern "C" void LLVMInitializeARMAsmParser() { 9905276479Sdim RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget); 9906276479Sdim RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget); 9907276479Sdim RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget); 9908276479Sdim RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget); 9909198090Srdivacky} 9910212904Sdim 9911218893Sdim#define GET_REGISTER_MATCHER 9912239462Sdim#define GET_SUBTARGET_FEATURE_NAME 9913218893Sdim#define GET_MATCHER_IMPLEMENTATION 9914212904Sdim#include "ARMGenAsmMatcher.inc" 9915249423Sdim 9916288943Sdim// FIXME: This structure should be moved inside ARMTargetParser 9917288943Sdim// when we start to table-generate them, and we can use the ARM 9918288943Sdim// flags below, that were generated by table-gen. 9919280031Sdimstatic const struct { 9920296417Sdim const unsigned Kind; 9921296417Sdim const uint64_t ArchCheck; 9922288943Sdim const FeatureBitset Features; 9923276479Sdim} Extensions[] = { 9924288943Sdim { ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} }, 9925288943Sdim { ARM::AEK_CRYPTO, Feature_HasV8, 9926288943Sdim {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} }, 9927288943Sdim { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} }, 9928296417Sdim { (ARM::AEK_HWDIV | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass, 9929288943Sdim {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} }, 9930288943Sdim { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} }, 9931288943Sdim { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} }, 9932296417Sdim { ARM::AEK_SEC, Feature_HasV6K, {ARM::FeatureTrustZone} }, 9933276479Sdim // FIXME: Only available in A-class, isel not predicated 9934288943Sdim { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} }, 9935296417Sdim { ARM::AEK_FP16, Feature_HasV8_2a, {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} }, 9936288943Sdim // FIXME: Unsupported extensions. 9937288943Sdim { ARM::AEK_OS, Feature_None, {} }, 9938288943Sdim { ARM::AEK_IWMMXT, Feature_None, {} }, 9939288943Sdim { ARM::AEK_IWMMXT2, Feature_None, {} }, 9940288943Sdim { ARM::AEK_MAVERICK, Feature_None, {} }, 9941288943Sdim { ARM::AEK_XSCALE, Feature_None, {} }, 9942276479Sdim}; 9943276479Sdim 9944276479Sdim/// parseDirectiveArchExtension 9945276479Sdim/// ::= .arch_extension [no]feature 9946276479Sdimbool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) { 9947280031Sdim MCAsmParser &Parser = getParser(); 9948280031Sdim 9949276479Sdim if (getLexer().isNot(AsmToken::Identifier)) { 9950276479Sdim Error(getLexer().getLoc(), "unexpected token"); 9951276479Sdim Parser.eatToEndOfStatement(); 9952276479Sdim return false; 9953276479Sdim } 9954276479Sdim 9955280031Sdim StringRef Name = Parser.getTok().getString(); 9956276479Sdim SMLoc ExtLoc = Parser.getTok().getLoc(); 9957276479Sdim getLexer().Lex(); 9958276479Sdim 9959276479Sdim bool EnableFeature = true; 9960280031Sdim if (Name.startswith_lower("no")) { 9961276479Sdim EnableFeature = false; 9962280031Sdim Name = Name.substr(2); 9963276479Sdim } 9964296417Sdim unsigned FeatureKind = ARM::parseArchExt(Name); 9965288943Sdim if (FeatureKind == ARM::AEK_INVALID) 9966288943Sdim Error(ExtLoc, "unknown architectural extension: " + Name); 9967276479Sdim 9968280031Sdim for (const auto &Extension : Extensions) { 9969288943Sdim if (Extension.Kind != FeatureKind) 9970276479Sdim continue; 9971276479Sdim 9972288943Sdim if (Extension.Features.none()) 9973280031Sdim report_fatal_error("unsupported architectural extension: " + Name); 9974280031Sdim 9975280031Sdim if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) { 9976280031Sdim Error(ExtLoc, "architectural extension '" + Name + "' is not " 9977276479Sdim "allowed for the current base architecture"); 9978276479Sdim return false; 9979276479Sdim } 9980276479Sdim 9981296417Sdim MCSubtargetInfo &STI = copySTI(); 9982288943Sdim FeatureBitset ToggleFeatures = EnableFeature 9983288943Sdim ? (~STI.getFeatureBits() & Extension.Features) 9984288943Sdim : ( STI.getFeatureBits() & Extension.Features); 9985288943Sdim 9986280031Sdim uint64_t Features = 9987280031Sdim ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures)); 9988280031Sdim setAvailableFeatures(Features); 9989276479Sdim return false; 9990276479Sdim } 9991276479Sdim 9992280031Sdim Error(ExtLoc, "unknown architectural extension: " + Name); 9993276479Sdim Parser.eatToEndOfStatement(); 9994276479Sdim return false; 9995276479Sdim} 9996276479Sdim 9997249423Sdim// Define this matcher function after the auto-generated include so we 9998249423Sdim// have the match class enum definitions. 9999276479Sdimunsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 10000249423Sdim unsigned Kind) { 10001276479Sdim ARMOperand &Op = static_cast<ARMOperand &>(AsmOp); 10002249423Sdim // If the kind is a token for a literal immediate, check if our asm 10003249423Sdim // operand matches. This is for InstAliases which have a fixed-value 10004249423Sdim // immediate in the syntax. 10005276479Sdim switch (Kind) { 10006276479Sdim default: break; 10007276479Sdim case MCK__35_0: 10008276479Sdim if (Op.isImm()) 10009276479Sdim if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm())) 10010276479Sdim if (CE->getValue() == 0) 10011276479Sdim return Match_Success; 10012276479Sdim break; 10013280031Sdim case MCK_ModImm: 10014276479Sdim if (Op.isImm()) { 10015276479Sdim const MCExpr *SOExpr = Op.getImm(); 10016276479Sdim int64_t Value; 10017288943Sdim if (!SOExpr->evaluateAsAbsolute(Value)) 10018276479Sdim return Match_Success; 10019276479Sdim assert((Value >= INT32_MIN && Value <= UINT32_MAX) && 10020276479Sdim "expression value must be representable in 32 bits"); 10021276479Sdim } 10022276479Sdim break; 10023296417Sdim case MCK_rGPR: 10024296417Sdim if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP) 10025296417Sdim return Match_Success; 10026296417Sdim break; 10027276479Sdim case MCK_GPRPair: 10028276479Sdim if (Op.isReg() && 10029276479Sdim MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg())) 10030249423Sdim return Match_Success; 10031276479Sdim break; 10032249423Sdim } 10033249423Sdim return Match_InvalidOperand; 10034249423Sdim} 10035