ARM/AsmParser/ARMAsmParser.cpp

204   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
495     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
505     ARM_AM::ShiftOpc ShiftTy;
515     ARM_AM::ShiftOpc ShiftTy;
522     ARM_AM::ShiftOpc ShiftTy;
706     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
977     return (ARM_AM::getSOImmVal(Value) != -1 ||
978             ARM_AM::getSOImmVal(-Value) != -1);
985     return ARM_AM::getT2SOImmVal(Value) != -1;
992     return ARM_AM::getT2SOImmVal(Value) == -1 &&
993       ARM_AM::getT2SOImmVal(~Value) != -1;
1001     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1002       ARM_AM::getT2SOImmVal(-Value) != -1;
1029     return ARM_AM::getSOImmVal(~Value) != -1;
1036     return ARM_AM::getSOImmVal(Value) == -1 &&
1037       ARM_AM::getSOImmVal(-Value) != -1;
1042     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1149     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1163       return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1188         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1194         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1209     if (Memory.ShiftType == ARM_AM::no_shift)
1211     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1219         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1568     return ARM_AM::isNEONi16splat(Value);
1578     return ARM_AM::isNEONi16splat(~Value & 0xffff);
1590     return ARM_AM::isNEONi32splat(Value);
1600     return ARM_AM::isNEONi32splat(~Value);
1732       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1743       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1787     uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
1794     uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
1829     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2045       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2049       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2053       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2066     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2070     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2089       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2093       Val = ARM_AM::getAM3Opc(AddSub, Val);
2097       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2108         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2117     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2121     Val = ARM_AM::getAM3Opc(AddSub, Val);
2139     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2143     Val = ARM_AM::getAM5Opc(AddSub, Val);
2232       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2314     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2315     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2374     Value = ARM_AM::encodeNEONi16splat(Value);
2383     Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2392     Value = ARM_AM::encodeNEONi32splat(Value);
2401     Value = ARM_AM::encodeNEONi32splat(~Value);
2542   CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2556   CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2688             unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2706   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2813     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2814       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2837        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2843        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2979   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2980       .Case("asl", ARM_AM::lsl)
2981       .Case("lsl", ARM_AM::lsl)
2982       .Case("lsr", ARM_AM::lsr)
2983       .Case("asr", ARM_AM::asr)
2984       .Case("ror", ARM_AM::ror)
2985       .Case("rrx", ARM_AM::rrx)
2986       .Default(ARM_AM::no_shift);
2988   if (ShiftTy == ARM_AM::no_shift)
3005   if (ShiftTy == ARM_AM::rrx) {
3032           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3033           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3040         ShiftTy = ARM_AM::lsl;
3056   if (ShiftReg && ShiftTy != ARM_AM::rrx)
4353     int Enc = ARM_AM::getSOImmVal(Imm1);
4527   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4609   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4718                                              ARM_AM::no_shift, 0, 0, false,
4775                                              ARM_AM::no_shift, 0, Align,
4824                                              ARM_AM::no_shift, 0, 0,
4853   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4885 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4895     St = ARM_AM::lsl;
4897     St = ARM_AM::lsr;
4899     St = ARM_AM::asr;
4901     St = ARM_AM::ror;
4903     St = ARM_AM::rrx;
4910   if (St != ARM_AM::rrx) {
4930         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4931         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4935       St = ARM_AM::lsl;
5013     float RealVal = ARM_AM::getFPImmFloat(Val);
6723         ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
7881     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7883     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7884     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7885     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7886     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
7915     switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7917     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7918     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7919     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7920     case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7921     case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7923     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7946     ARM_AM::ShiftOpc ShiftTy;
7949     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7950     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7951     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7952     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7954     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7971     ARM_AM::ShiftOpc ShiftTy;
7974     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7975     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7976     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7977     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7983     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7985     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7999     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
8081         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8090         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8347     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8349     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8351     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8372     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8373     if (SOpc == ARM_AM::rrx) return false;
8385     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8386         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {