Searched refs:VTs (Results 1 - 25 of 45) sorted by relevance

12

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFSelectionDAGInfo.cpp35 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
37 Dst = DAG.getNode(BPFISD::MEMCPY, dl, VTs, Chain, Dst, Src,
H A DBPFISelLowering.cpp525 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); local
528 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.cpp34 SmallVector<EVT, 4> VTs; local
35 ComputeValueVTs(TLI, DL, Ty, VTs);
37 for (EVT VT : VTs) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp147 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); local
158 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2,
161 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2,
199 SDVTList VTs = DAG.getVTList(PtrVT, MVT::i32, MVT::Other); local
205 SDValue End = DAG.getNode(SystemZISD::SEARCH_STRING, DL, VTs, Chain,
224 SDVTList VTs = DAG.getVTList(Dest.getValueType(), MVT::Other); local
225 SDValue EndDest = DAG.getNode(SystemZISD::STPCPY, DL, VTs, Chain, Dest, Src,
234 SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::i32, MVT::Other); local
236 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src2, Src1,
253 SDVTList VTs local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1544 SDVTList VTs, EVT MemVT,
1546 :MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1562 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1564 : MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1580 SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
1581 : X86StoreSDNode(X86ISD::VTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {}
1592 SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
1593 : X86StoreSDNode(X86ISD::VTRUNCSTOREUS, Order, dl, VTs, MemVT, MMO) {}
1604 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1606 : X86MaskedStoreSDNode(X86ISD::VMTRUNCSTORES, Order, dl, VTs, MemV
1543 X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1561 X86MaskedStoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1579 TruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1591 TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1603 MaskedTruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1616 MaskedTruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1631 X86MaskedGatherScatterSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1649 X86MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1663 X86MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
[all...]
H A DX86ISelDAGToDAG.cpp1127 SDVTList VTs = CurDAG->getVTList(MVT::Other); local
1129 Store = CurDAG->getMemIntrinsicNode(X86ISD::FST, dl, VTs, Ops, MemVT,
1144 SDVTList VTs = CurDAG->getVTList(DstVT, MVT::Other); local
1146 Result = CurDAG->getMemIntrinsicNode(X86ISD::FLD, dl, VTs, Ops, MemVT,
3613 SDVTList VTs = CurDAG->getVTList(NVT, MVT::i32, MVT::Other); local
3614 NewNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
3649 SDVTList VTs = CurDAG->getVTList(VT, MVT::i32, MVT::Other); local
3650 MachineSDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
3659 SDVTList VTs = CurDAG->getVTList(VT, MVT::i32); local
3660 MachineSDNode *CNode = CurDAG->getMachineNode(ROpc, dl, VTs, Op
3682 SDVTList VTs = CurDAG->getVTList(VT, MVT::i32, MVT::Other, MVT::Glue); local
3693 SDVTList VTs = CurDAG->getVTList(VT, MVT::i32, MVT::Glue); local
4328 SDVTList VTs = CurDAG->getVTList(MaskVT, MVT::Other); local
4671 SDVTList VTs = CurDAG->getVTList(NVT, MVT::i32, MVT::Other); local
4737 SDVTList VTs; local
4754 SDVTList VTs; local
4819 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue); local
4830 SDVTList VTs = CurDAG->getVTList(MVT::Glue); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.h328 SmallVector<ValueTypeByHwMode, 4> VTs; member in class:llvm::CodeGenRegisterClass
348 ArrayRef<ValueTypeByHwMode> getValueTypes() const { return VTs; }
349 unsigned getNumValueTypes() const { return VTs.size(); }
352 return std::find(VTs.begin(), VTs.end(), VT) != VTs.end();
356 if (VTNum < VTs.size())
357 return VTs[VTNum];
H A DCallingConvEmitter.cpp100 ListInit *VTs = Action->getValueAsListInit("VTs"); local
101 for (unsigned i = 0, e = VTs->size(); i != e; ++i) {
102 Record *VT = VTs->getElementAsRecord(i);
H A DDAGISelMatcher.cpp295 for (unsigned i = 0, e = VTs.size(); i != e; ++i)
296 OS << ' ' << getEnumName(VTs[i]);
318 return M->OpcodeName == OpcodeName && M->VTs == VTs &&
H A DDAGISelMatcher.h987 const SmallVector<MVT::SimpleValueType, 3> VTs; member in class:llvm::EmitNodeMatcherCommon
1003 VTs(vts.begin(), vts.end()), Operands(operands.begin(), operands.end()),
1009 unsigned getNumVTs() const { return VTs.size(); }
1011 assert(i < VTs.size());
1012 return VTs[i];
1021 const SmallVectorImpl<MVT::SimpleValueType> &getVTList() const { return VTs; }
H A DDAGISelMatcherOpt.cpp125 const SmallVectorImpl<MVT::SimpleValueType> &VTs = EN->getVTList(); local
128 VTs, Operands,
H A DCodeGenTarget.cpp316 if (llvm::none_of(SubClassWithSubReg->VTs,
382 LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end());
H A DRegisterInfoEmitter.cpp1236 for (const ValueTypeByHwMode &VVT : RC.VTs)
1284 std::vector<MVT::SimpleValueType> VTs; local
1285 for (const ValueTypeByHwMode &VVT : RC.VTs)
1286 VTs.push_back(VVT.get(M).SimpleTy);
1287 OS << ", VTLists+" << VTSeqs.get(VTs) << " }, // "
H A DCodeGenRegisters.cpp754 VTs.push_back(getValueTypeByHwMode(Type, RegBank.getHwModes()));
756 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
795 assert((RSI.hasDefault() || Size != 0 || VTs[0].isSimple()) &&
800 : VTs[0].getSimple().getSizeInBits();
846 VTs = Super.VTs;
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h79 const EVT *VTs; member in struct:llvm::SDVTList
1096 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1097 : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
1101 assert(NumValues == VTs.NumVTs &&
1296 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1483 SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
1484 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
1766 SDVTList VTs, int64_
1482 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO) argument
1765 LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, int64_t Size, int64_t Offset) argument
2192 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) argument
2226 LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, MachineMemOperand *MMO) argument
2254 StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, MachineMemOperand *MMO) argument
2286 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) argument
2331 MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, bool IsExpanding, EVT MemVT, MachineMemOperand *MMO) argument
2360 MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing, EVT MemVT, MachineMemOperand *MMO) argument
2396 MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexType IndexType) argument
2438 MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexType IndexType) argument
2457 MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexType IndexType) argument
2481 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs) argument
[all...]
H A DSelectionDAG.h95 const EVT *VTs; member in class:llvm::SDVTListNode
103 FastID(ID), VTs(VT), NumVTs(Num) {
108 SDVTList result = {VTs, NumVTs};
378 SDVTList VTs, EVT MemoryVT,
380 return SDNodeTy(Opc, Order, DebugLoc(), VTs, MemoryVT, MMO)
575 SDVTList getVTList(ArrayRef<EVT> VTs);
714 SDVTList VTs = getVTList(MVT::Other, MVT::Glue); local
716 return getNode(ISD::CopyToReg, dl, VTs,
723 SDVTList VTs = getVTList(MVT::Other, MVT::Glue); local
725 return getNode(ISD::CopyToReg, dl, VTs,
377 getSyntheticNodeSubclassData(unsigned Opc, unsigned Order, SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO) argument
730 SDVTList VTs = getVTList(VT, MVT::Other); local
740 SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue); local
885 SDVTList VTs = getVTList(MVT::Other, MVT::Glue); local
1802 getTargetMemSDNode(SDVTList VTs, ArrayRef<SDValue> Ops, const SDLoc &dl, EVT MemVT, MachineMemOperand *MMO) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp84 static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs) { argument
85 SDVTList Res = {VTs, NumVTs};
458 ID.AddPointer(VTList.VTs);
4759 SDVTList VTs = getVTList(VT);
4763 AddNodeIDNode(ID, Opcode, VTs, Ops);
4770 N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
4775 N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
5411 "Extract subvector VTs must be a vectors!");
5414 "Extract subvector VTs must have the same element type!");
5508 SDVTList VTs
[all...]
H A DScheduleDAGSDNodes.cpp140 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs, argument
146 SDVTList VTList = DAG->getVTList(VTs);
175 SmallVector<EVT, 4> VTs(N->value_begin(), N->value_end());
177 VTs.push_back(MVT::Glue);
179 CloneNodeWithValues(N, DAG, VTs, Glue);
H A DSelectionDAGISel.cpp2243 const EVT VTs[] = {MVT::Other, MVT::Glue}; local
2244 SDValue New = CurDAG->getNode(Branch ? ISD::INLINEASM_BR : ISD::INLINEASM, DL, VTs, Ops);
3400 // If this is one of the compressed forms, get the number of VTs based
3408 SmallVector<EVT, 4> VTs;
3414 VTs.push_back(VT);
3418 VTs.push_back(MVT::Other);
3420 VTs.push_back(MVT::Glue);
3425 if (VTs.size() == 1)
3426 VTList = CurDAG->getVTList(VTs[0]);
3427 else if (VTs
[all...]
H A DLegalizeDAG.cpp2586 SDVTList VTs = DAG.getVTList(NewOutTy, MVT::Other);
2587 Operation = DAG.getNode(OpToUse, dl, VTs, N->getOperand(0), LegalOp);
2794 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2796 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2817 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2819 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3200 SDVTList VTs = DAG.getVTList(VT, VT);
3201 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3284 SDVTList VTs = DAG.getVTList(VT, VT);
3285 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp
[all...]
H A DLegalizeIntegerTypes.cpp264 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other); local
266 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
288 SDVTList VTs = local
291 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
941 EVT VTs[] = {SVT, MVT::Other}; local
944 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers);
1158 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1)); local
1159 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
1868 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other); local
1870 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
2798 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other); local
3014 SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other); local
3728 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp177 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other, MVT::Glue); local
185 Dst = DAG.getNode(ARMISD::MEMCPY, dl, VTs, Chain, Dst, Src,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1465 SmallVector<EVT, 16> VTs; local
1467 ComputePTXValueVTs(*this, DL, Ty, VTs, &Offsets);
1507 auto VectorInfo = VectorizePTXValueVTs(VTs, Offsets, ArgAlign);
1509 for (unsigned j = 0, je = VTs.size(); j != je; ++j) {
1518 EVT EltVT = VTs[j];
1521 assert(VTs.size() == 1 && "Scalar can't have multiple parts.");
1556 EVT TheStoreType = ExtendIntegerParam ? MVT::i32 : VTs[j];
1572 if (VTs.size() > 0)
1579 SmallVector<EVT, 16> VTs;
1583 ComputePTXValueVTs(*this, DL, PTy->getElementType(), VTs, local
1766 SmallVector<EVT, 16> VTs; local
2557 SmallVector<EVT, 16> VTs; local
2675 SmallVector<EVT, 16> VTs; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp2152 SDVTList VTs = CurDAG->getVTList(MVT::Other);
2154 SDNode *Result = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
2189 SDVTList VTs = CurDAG->getVTList(MVT::Other);
2191 SDNode *Result = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
2206 SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1);
2207 Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs, Ops);
2213 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1);
2214 Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs, Ops);
2220 SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1);
2221 Result = CurDAG->getMachineNode(Hexagon::V6_vsubcarry, SDLoc(N), VTs, Op
[all...]
H A DHexagonISelLowering.cpp696 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); local
697 return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
738 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); local
739 SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
2807 SDVTList VTs = Op.getNode()->getVTList(); local
2808 assert(VTs.NumVTs == 2);
2809 assert(VTs.VTs[1] == MVT::i1);
2820 SDValue Op = DAG.getNode(ISD::ADD, dl, VTs.VTs[
[all...]

Completed in 636 milliseconds

12