1193323Sed//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2193323Sed// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6193323Sed// 7193323Sed//===----------------------------------------------------------------------===// 8193323Sed// 9193323Sed// This tablegen backend is responsible for emitting a description of a target 10193323Sed// register file for a code generator. It uses instances of the Register, 11193323Sed// RegisterAliases, and RegisterClass classes to gather this information. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15239462Sdim#include "CodeGenRegisters.h" 16193323Sed#include "CodeGenTarget.h" 17341825Sdim#include "SequenceToOffsetTable.h" 18314564Sdim#include "Types.h" 19309124Sdim#include "llvm/ADT/ArrayRef.h" 20226633Sdim#include "llvm/ADT/BitVector.h" 21341825Sdim#include "llvm/ADT/STLExtras.h" 22309124Sdim#include "llvm/ADT/SetVector.h" 23309124Sdim#include "llvm/ADT/SmallVector.h" 24309124Sdim#include "llvm/ADT/SparseBitVector.h" 25234982Sdim#include "llvm/ADT/Twine.h" 26309124Sdim#include "llvm/Support/Casting.h" 27327952Sdim#include "llvm/Support/CommandLine.h" 28224145Sdim#include "llvm/Support/Format.h" 29341825Sdim#include "llvm/Support/MachineValueType.h" 30309124Sdim#include "llvm/Support/raw_ostream.h" 31239462Sdim#include "llvm/TableGen/Error.h" 32239462Sdim#include "llvm/TableGen/Record.h" 33309124Sdim#include "llvm/TableGen/SetTheory.h" 34239462Sdim#include "llvm/TableGen/TableGenBackend.h" 35195340Sed#include <algorithm> 36309124Sdim#include <cassert> 37309124Sdim#include <cstddef> 38309124Sdim#include <cstdint> 39309124Sdim#include <deque> 40309124Sdim#include <iterator> 41193323Sed#include <set> 42309124Sdim#include <string> 43239462Sdim#include <vector> 44309124Sdim 45193323Sedusing namespace llvm; 46193323Sed 47327952Sdimcl::OptionCategory RegisterInfoCat("Options for -gen-register-info"); 48327952Sdim 49327952Sdimstatic cl::opt<bool> 50327952Sdim RegisterInfoDebug("register-info-debug", cl::init(false), 51327952Sdim cl::desc("Dump register information to help debugging"), 52327952Sdim cl::cat(RegisterInfoCat)); 53327952Sdim 54239462Sdimnamespace { 55309124Sdim 56239462Sdimclass RegisterInfoEmitter { 57327952Sdim CodeGenTarget Target; 58239462Sdim RecordKeeper &Records; 59309124Sdim 60239462Sdimpublic: 61327952Sdim RegisterInfoEmitter(RecordKeeper &R) : Target(R), Records(R) { 62327952Sdim CodeGenRegBank &RegBank = Target.getRegBank(); 63327952Sdim RegBank.computeDerivedInfo(); 64327952Sdim } 65239462Sdim 66239462Sdim // runEnums - Print out enum values for all of the registers. 67239462Sdim void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 68239462Sdim 69239462Sdim // runMCDesc - Print out MC register descriptions. 70239462Sdim void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 71239462Sdim 72239462Sdim // runTargetHeader - Emit a header fragment for the register info emitter. 73239462Sdim void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, 74239462Sdim CodeGenRegBank &Bank); 75239462Sdim 76239462Sdim // runTargetDesc - Output the target register and register file descriptions. 77239462Sdim void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, 78239462Sdim CodeGenRegBank &Bank); 79239462Sdim 80239462Sdim // run - Output the register file description. 81239462Sdim void run(raw_ostream &o); 82239462Sdim 83327952Sdim void debugDump(raw_ostream &OS); 84327952Sdim 85239462Sdimprivate: 86280031Sdim void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs, 87280031Sdim bool isCtor); 88239462Sdim void EmitRegMappingTables(raw_ostream &o, 89280031Sdim const std::deque<CodeGenRegister> &Regs, 90239462Sdim bool isCtor); 91239462Sdim void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 92239462Sdim const std::string &ClassName); 93243830Sdim void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, 94243830Sdim const std::string &ClassName); 95280031Sdim void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank, 96280031Sdim const std::string &ClassName); 97239462Sdim}; 98239462Sdim 99309124Sdim} // end anonymous namespace 100309124Sdim 101193323Sed// runEnums - Print out enum values for all of the registers. 102234982Sdimvoid RegisterInfoEmitter::runEnums(raw_ostream &OS, 103234982Sdim CodeGenTarget &Target, CodeGenRegBank &Bank) { 104280031Sdim const auto &Registers = Bank.getRegisters(); 105193323Sed 106234982Sdim // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 107234353Sdim assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 108234353Sdim 109321369Sdim StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); 110193323Sed 111239462Sdim emitSourceFileHeader("Target Register Enum Values", OS); 112224145Sdim 113224145Sdim OS << "\n#ifdef GET_REGINFO_ENUM\n"; 114309124Sdim OS << "#undef GET_REGINFO_ENUM\n\n"; 115224145Sdim 116193323Sed OS << "namespace llvm {\n\n"; 117193323Sed 118226633Sdim OS << "class MCRegisterClass;\n" 119314564Sdim << "extern const MCRegisterClass " << Target.getName() 120234353Sdim << "MCRegisterClasses[];\n\n"; 121226633Sdim 122193323Sed if (!Namespace.empty()) 123193323Sed OS << "namespace " << Namespace << " {\n"; 124208599Srdivacky OS << "enum {\n NoRegister,\n"; 125193323Sed 126280031Sdim for (const auto &Reg : Registers) 127280031Sdim OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; 128280031Sdim assert(Registers.size() == Registers.back().EnumValue && 129221345Sdim "Register enum value mismatch!"); 130208599Srdivacky OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 131208599Srdivacky OS << "};\n"; 132193323Sed if (!Namespace.empty()) 133309124Sdim OS << "} // end namespace " << Namespace << "\n"; 134208599Srdivacky 135280031Sdim const auto &RegisterClasses = Bank.getRegClasses(); 136224145Sdim if (!RegisterClasses.empty()) { 137234353Sdim 138234353Sdim // RegisterClass enums are stored as uint16_t in the tables. 139234353Sdim assert(RegisterClasses.size() <= 0xffff && 140234353Sdim "Too many register classes to fit in tables"); 141234353Sdim 142309124Sdim OS << "\n// Register classes\n\n"; 143208599Srdivacky if (!Namespace.empty()) 144208599Srdivacky OS << "namespace " << Namespace << " {\n"; 145224145Sdim OS << "enum {\n"; 146280031Sdim for (const auto &RC : RegisterClasses) 147280031Sdim OS << " " << RC.getName() << "RegClassID" 148280031Sdim << " = " << RC.EnumValue << ",\n"; 149224145Sdim OS << "\n };\n"; 150224145Sdim if (!Namespace.empty()) 151309124Sdim OS << "} // end namespace " << Namespace << "\n\n"; 152224145Sdim } 153224145Sdim 154261991Sdim const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); 155224145Sdim // If the only definition is the default NoRegAltName, we don't need to 156224145Sdim // emit anything. 157224145Sdim if (RegAltNameIndices.size() > 1) { 158309124Sdim OS << "\n// Register alternate name indices\n\n"; 159224145Sdim if (!Namespace.empty()) 160224145Sdim OS << "namespace " << Namespace << " {\n"; 161224145Sdim OS << "enum {\n"; 162224145Sdim for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 163224145Sdim OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 164224145Sdim OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 165208599Srdivacky OS << "};\n"; 166208599Srdivacky if (!Namespace.empty()) 167309124Sdim OS << "} // end namespace " << Namespace << "\n\n"; 168208599Srdivacky } 169224145Sdim 170280031Sdim auto &SubRegIndices = Bank.getSubRegIndices(); 171234353Sdim if (!SubRegIndices.empty()) { 172309124Sdim OS << "\n// Subregister indices\n\n"; 173280031Sdim std::string Namespace = SubRegIndices.front().getNamespace(); 174234353Sdim if (!Namespace.empty()) 175234353Sdim OS << "namespace " << Namespace << " {\n"; 176234353Sdim OS << "enum {\n NoSubRegister,\n"; 177280031Sdim unsigned i = 0; 178280031Sdim for (const auto &Idx : SubRegIndices) 179280031Sdim OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; 180239462Sdim OS << " NUM_TARGET_SUBREGS\n};\n"; 181234353Sdim if (!Namespace.empty()) 182309124Sdim OS << "} // end namespace " << Namespace << "\n\n"; 183234353Sdim } 184224145Sdim 185309124Sdim OS << "} // end namespace llvm\n\n"; 186224145Sdim OS << "#endif // GET_REGINFO_ENUM\n\n"; 187193323Sed} 188193323Sed 189280031Sdimstatic void printInt(raw_ostream &OS, int Val) { 190280031Sdim OS << Val; 191280031Sdim} 192280031Sdim 193234353Sdimvoid RegisterInfoEmitter:: 194234353SdimEmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 195234353Sdim const std::string &ClassName) { 196234353Sdim unsigned NumRCs = RegBank.getRegClasses().size(); 197234353Sdim unsigned NumSets = RegBank.getNumRegPressureSets(); 198234353Sdim 199234353Sdim OS << "/// Get the weight in units of pressure for this register class.\n" 200234353Sdim << "const RegClassWeight &" << ClassName << "::\n" 201234353Sdim << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 202234353Sdim << " static const RegClassWeight RCWeightTable[] = {\n"; 203280031Sdim for (const auto &RC : RegBank.getRegClasses()) { 204288943Sdim const CodeGenRegister::Vec &Regs = RC.getMembers(); 205341825Sdim if (Regs.empty() || RC.Artificial) 206234353Sdim OS << " {0, 0"; 207234353Sdim else { 208234353Sdim std::vector<unsigned> RegUnits; 209341825Sdim RC.buildRegUnitSet(RegBank, RegUnits); 210234353Sdim OS << " {" << (*Regs.begin())->getWeight(RegBank) 211234353Sdim << ", " << RegBank.getRegUnitSetWeight(RegUnits); 212234353Sdim } 213234353Sdim OS << "}, \t// " << RC.getName() << "\n"; 214234353Sdim } 215280031Sdim OS << " };\n" 216234353Sdim << " return RCWeightTable[RC->getID()];\n" 217234353Sdim << "}\n\n"; 218234353Sdim 219249423Sdim // Reasonable targets (not ARMv7) have unit weight for all units, so don't 220249423Sdim // bother generating a table. 221249423Sdim bool RegUnitsHaveUnitWeight = true; 222249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 223249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 224249423Sdim if (RegBank.getRegUnit(UnitIdx).Weight > 1) 225249423Sdim RegUnitsHaveUnitWeight = false; 226249423Sdim } 227249423Sdim OS << "/// Get the weight in units of pressure for this register unit.\n" 228249423Sdim << "unsigned " << ClassName << "::\n" 229249423Sdim << "getRegUnitWeight(unsigned RegUnit) const {\n" 230249423Sdim << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 231249423Sdim << " && \"invalid register unit\");\n"; 232249423Sdim if (!RegUnitsHaveUnitWeight) { 233249423Sdim OS << " static const uint8_t RUWeightTable[] = {\n "; 234249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 235249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 236249423Sdim const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 237249423Sdim assert(RU.Weight < 256 && "RegUnit too heavy"); 238249423Sdim OS << RU.Weight << ", "; 239249423Sdim } 240280031Sdim OS << "};\n" 241249423Sdim << " return RUWeightTable[RegUnit];\n"; 242249423Sdim } 243249423Sdim else { 244249423Sdim OS << " // All register units have unit weight.\n" 245249423Sdim << " return 1;\n"; 246249423Sdim } 247249423Sdim OS << "}\n\n"; 248249423Sdim 249234353Sdim OS << "\n" 250234353Sdim << "// Get the number of dimensions of register pressure.\n" 251234353Sdim << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 252234353Sdim << " return " << NumSets << ";\n}\n\n"; 253234353Sdim 254239462Sdim OS << "// Get the name of this register unit pressure set.\n" 255239462Sdim << "const char *" << ClassName << "::\n" 256239462Sdim << "getRegPressureSetName(unsigned Idx) const {\n" 257288943Sdim << " static const char *const PressureNameTable[] = {\n"; 258280031Sdim unsigned MaxRegUnitWeight = 0; 259239462Sdim for (unsigned i = 0; i < NumSets; ++i ) { 260280031Sdim const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 261280031Sdim MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight); 262280031Sdim OS << " \"" << RegUnits.Name << "\",\n"; 263239462Sdim } 264296417Sdim OS << " };\n" 265239462Sdim << " return PressureNameTable[Idx];\n" 266239462Sdim << "}\n\n"; 267239462Sdim 268234353Sdim OS << "// Get the register unit pressure limit for this dimension.\n" 269234353Sdim << "// This limit must be adjusted dynamically for reserved registers.\n" 270234353Sdim << "unsigned " << ClassName << "::\n" 271314564Sdim << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const " 272314564Sdim "{\n" 273314564Sdim << " static const " << getMinimalTypeForRange(MaxRegUnitWeight, 32) 274280031Sdim << " PressureLimitTable[] = {\n"; 275234353Sdim for (unsigned i = 0; i < NumSets; ++i ) { 276261991Sdim const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 277261991Sdim OS << " " << RegUnits.Weight << ", \t// " << i << ": " 278261991Sdim << RegUnits.Name << "\n"; 279234353Sdim } 280280031Sdim OS << " };\n" 281234353Sdim << " return PressureLimitTable[Idx];\n" 282234353Sdim << "}\n\n"; 283234353Sdim 284280031Sdim SequenceToOffsetTable<std::vector<int>> PSetsSeqs; 285280031Sdim 286249423Sdim // This table may be larger than NumRCs if some register units needed a list 287249423Sdim // of unit sets that did not correspond to a register class. 288249423Sdim unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 289280031Sdim std::vector<std::vector<int>> PSets(NumRCUnitSets); 290280031Sdim 291280031Sdim for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) { 292234353Sdim ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 293280031Sdim PSets[i].reserve(PSetIDs.size()); 294234353Sdim for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), 295234353Sdim PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { 296280031Sdim PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order); 297261991Sdim } 298344779Sdim llvm::sort(PSets[i]); 299280031Sdim PSetsSeqs.add(PSets[i]); 300234353Sdim } 301249423Sdim 302280031Sdim PSetsSeqs.layout(); 303280031Sdim 304280031Sdim OS << "/// Table of pressure sets per register class or unit.\n" 305280031Sdim << "static const int RCSetsTable[] = {\n"; 306280031Sdim PSetsSeqs.emit(OS, printInt, "-1"); 307280031Sdim OS << "};\n\n"; 308280031Sdim 309249423Sdim OS << "/// Get the dimensions of register pressure impacted by this " 310249423Sdim << "register class.\n" 311249423Sdim << "/// Returns a -1 terminated array of pressure set IDs\n" 312249423Sdim << "const int* " << ClassName << "::\n" 313249423Sdim << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 314314564Sdim OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 315280031Sdim << " RCSetStartTable[] = {\n "; 316234353Sdim for (unsigned i = 0, e = NumRCs; i != e; ++i) { 317280031Sdim OS << PSetsSeqs.get(PSets[i]) << ","; 318234353Sdim } 319280031Sdim OS << "};\n" 320280031Sdim << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n" 321234353Sdim << "}\n\n"; 322249423Sdim 323249423Sdim OS << "/// Get the dimensions of register pressure impacted by this " 324249423Sdim << "register unit.\n" 325249423Sdim << "/// Returns a -1 terminated array of pressure set IDs\n" 326249423Sdim << "const int* " << ClassName << "::\n" 327249423Sdim << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 328249423Sdim << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 329249423Sdim << " && \"invalid register unit\");\n"; 330314564Sdim OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 331280031Sdim << " RUSetStartTable[] = {\n "; 332249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 333249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 334280031Sdim OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) 335280031Sdim << ","; 336249423Sdim } 337280031Sdim OS << "};\n" 338280031Sdim << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n" 339249423Sdim << "}\n\n"; 340234353Sdim} 341234353Sdim 342344779Sdimusing DwarfRegNumsMapPair = std::pair<Record*, std::vector<int64_t>>; 343344779Sdimusing DwarfRegNumsVecTy = std::vector<DwarfRegNumsMapPair>; 344344779Sdim 345344779Sdimvoid finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) { 346344779Sdim // Sort and unique to get a map-like vector. We want the last assignment to 347344779Sdim // match previous behaviour. 348344779Sdim std::stable_sort(DwarfRegNums.begin(), DwarfRegNums.end(), 349344779Sdim on_first<LessRecordRegister>()); 350344779Sdim // Warn about duplicate assignments. 351344779Sdim const Record *LastSeenReg = nullptr; 352344779Sdim for (const auto &X : DwarfRegNums) { 353344779Sdim const auto &Reg = X.first; 354344779Sdim // The only way LessRecordRegister can return equal is if they're the same 355344779Sdim // string. Use simple equality instead. 356344779Sdim if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) 357344779Sdim PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 358344779Sdim getQualifiedName(Reg) + 359344779Sdim "specified multiple times"); 360344779Sdim LastSeenReg = Reg; 361344779Sdim } 362344779Sdim auto Last = std::unique( 363344779Sdim DwarfRegNums.begin(), DwarfRegNums.end(), 364344779Sdim [](const DwarfRegNumsMapPair &A, const DwarfRegNumsMapPair &B) { 365344779Sdim return A.first->getName() == B.first->getName(); 366344779Sdim }); 367344779Sdim DwarfRegNums.erase(Last, DwarfRegNums.end()); 368344779Sdim} 369344779Sdim 370280031Sdimvoid RegisterInfoEmitter::EmitRegMappingTables( 371280031Sdim raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 372226633Sdim // Collect all information about dwarf register numbers 373344779Sdim DwarfRegNumsVecTy DwarfRegNums; 374226633Sdim 375226633Sdim // First, just pull all provided information to the map 376226633Sdim unsigned maxLength = 0; 377280031Sdim for (auto &RE : Regs) { 378280031Sdim Record *Reg = RE.TheDef; 379226633Sdim std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 380226633Sdim maxLength = std::max((size_t)maxLength, RegNums.size()); 381344779Sdim DwarfRegNums.emplace_back(Reg, std::move(RegNums)); 382226633Sdim } 383344779Sdim finalizeDwarfRegNumsKeys(DwarfRegNums); 384226633Sdim 385226633Sdim if (!maxLength) 386226633Sdim return; 387226633Sdim 388226633Sdim // Now we know maximal length of number list. Append -1's, where needed 389344779Sdim for (DwarfRegNumsVecTy::iterator I = DwarfRegNums.begin(), 390344779Sdim E = DwarfRegNums.end(); 391344779Sdim I != E; ++I) 392226633Sdim for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 393226633Sdim I->second.push_back(-1); 394226633Sdim 395321369Sdim StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 396234353Sdim 397234353Sdim OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 398234353Sdim 399226633Sdim // Emit reverse information about the dwarf register numbers. 400226633Sdim for (unsigned j = 0; j < 2; ++j) { 401234353Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 402234353Sdim OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 403234353Sdim OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 404234353Sdim OS << i << "Dwarf2L[]"; 405234353Sdim 406234353Sdim if (!isCtor) { 407234353Sdim OS << " = {\n"; 408234353Sdim 409234353Sdim // Store the mapping sorted by the LLVM reg num so lookup can be done 410234353Sdim // with a binary search. 411234353Sdim std::map<uint64_t, Record*> Dwarf2LMap; 412344779Sdim for (DwarfRegNumsVecTy::iterator 413234353Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 414234353Sdim int DwarfRegNo = I->second[i]; 415234353Sdim if (DwarfRegNo < 0) 416234353Sdim continue; 417234353Sdim Dwarf2LMap[DwarfRegNo] = I->first; 418234353Sdim } 419234353Sdim 420234353Sdim for (std::map<uint64_t, Record*>::iterator 421234353Sdim I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I) 422234353Sdim OS << " { " << I->first << "U, " << getQualifiedName(I->second) 423234353Sdim << " },\n"; 424234353Sdim 425234353Sdim OS << "};\n"; 426234353Sdim } else { 427234353Sdim OS << ";\n"; 428234353Sdim } 429234353Sdim 430234353Sdim // We have to store the size in a const global, it's used in multiple 431234353Sdim // places. 432234353Sdim OS << "extern const unsigned " << Namespace 433234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize"; 434234353Sdim if (!isCtor) 435280031Sdim OS << " = array_lengthof(" << Namespace 436234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 437280031Sdim << "Dwarf2L);\n\n"; 438234353Sdim else 439234353Sdim OS << ";\n\n"; 440234353Sdim } 441234353Sdim } 442234353Sdim 443280031Sdim for (auto &RE : Regs) { 444280031Sdim Record *Reg = RE.TheDef; 445234353Sdim const RecordVal *V = Reg->getValue("DwarfAlias"); 446234353Sdim if (!V || !V->getValue()) 447234353Sdim continue; 448234353Sdim 449243830Sdim DefInit *DI = cast<DefInit>(V->getValue()); 450234353Sdim Record *Alias = DI->getDef(); 451344779Sdim const auto &AliasIter = 452344779Sdim std::lower_bound(DwarfRegNums.begin(), DwarfRegNums.end(), Alias, 453344779Sdim [](const DwarfRegNumsMapPair &A, const Record *B) { 454344779Sdim return LessRecordRegister()(A.first, B); 455344779Sdim }); 456344779Sdim assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias && 457344779Sdim "Expected Alias to be present in map"); 458344779Sdim const auto &RegIter = 459344779Sdim std::lower_bound(DwarfRegNums.begin(), DwarfRegNums.end(), Reg, 460344779Sdim [](const DwarfRegNumsMapPair &A, const Record *B) { 461344779Sdim return LessRecordRegister()(A.first, B); 462344779Sdim }); 463344779Sdim assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg && 464344779Sdim "Expected Reg to be present in map"); 465344779Sdim RegIter->second = AliasIter->second; 466234353Sdim } 467234353Sdim 468234353Sdim // Emit information about the dwarf register numbers. 469234353Sdim for (unsigned j = 0; j < 2; ++j) { 470234353Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 471234353Sdim OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 472234353Sdim OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 473234353Sdim OS << i << "L2Dwarf[]"; 474234353Sdim if (!isCtor) { 475234353Sdim OS << " = {\n"; 476234353Sdim // Store the mapping sorted by the Dwarf reg num so lookup can be done 477234353Sdim // with a binary search. 478344779Sdim for (DwarfRegNumsVecTy::iterator 479234353Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 480234353Sdim int RegNo = I->second[i]; 481234353Sdim if (RegNo == -1) // -1 is the default value, don't emit a mapping. 482234353Sdim continue; 483234353Sdim 484234353Sdim OS << " { " << getQualifiedName(I->first) << ", " << RegNo 485234353Sdim << "U },\n"; 486234353Sdim } 487234353Sdim OS << "};\n"; 488234353Sdim } else { 489234353Sdim OS << ";\n"; 490234353Sdim } 491234353Sdim 492234353Sdim // We have to store the size in a const global, it's used in multiple 493234353Sdim // places. 494234353Sdim OS << "extern const unsigned " << Namespace 495234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 496234353Sdim if (!isCtor) 497280031Sdim OS << " = array_lengthof(" << Namespace 498280031Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n"; 499234353Sdim else 500234353Sdim OS << ";\n\n"; 501234353Sdim } 502234353Sdim } 503234353Sdim} 504234353Sdim 505280031Sdimvoid RegisterInfoEmitter::EmitRegMapping( 506280031Sdim raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 507234353Sdim // Emit the initializer so the tables from EmitRegMappingTables get wired up 508234353Sdim // to the MCRegisterInfo object. 509234353Sdim unsigned maxLength = 0; 510280031Sdim for (auto &RE : Regs) { 511280031Sdim Record *Reg = RE.TheDef; 512234353Sdim maxLength = std::max((size_t)maxLength, 513234353Sdim Reg->getValueAsListOfInts("DwarfNumbers").size()); 514234353Sdim } 515234353Sdim 516234353Sdim if (!maxLength) 517234353Sdim return; 518234353Sdim 519321369Sdim StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 520234353Sdim 521234353Sdim // Emit reverse information about the dwarf register numbers. 522234353Sdim for (unsigned j = 0; j < 2; ++j) { 523226633Sdim OS << " switch ("; 524226633Sdim if (j == 0) 525226633Sdim OS << "DwarfFlavour"; 526226633Sdim else 527226633Sdim OS << "EHFlavour"; 528226633Sdim OS << ") {\n" 529226633Sdim << " default:\n" 530234353Sdim << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 531226633Sdim 532226633Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 533226633Sdim OS << " case " << i << ":\n"; 534234353Sdim OS << " "; 535234353Sdim if (!isCtor) 536234353Sdim OS << "RI->"; 537234353Sdim std::string Tmp; 538234353Sdim raw_string_ostream(Tmp) << Namespace 539234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 540234353Sdim << "Dwarf2L"; 541234353Sdim OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 542234353Sdim if (j == 0) 543226633Sdim OS << "false"; 544226633Sdim else 545226633Sdim OS << "true"; 546234353Sdim OS << ");\n"; 547226633Sdim OS << " break;\n"; 548226633Sdim } 549226633Sdim OS << " }\n"; 550226633Sdim } 551226633Sdim 552226633Sdim // Emit information about the dwarf register numbers. 553226633Sdim for (unsigned j = 0; j < 2; ++j) { 554226633Sdim OS << " switch ("; 555226633Sdim if (j == 0) 556226633Sdim OS << "DwarfFlavour"; 557226633Sdim else 558226633Sdim OS << "EHFlavour"; 559226633Sdim OS << ") {\n" 560226633Sdim << " default:\n" 561234353Sdim << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 562226633Sdim 563226633Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 564226633Sdim OS << " case " << i << ":\n"; 565234353Sdim OS << " "; 566234353Sdim if (!isCtor) 567234353Sdim OS << "RI->"; 568234353Sdim std::string Tmp; 569234353Sdim raw_string_ostream(Tmp) << Namespace 570234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 571234353Sdim << "L2Dwarf"; 572234353Sdim OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 573234353Sdim if (j == 0) 574226633Sdim OS << "false"; 575226633Sdim else 576226633Sdim OS << "true"; 577234353Sdim OS << ");\n"; 578226633Sdim OS << " break;\n"; 579226633Sdim } 580226633Sdim OS << " }\n"; 581226633Sdim } 582226633Sdim} 583226633Sdim 584226633Sdim// Print a BitVector as a sequence of hex numbers using a little-endian mapping. 585226633Sdim// Width is the number of bits per hex number. 586226633Sdimstatic void printBitVectorAsHex(raw_ostream &OS, 587226633Sdim const BitVector &Bits, 588226633Sdim unsigned Width) { 589226633Sdim assert(Width <= 32 && "Width too large"); 590226633Sdim unsigned Digits = (Width + 3) / 4; 591226633Sdim for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 592226633Sdim unsigned Value = 0; 593226633Sdim for (unsigned j = 0; j != Width && i + j != e; ++j) 594226633Sdim Value |= Bits.test(i + j) << j; 595226633Sdim OS << format("0x%0*x, ", Digits, Value); 596226633Sdim } 597226633Sdim} 598226633Sdim 599226633Sdim// Helper to emit a set of bits into a constant byte array. 600226633Sdimclass BitVectorEmitter { 601226633Sdim BitVector Values; 602226633Sdimpublic: 603226633Sdim void add(unsigned v) { 604226633Sdim if (v >= Values.size()) 605226633Sdim Values.resize(((v/8)+1)*8); // Round up to the next byte. 606226633Sdim Values[v] = true; 607226633Sdim } 608226633Sdim 609226633Sdim void print(raw_ostream &OS) { 610226633Sdim printBitVectorAsHex(OS, Values, 8); 611226633Sdim } 612226633Sdim}; 613226633Sdim 614234353Sdimstatic void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 615234353Sdim OS << getEnumName(VT); 616234353Sdim} 617234353Sdim 618239462Sdimstatic void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 619239462Sdim OS << Idx->EnumValue; 620239462Sdim} 621239462Sdim 622239462Sdim// Differentially encoded register and regunit lists allow for better 623239462Sdim// compression on regular register banks. The sequence is computed from the 624239462Sdim// differential list as: 625224145Sdim// 626239462Sdim// out[0] = InitVal; 627239462Sdim// out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 628239462Sdim// 629239462Sdim// The initial value depends on the specific list. The list is terminated by a 630239462Sdim// 0 differential which means we can't encode repeated elements. 631239462Sdim 632239462Sdimtypedef SmallVector<uint16_t, 4> DiffVec; 633314564Sdimtypedef SmallVector<LaneBitmask, 4> MaskVec; 634239462Sdim 635239462Sdim// Differentially encode a sequence of numbers into V. The starting value and 636239462Sdim// terminating 0 are not added to V, so it will have the same size as List. 637239462Sdimstatic 638288943SdimDiffVec &diffEncode(DiffVec &V, unsigned InitVal, SparseBitVector<> List) { 639239462Sdim assert(V.empty() && "Clear DiffVec before diffEncode."); 640239462Sdim uint16_t Val = uint16_t(InitVal); 641288943Sdim 642288943Sdim for (uint16_t Cur : List) { 643239462Sdim V.push_back(Cur - Val); 644239462Sdim Val = Cur; 645239462Sdim } 646239462Sdim return V; 647239462Sdim} 648239462Sdim 649239462Sdimtemplate<typename Iter> 650239462Sdimstatic 651239462SdimDiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 652239462Sdim assert(V.empty() && "Clear DiffVec before diffEncode."); 653239462Sdim uint16_t Val = uint16_t(InitVal); 654239462Sdim for (Iter I = Begin; I != End; ++I) { 655239462Sdim uint16_t Cur = (*I)->EnumValue; 656239462Sdim V.push_back(Cur - Val); 657239462Sdim Val = Cur; 658239462Sdim } 659239462Sdim return V; 660239462Sdim} 661239462Sdim 662239462Sdimstatic void printDiff16(raw_ostream &OS, uint16_t Val) { 663239462Sdim OS << Val; 664239462Sdim} 665239462Sdim 666314564Sdimstatic void printMask(raw_ostream &OS, LaneBitmask Val) { 667314564Sdim OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; 668280031Sdim} 669280031Sdim 670243830Sdim// Try to combine Idx's compose map into Vec if it is compatible. 671243830Sdim// Return false if it's not possible. 672243830Sdimstatic bool combine(const CodeGenSubRegIndex *Idx, 673243830Sdim SmallVectorImpl<CodeGenSubRegIndex*> &Vec) { 674243830Sdim const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 675288943Sdim for (const auto &I : Map) { 676288943Sdim CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1]; 677288943Sdim if (Entry && Entry != I.second) 678243830Sdim return false; 679243830Sdim } 680243830Sdim 681243830Sdim // All entries are compatible. Make it so. 682288943Sdim for (const auto &I : Map) { 683288943Sdim auto *&Entry = Vec[I.first->EnumValue - 1]; 684288943Sdim assert((!Entry || Entry == I.second) && 685288943Sdim "Expected EnumValue to be unique"); 686288943Sdim Entry = I.second; 687288943Sdim } 688243830Sdim return true; 689243830Sdim} 690243830Sdim 691243830Sdimvoid 692243830SdimRegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 693243830Sdim CodeGenRegBank &RegBank, 694243830Sdim const std::string &ClName) { 695280031Sdim const auto &SubRegIndices = RegBank.getSubRegIndices(); 696243830Sdim OS << "unsigned " << ClName 697243830Sdim << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 698243830Sdim 699243830Sdim // Many sub-register indexes are composition-compatible, meaning that 700243830Sdim // 701243830Sdim // compose(IdxA, IdxB) == compose(IdxA', IdxB) 702243830Sdim // 703243830Sdim // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 704243830Sdim // The illegal entries can be use as wildcards to compress the table further. 705243830Sdim 706243830Sdim // Map each Sub-register index to a compatible table row. 707243830Sdim SmallVector<unsigned, 4> RowMap; 708243830Sdim SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows; 709243830Sdim 710280031Sdim auto SubRegIndicesSize = 711280031Sdim std::distance(SubRegIndices.begin(), SubRegIndices.end()); 712280031Sdim for (const auto &Idx : SubRegIndices) { 713243830Sdim unsigned Found = ~0u; 714243830Sdim for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 715280031Sdim if (combine(&Idx, Rows[r])) { 716243830Sdim Found = r; 717243830Sdim break; 718243830Sdim } 719243830Sdim } 720243830Sdim if (Found == ~0u) { 721243830Sdim Found = Rows.size(); 722243830Sdim Rows.resize(Found + 1); 723280031Sdim Rows.back().resize(SubRegIndicesSize); 724280031Sdim combine(&Idx, Rows.back()); 725243830Sdim } 726243830Sdim RowMap.push_back(Found); 727243830Sdim } 728243830Sdim 729243830Sdim // Output the row map if there is multiple rows. 730243830Sdim if (Rows.size() > 1) { 731314564Sdim OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) 732314564Sdim << " RowMap[" << SubRegIndicesSize << "] = {\n "; 733280031Sdim for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 734243830Sdim OS << RowMap[i] << ", "; 735243830Sdim OS << "\n };\n"; 736243830Sdim } 737243830Sdim 738243830Sdim // Output the rows. 739314564Sdim OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) 740280031Sdim << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n"; 741243830Sdim for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 742243830Sdim OS << " { "; 743280031Sdim for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 744243830Sdim if (Rows[r][i]) 745360784Sdim OS << Rows[r][i]->getQualifiedName() << ", "; 746243830Sdim else 747243830Sdim OS << "0, "; 748243830Sdim OS << "},\n"; 749243830Sdim } 750243830Sdim OS << " };\n\n"; 751243830Sdim 752280031Sdim OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n" 753280031Sdim << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n"; 754243830Sdim if (Rows.size() > 1) 755243830Sdim OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 756243830Sdim else 757243830Sdim OS << " return Rows[0][IdxB];\n"; 758243830Sdim OS << "}\n\n"; 759243830Sdim} 760243830Sdim 761280031Sdimvoid 762280031SdimRegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, 763280031Sdim CodeGenRegBank &RegBank, 764280031Sdim const std::string &ClName) { 765280031Sdim // See the comments in computeSubRegLaneMasks() for our goal here. 766280031Sdim const auto &SubRegIndices = RegBank.getSubRegIndices(); 767280031Sdim 768280031Sdim // Create a list of Mask+Rotate operations, with equivalent entries merged. 769280031Sdim SmallVector<unsigned, 4> SubReg2SequenceIndexMap; 770280031Sdim SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences; 771280031Sdim for (const auto &Idx : SubRegIndices) { 772280031Sdim const SmallVector<MaskRolPair, 1> &IdxSequence 773280031Sdim = Idx.CompositionLaneMaskTransform; 774280031Sdim 775280031Sdim unsigned Found = ~0u; 776280031Sdim unsigned SIdx = 0; 777280031Sdim unsigned NextSIdx; 778280031Sdim for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) { 779280031Sdim SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 780280031Sdim NextSIdx = SIdx + Sequence.size() + 1; 781288943Sdim if (Sequence == IdxSequence) { 782280031Sdim Found = SIdx; 783280031Sdim break; 784280031Sdim } 785280031Sdim } 786280031Sdim if (Found == ~0u) { 787280031Sdim Sequences.push_back(IdxSequence); 788280031Sdim Found = SIdx; 789280031Sdim } 790280031Sdim SubReg2SequenceIndexMap.push_back(Found); 791280031Sdim } 792280031Sdim 793280031Sdim OS << " struct MaskRolOp {\n" 794314564Sdim " LaneBitmask Mask;\n" 795280031Sdim " uint8_t RotateLeft;\n" 796280031Sdim " };\n" 797309124Sdim " static const MaskRolOp LaneMaskComposeSequences[] = {\n"; 798280031Sdim unsigned Idx = 0; 799280031Sdim for (size_t s = 0, se = Sequences.size(); s != se; ++s) { 800280031Sdim OS << " "; 801280031Sdim const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 802280031Sdim for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) { 803280031Sdim const MaskRolPair &P = Sequence[p]; 804314564Sdim printMask(OS << "{ ", P.Mask); 805314564Sdim OS << format(", %2u }, ", P.RotateLeft); 806280031Sdim } 807314564Sdim OS << "{ LaneBitmask::getNone(), 0 }"; 808280031Sdim if (s+1 != se) 809280031Sdim OS << ", "; 810280031Sdim OS << " // Sequence " << Idx << "\n"; 811280031Sdim Idx += Sequence.size() + 1; 812280031Sdim } 813280031Sdim OS << " };\n" 814288943Sdim " static const MaskRolOp *const CompositeSequences[] = {\n"; 815280031Sdim for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { 816280031Sdim OS << " "; 817280031Sdim unsigned Idx = SubReg2SequenceIndexMap[i]; 818309124Sdim OS << format("&LaneMaskComposeSequences[%u]", Idx); 819280031Sdim if (i+1 != e) 820280031Sdim OS << ","; 821280031Sdim OS << " // to " << SubRegIndices[i].getName() << "\n"; 822280031Sdim } 823280031Sdim OS << " };\n\n"; 824280031Sdim 825309124Sdim OS << "LaneBitmask " << ClName 826309124Sdim << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)" 827309124Sdim " const {\n" 828309124Sdim " --IdxA; assert(IdxA < " << SubRegIndices.size() 829280031Sdim << " && \"Subregister index out of bounds\");\n" 830314564Sdim " LaneBitmask Result;\n" 831314564Sdim " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n" 832314564Sdim " LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();\n" 833314564Sdim " if (unsigned S = Ops->RotateLeft)\n" 834314564Sdim " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));\n" 835314564Sdim " else\n" 836314564Sdim " Result |= LaneBitmask(M);\n" 837280031Sdim " }\n" 838280031Sdim " return Result;\n" 839309124Sdim "}\n\n"; 840309124Sdim 841309124Sdim OS << "LaneBitmask " << ClName 842309124Sdim << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, " 843309124Sdim " LaneBitmask LaneMask) const {\n" 844309124Sdim " LaneMask &= getSubRegIndexLaneMask(IdxA);\n" 845309124Sdim " --IdxA; assert(IdxA < " << SubRegIndices.size() 846309124Sdim << " && \"Subregister index out of bounds\");\n" 847314564Sdim " LaneBitmask Result;\n" 848314564Sdim " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n" 849314564Sdim " LaneBitmask::Type M = LaneMask.getAsInteger();\n" 850314564Sdim " if (unsigned S = Ops->RotateLeft)\n" 851314564Sdim " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));\n" 852314564Sdim " else\n" 853314564Sdim " Result |= LaneBitmask(M);\n" 854309124Sdim " }\n" 855309124Sdim " return Result;\n" 856309124Sdim "}\n\n"; 857280031Sdim} 858280031Sdim 859239462Sdim// 860224145Sdim// runMCDesc - Print out MC register descriptions. 861224145Sdim// 862224145Sdimvoid 863224145SdimRegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 864224145Sdim CodeGenRegBank &RegBank) { 865239462Sdim emitSourceFileHeader("MC Register Information", OS); 866224145Sdim 867224145Sdim OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 868309124Sdim OS << "#undef GET_REGINFO_MC_DESC\n\n"; 869224145Sdim 870280031Sdim const auto &Regs = RegBank.getRegisters(); 871224145Sdim 872280031Sdim auto &SubRegIndices = RegBank.getSubRegIndices(); 873261991Sdim // The lists of sub-registers and super-registers go in the same array. That 874261991Sdim // allows us to share suffixes. 875234353Sdim typedef std::vector<const CodeGenRegister*> RegVec; 876224145Sdim 877239462Sdim // Differentially encoded lists. 878239462Sdim SequenceToOffsetTable<DiffVec> DiffSeqs; 879239462Sdim SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 880239462Sdim SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 881239462Sdim SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 882239462Sdim SmallVector<unsigned, 4> RegUnitInitScale(Regs.size()); 883239462Sdim 884280031Sdim // List of lane masks accompanying register unit sequences. 885280031Sdim SequenceToOffsetTable<MaskVec> LaneMaskSeqs; 886280031Sdim SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size()); 887280031Sdim 888239462Sdim // Keep track of sub-register names as well. These are not differentially 889239462Sdim // encoded. 890239462Sdim typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; 891360784Sdim SequenceToOffsetTable<SubRegIdxVec, deref<std::less<>>> SubRegIdxSeqs; 892239462Sdim SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 893239462Sdim 894239462Sdim SequenceToOffsetTable<std::string> RegStrings; 895239462Sdim 896234353Sdim // Precompute register lists for the SequenceToOffsetTable. 897280031Sdim unsigned i = 0; 898280031Sdim for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { 899280031Sdim const auto &Reg = *I; 900280031Sdim RegStrings.add(Reg.getName()); 901224145Sdim 902234353Sdim // Compute the ordered sub-register list. 903234353Sdim SetVector<const CodeGenRegister*> SR; 904280031Sdim Reg.addSubRegsPreOrder(SR, RegBank); 905280031Sdim diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end()); 906239462Sdim DiffSeqs.add(SubRegLists[i]); 907224145Sdim 908239462Sdim // Compute the corresponding sub-register indexes. 909239462Sdim SubRegIdxVec &SRIs = SubRegIdxLists[i]; 910327952Sdim for (const CodeGenRegister *S : SR) 911327952Sdim SRIs.push_back(Reg.getSubRegIndex(S)); 912239462Sdim SubRegIdxSeqs.add(SRIs); 913239462Sdim 914234353Sdim // Super-registers are already computed. 915280031Sdim const RegVec &SuperRegList = Reg.getSuperRegs(); 916280031Sdim diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(), 917280031Sdim SuperRegList.end()); 918239462Sdim DiffSeqs.add(SuperRegLists[i]); 919224145Sdim 920239462Sdim // Differentially encode the register unit list, seeded by register number. 921239462Sdim // First compute a scale factor that allows more diff-lists to be reused: 922239462Sdim // 923239462Sdim // D0 -> (S0, S1) 924239462Sdim // D1 -> (S2, S3) 925239462Sdim // 926239462Sdim // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial 927239462Sdim // value for the differential decoder is the register number multiplied by 928239462Sdim // the scale. 929239462Sdim // 930239462Sdim // Check the neighboring registers for arithmetic progressions. 931239462Sdim unsigned ScaleA = ~0u, ScaleB = ~0u; 932288943Sdim SparseBitVector<> RUs = Reg.getNativeRegUnits(); 933280031Sdim if (I != Regs.begin() && 934288943Sdim std::prev(I)->getNativeRegUnits().count() == RUs.count()) 935288943Sdim ScaleB = *RUs.begin() - *std::prev(I)->getNativeRegUnits().begin(); 936280031Sdim if (std::next(I) != Regs.end() && 937288943Sdim std::next(I)->getNativeRegUnits().count() == RUs.count()) 938288943Sdim ScaleA = *std::next(I)->getNativeRegUnits().begin() - *RUs.begin(); 939239462Sdim unsigned Scale = std::min(ScaleB, ScaleA); 940239462Sdim // Default the scale to 0 if it can't be encoded in 4 bits. 941239462Sdim if (Scale >= 16) 942239462Sdim Scale = 0; 943239462Sdim RegUnitInitScale[i] = Scale; 944280031Sdim DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); 945280031Sdim 946280031Sdim const auto &RUMasks = Reg.getRegUnitLaneMasks(); 947280031Sdim MaskVec &LaneMaskVec = RegUnitLaneMasks[i]; 948280031Sdim assert(LaneMaskVec.empty()); 949280031Sdim LaneMaskVec.insert(LaneMaskVec.begin(), RUMasks.begin(), RUMasks.end()); 950280031Sdim // Terminator mask should not be used inside of the list. 951280031Sdim#ifndef NDEBUG 952314564Sdim for (LaneBitmask M : LaneMaskVec) { 953314564Sdim assert(!M.all() && "terminator mask should not be part of the list"); 954280031Sdim } 955280031Sdim#endif 956280031Sdim LaneMaskSeqs.add(LaneMaskVec); 957224145Sdim } 958224145Sdim 959234353Sdim // Compute the final layout of the sequence table. 960239462Sdim DiffSeqs.layout(); 961280031Sdim LaneMaskSeqs.layout(); 962239462Sdim SubRegIdxSeqs.layout(); 963234353Sdim 964234353Sdim OS << "namespace llvm {\n\n"; 965234353Sdim 966234353Sdim const std::string &TargetName = Target.getName(); 967234353Sdim 968239462Sdim // Emit the shared table of differential lists. 969249423Sdim OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 970239462Sdim DiffSeqs.emit(OS, printDiff16); 971234353Sdim OS << "};\n\n"; 972234353Sdim 973280031Sdim // Emit the shared table of regunit lane mask sequences. 974314564Sdim OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; 975314564Sdim LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); 976280031Sdim OS << "};\n\n"; 977280031Sdim 978239462Sdim // Emit the table of sub-register indexes. 979239462Sdim OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 980239462Sdim SubRegIdxSeqs.emit(OS, printSubRegIndex); 981239462Sdim OS << "};\n\n"; 982239462Sdim 983261991Sdim // Emit the table of sub-register index sizes. 984261991Sdim OS << "extern const MCRegisterInfo::SubRegCoveredBits " 985261991Sdim << TargetName << "SubRegIdxRanges[] = {\n"; 986261991Sdim OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; 987280031Sdim for (const auto &Idx : SubRegIndices) { 988280031Sdim OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " 989280031Sdim << Idx.getName() << "\n"; 990261991Sdim } 991261991Sdim OS << "};\n\n"; 992261991Sdim 993239462Sdim // Emit the string table. 994239462Sdim RegStrings.layout(); 995239462Sdim OS << "extern const char " << TargetName << "RegStrings[] = {\n"; 996239462Sdim RegStrings.emit(OS, printChar); 997239462Sdim OS << "};\n\n"; 998239462Sdim 999234353Sdim OS << "extern const MCRegisterDesc " << TargetName 1000224145Sdim << "RegDesc[] = { // Descriptors\n"; 1001280031Sdim OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 1002224145Sdim 1003234353Sdim // Emit the register descriptors now. 1004280031Sdim i = 0; 1005280031Sdim for (const auto &Reg : Regs) { 1006280031Sdim OS << " { " << RegStrings.get(Reg.getName()) << ", " 1007280031Sdim << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) 1008280031Sdim << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 1009280031Sdim << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " 1010280031Sdim << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n"; 1011280031Sdim ++i; 1012224145Sdim } 1013224145Sdim OS << "};\n\n"; // End of register descriptors... 1014224145Sdim 1015239462Sdim // Emit the table of register unit roots. Each regunit has one or two root 1016239462Sdim // registers. 1017276479Sdim OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; 1018239462Sdim for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 1019239462Sdim ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots(); 1020239462Sdim assert(!Roots.empty() && "All regunits must have a root register."); 1021239462Sdim assert(Roots.size() <= 2 && "More than two roots not supported yet."); 1022239462Sdim OS << " { " << getQualifiedName(Roots.front()->TheDef); 1023239462Sdim for (unsigned r = 1; r != Roots.size(); ++r) 1024239462Sdim OS << ", " << getQualifiedName(Roots[r]->TheDef); 1025239462Sdim OS << " },\n"; 1026239462Sdim } 1027239462Sdim OS << "};\n\n"; 1028239462Sdim 1029280031Sdim const auto &RegisterClasses = RegBank.getRegClasses(); 1030226633Sdim 1031226633Sdim // Loop over all of the register classes... emitting each one. 1032226633Sdim OS << "namespace { // Register classes...\n"; 1033226633Sdim 1034280031Sdim SequenceToOffsetTable<std::string> RegClassStrings; 1035280031Sdim 1036226633Sdim // Emit the register enum value arrays for each RegisterClass 1037280031Sdim for (const auto &RC : RegisterClasses) { 1038226633Sdim ArrayRef<Record*> Order = RC.getOrder(); 1039226633Sdim 1040226633Sdim // Give the register class a legal C name if it's anonymous. 1041309124Sdim const std::string &Name = RC.getName(); 1042226633Sdim 1043280031Sdim RegClassStrings.add(Name); 1044280031Sdim 1045226633Sdim // Emit the register list now. 1046226633Sdim OS << " // " << Name << " Register Class...\n" 1047276479Sdim << " const MCPhysReg " << Name 1048226633Sdim << "[] = {\n "; 1049327952Sdim for (Record *Reg : Order) { 1050226633Sdim OS << getQualifiedName(Reg) << ", "; 1051226633Sdim } 1052226633Sdim OS << "\n };\n\n"; 1053226633Sdim 1054226633Sdim OS << " // " << Name << " Bit set.\n" 1055234353Sdim << " const uint8_t " << Name 1056226633Sdim << "Bits[] = {\n "; 1057226633Sdim BitVectorEmitter BVE; 1058327952Sdim for (Record *Reg : Order) { 1059226633Sdim BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 1060226633Sdim } 1061226633Sdim BVE.print(OS); 1062226633Sdim OS << "\n };\n\n"; 1063226633Sdim 1064226633Sdim } 1065309124Sdim OS << "} // end anonymous namespace\n\n"; 1066226633Sdim 1067280031Sdim RegClassStrings.layout(); 1068280031Sdim OS << "extern const char " << TargetName << "RegClassStrings[] = {\n"; 1069280031Sdim RegClassStrings.emit(OS, printChar); 1070280031Sdim OS << "};\n\n"; 1071280031Sdim 1072234353Sdim OS << "extern const MCRegisterClass " << TargetName 1073234353Sdim << "MCRegisterClasses[] = {\n"; 1074226633Sdim 1075280031Sdim for (const auto &RC : RegisterClasses) { 1076321369Sdim assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); 1077280031Sdim OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " 1078280031Sdim << RegClassStrings.get(RC.getName()) << ", " 1079234353Sdim << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " 1080234353Sdim << RC.getQualifiedName() + "RegClassID" << ", " 1081226633Sdim << RC.CopyCost << ", " 1082309124Sdim << ( RC.Allocatable ? "true" : "false" ) << " },\n"; 1083226633Sdim } 1084226633Sdim 1085226633Sdim OS << "};\n\n"; 1086226633Sdim 1087239462Sdim EmitRegMappingTables(OS, Regs, false); 1088239462Sdim 1089239462Sdim // Emit Reg encoding table 1090239462Sdim OS << "extern const uint16_t " << TargetName; 1091239462Sdim OS << "RegEncodingTable[] = {\n"; 1092239462Sdim // Add entry for NoRegister 1093239462Sdim OS << " 0,\n"; 1094280031Sdim for (const auto &RE : Regs) { 1095280031Sdim Record *Reg = RE.TheDef; 1096239462Sdim BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 1097239462Sdim uint64_t Value = 0; 1098239462Sdim for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 1099243830Sdim if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 1100276479Sdim Value |= (uint64_t)B->getValue() << b; 1101234353Sdim } 1102239462Sdim OS << " " << Value << ",\n"; 1103234353Sdim } 1104239462Sdim OS << "};\n"; // End of HW encoding table 1105234353Sdim 1106224145Sdim // MCRegisterInfo initialization routine. 1107224145Sdim OS << "static inline void Init" << TargetName 1108226633Sdim << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 1109280031Sdim << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) " 1110280031Sdim "{\n" 1111239462Sdim << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 1112280031Sdim << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 1113280031Sdim << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " 1114280031Sdim << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " 1115280031Sdim << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, " 1116280031Sdim << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, " 1117280031Sdim << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n" 1118280031Sdim << TargetName << "SubRegIdxRanges, " << TargetName 1119280031Sdim << "RegEncodingTable);\n\n"; 1120224145Sdim 1121226633Sdim EmitRegMapping(OS, Regs, false); 1122226633Sdim 1123226633Sdim OS << "}\n\n"; 1124226633Sdim 1125309124Sdim OS << "} // end namespace llvm\n\n"; 1126224145Sdim OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 1127224145Sdim} 1128224145Sdim 1129224145Sdimvoid 1130224145SdimRegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 1131224145Sdim CodeGenRegBank &RegBank) { 1132239462Sdim emitSourceFileHeader("Register Information Header Fragment", OS); 1133224145Sdim 1134224145Sdim OS << "\n#ifdef GET_REGINFO_HEADER\n"; 1135309124Sdim OS << "#undef GET_REGINFO_HEADER\n\n"; 1136224145Sdim 1137193323Sed const std::string &TargetName = Target.getName(); 1138193323Sed std::string ClassName = TargetName + "GenRegisterInfo"; 1139193323Sed 1140327952Sdim OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; 1141193323Sed 1142193323Sed OS << "namespace llvm {\n\n"; 1143193323Sed 1144288943Sdim OS << "class " << TargetName << "FrameLowering;\n\n"; 1145288943Sdim 1146193323Sed OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 1147226633Sdim << " explicit " << ClassName 1148327952Sdim << "(unsigned RA, unsigned D = 0, unsigned E = 0,\n" 1149327952Sdim << " unsigned PC = 0, unsigned HwMode = 0);\n"; 1150239462Sdim if (!RegBank.getSubRegIndices().empty()) { 1151276479Sdim OS << " unsigned composeSubRegIndicesImpl" 1152276479Sdim << "(unsigned, unsigned) const override;\n" 1153309124Sdim << " LaneBitmask composeSubRegIndexLaneMaskImpl" 1154309124Sdim << "(unsigned, LaneBitmask) const override;\n" 1155309124Sdim << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl" 1156309124Sdim << "(unsigned, LaneBitmask) const override;\n" 1157276479Sdim << " const TargetRegisterClass *getSubClassWithSubReg" 1158276479Sdim << "(const TargetRegisterClass*, unsigned) const override;\n"; 1159239462Sdim } 1160276479Sdim OS << " const RegClassWeight &getRegClassWeight(" 1161276479Sdim << "const TargetRegisterClass *RC) const override;\n" 1162276479Sdim << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n" 1163276479Sdim << " unsigned getNumRegPressureSets() const override;\n" 1164276479Sdim << " const char *getRegPressureSetName(unsigned Idx) const override;\n" 1165288943Sdim << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned " 1166288943Sdim "Idx) const override;\n" 1167276479Sdim << " const int *getRegClassPressureSets(" 1168276479Sdim << "const TargetRegisterClass *RC) const override;\n" 1169276479Sdim << " const int *getRegUnitPressureSets(" 1170276479Sdim << "unsigned RegUnit) const override;\n" 1171288943Sdim << " ArrayRef<const char *> getRegMaskNames() const override;\n" 1172288943Sdim << " ArrayRef<const uint32_t *> getRegMasks() const override;\n" 1173288943Sdim << " /// Devirtualized TargetFrameLowering.\n" 1174288943Sdim << " static const " << TargetName << "FrameLowering *getFrameLowering(\n" 1175288943Sdim << " const MachineFunction &MF);\n" 1176193323Sed << "};\n\n"; 1177193323Sed 1178280031Sdim const auto &RegisterClasses = RegBank.getRegClasses(); 1179193323Sed 1180193323Sed if (!RegisterClasses.empty()) { 1181280031Sdim OS << "namespace " << RegisterClasses.front().Namespace 1182193323Sed << " { // Register classes\n"; 1183221345Sdim 1184280031Sdim for (const auto &RC : RegisterClasses) { 1185224145Sdim const std::string &Name = RC.getName(); 1186193323Sed 1187193323Sed // Output the extern for the instance. 1188234353Sdim OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 1189193323Sed } 1190309124Sdim OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; 1191193323Sed } 1192309124Sdim OS << "} // end namespace llvm\n\n"; 1193224145Sdim OS << "#endif // GET_REGINFO_HEADER\n\n"; 1194193323Sed} 1195193323Sed 1196224145Sdim// 1197224145Sdim// runTargetDesc - Output the target register and register file descriptions. 1198224145Sdim// 1199224145Sdimvoid 1200224145SdimRegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 1201224145Sdim CodeGenRegBank &RegBank){ 1202239462Sdim emitSourceFileHeader("Target Register and Register Classes Information", OS); 1203193323Sed 1204224145Sdim OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1205309124Sdim OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; 1206193323Sed 1207193323Sed OS << "namespace llvm {\n\n"; 1208193323Sed 1209226633Sdim // Get access to MCRegisterClass data. 1210234353Sdim OS << "extern const MCRegisterClass " << Target.getName() 1211234353Sdim << "MCRegisterClasses[];\n"; 1212226633Sdim 1213223017Sdim // Start out by emitting each of the register classes. 1214280031Sdim const auto &RegisterClasses = RegBank.getRegClasses(); 1215280031Sdim const auto &SubRegIndices = RegBank.getSubRegIndices(); 1216193323Sed 1217223017Sdim // Collect all registers belonging to any allocatable class. 1218223017Sdim std::set<Record*> AllocatableRegs; 1219223017Sdim 1220226633Sdim // Collect allocatable registers. 1221280031Sdim for (const auto &RC : RegisterClasses) { 1222224145Sdim ArrayRef<Record*> Order = RC.getOrder(); 1223193323Sed 1224223017Sdim if (RC.Allocatable) 1225224145Sdim AllocatableRegs.insert(Order.begin(), Order.end()); 1226226633Sdim } 1227223017Sdim 1228327952Sdim const CodeGenHwModes &CGH = Target.getHwModes(); 1229327952Sdim unsigned NumModes = CGH.getNumModeIds(); 1230327952Sdim 1231234353Sdim // Build a shared array of value types. 1232327952Sdim SequenceToOffsetTable<std::vector<MVT::SimpleValueType>> VTSeqs; 1233327952Sdim for (unsigned M = 0; M < NumModes; ++M) { 1234327952Sdim for (const auto &RC : RegisterClasses) { 1235327952Sdim std::vector<MVT::SimpleValueType> S; 1236327952Sdim for (const ValueTypeByHwMode &VVT : RC.VTs) 1237327952Sdim S.push_back(VVT.get(M).SimpleTy); 1238327952Sdim VTSeqs.add(S); 1239327952Sdim } 1240327952Sdim } 1241234353Sdim VTSeqs.layout(); 1242234353Sdim OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1243234353Sdim VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 1244234353Sdim OS << "};\n"; 1245221345Sdim 1246243830Sdim // Emit SubRegIndex names, skipping 0. 1247243830Sdim OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; 1248280031Sdim 1249280031Sdim for (const auto &Idx : SubRegIndices) { 1250280031Sdim OS << Idx.getName(); 1251280031Sdim OS << "\", \""; 1252239462Sdim } 1253239462Sdim OS << "\" };\n\n"; 1254239462Sdim 1255243830Sdim // Emit SubRegIndex lane masks, including 0. 1256321369Sdim OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " 1257321369Sdim "LaneBitmask::getAll(),\n"; 1258280031Sdim for (const auto &Idx : SubRegIndices) { 1259314564Sdim printMask(OS << " ", Idx.LaneMask); 1260314564Sdim OS << ", // " << Idx.getName() << '\n'; 1261243830Sdim } 1262243830Sdim OS << " };\n\n"; 1263243830Sdim 1264239462Sdim OS << "\n"; 1265239462Sdim 1266193323Sed // Now that all of the structs have been emitted, emit the instances. 1267193323Sed if (!RegisterClasses.empty()) { 1268327952Sdim OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" 1269327952Sdim << " = {\n"; 1270327952Sdim for (unsigned M = 0; M < NumModes; ++M) { 1271327952Sdim unsigned EV = 0; 1272327952Sdim OS << " // Mode = " << M << " ("; 1273327952Sdim if (M == 0) 1274327952Sdim OS << "Default"; 1275327952Sdim else 1276327952Sdim OS << CGH.getMode(M).Name; 1277327952Sdim OS << ")\n"; 1278327952Sdim for (const auto &RC : RegisterClasses) { 1279327952Sdim assert(RC.EnumValue == EV++ && "Unexpected order of register classes"); 1280327952Sdim (void)EV; 1281327952Sdim const RegSizeInfo &RI = RC.RSI.get(M); 1282327952Sdim OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " 1283327952Sdim << RI.SpillAlignment; 1284327952Sdim std::vector<MVT::SimpleValueType> VTs; 1285327952Sdim for (const ValueTypeByHwMode &VVT : RC.VTs) 1286327952Sdim VTs.push_back(VVT.get(M).SimpleTy); 1287327952Sdim OS << ", VTLists+" << VTSeqs.get(VTs) << " }, // " 1288327952Sdim << RC.getName() << '\n'; 1289327952Sdim } 1290327952Sdim } 1291327952Sdim OS << "};\n"; 1292327952Sdim 1293327952Sdim 1294234353Sdim OS << "\nstatic const TargetRegisterClass *const " 1295276479Sdim << "NullRegClasses[] = { nullptr };\n\n"; 1296226633Sdim 1297239462Sdim // Emit register class bit mask tables. The first bit mask emitted for a 1298239462Sdim // register class, RC, is the set of sub-classes, including RC itself. 1299239462Sdim // 1300239462Sdim // If RC has super-registers, also create a list of subreg indices and bit 1301239462Sdim // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1302239462Sdim // SuperRC, that satisfies: 1303239462Sdim // 1304239462Sdim // For all SuperReg in SuperRC: SuperReg:Idx in RC 1305239462Sdim // 1306239462Sdim // The 0-terminated list of subreg indices starts at: 1307239462Sdim // 1308239462Sdim // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1309239462Sdim // 1310239462Sdim // The corresponding bitmasks follow the sub-class mask in memory. Each 1311239462Sdim // mask has RCMaskWords uint32_t entries. 1312239462Sdim // 1313239462Sdim // Every bit mask present in the list has at least one bit set. 1314193323Sed 1315239462Sdim // Compress the sub-reg index lists. 1316239462Sdim typedef std::vector<const CodeGenSubRegIndex*> IdxList; 1317239462Sdim SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1318360784Sdim SequenceToOffsetTable<IdxList, deref<std::less<>>> SuperRegIdxSeqs; 1319239462Sdim BitVector MaskBV(RegisterClasses.size()); 1320193323Sed 1321280031Sdim for (const auto &RC : RegisterClasses) { 1322321369Sdim OS << "static const uint32_t " << RC.getName() 1323321369Sdim << "SubClassMask[] = {\n "; 1324239462Sdim printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1325193323Sed 1326239462Sdim // Emit super-reg class masks for any relevant SubRegIndices that can 1327239462Sdim // project into RC. 1328280031Sdim IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; 1329280031Sdim for (auto &Idx : SubRegIndices) { 1330239462Sdim MaskBV.reset(); 1331280031Sdim RC.getSuperRegClasses(&Idx, MaskBV); 1332239462Sdim if (MaskBV.none()) 1333239462Sdim continue; 1334280031Sdim SRIList.push_back(&Idx); 1335239462Sdim OS << "\n "; 1336239462Sdim printBitVectorAsHex(OS, MaskBV, 32); 1337280031Sdim OS << "// " << Idx.getName(); 1338239462Sdim } 1339239462Sdim SuperRegIdxSeqs.add(SRIList); 1340234353Sdim OS << "\n};\n\n"; 1341193323Sed } 1342193323Sed 1343239462Sdim OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1344239462Sdim SuperRegIdxSeqs.layout(); 1345239462Sdim SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1346239462Sdim OS << "};\n\n"; 1347239462Sdim 1348226633Sdim // Emit NULL terminated super-class lists. 1349280031Sdim for (const auto &RC : RegisterClasses) { 1350226633Sdim ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 1351193323Sed 1352226633Sdim // Skip classes without supers. We can reuse NullRegClasses. 1353226633Sdim if (Supers.empty()) 1354226633Sdim continue; 1355193323Sed 1356234353Sdim OS << "static const TargetRegisterClass *const " 1357226633Sdim << RC.getName() << "Superclasses[] = {\n"; 1358280031Sdim for (const auto *Super : Supers) 1359280031Sdim OS << " &" << Super->getQualifiedName() << "RegClass,\n"; 1360276479Sdim OS << " nullptr\n};\n\n"; 1361193323Sed } 1362193323Sed 1363224145Sdim // Emit methods. 1364280031Sdim for (const auto &RC : RegisterClasses) { 1365224145Sdim if (!RC.AltOrderSelect.empty()) { 1366224145Sdim OS << "\nstatic inline unsigned " << RC.getName() 1367224145Sdim << "AltOrderSelect(const MachineFunction &MF) {" 1368234353Sdim << RC.AltOrderSelect << "}\n\n" 1369249423Sdim << "static ArrayRef<MCPhysReg> " << RC.getName() 1370234353Sdim << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1371224145Sdim for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 1372224145Sdim ArrayRef<Record*> Elems = RC.getOrder(oi); 1373234353Sdim if (!Elems.empty()) { 1374249423Sdim OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1375234353Sdim for (unsigned elem = 0; elem != Elems.size(); ++elem) 1376234353Sdim OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1377234353Sdim OS << " };\n"; 1378234353Sdim } 1379224145Sdim } 1380226633Sdim OS << " const MCRegisterClass &MCR = " << Target.getName() 1381234353Sdim << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1382249423Sdim << " const ArrayRef<MCPhysReg> Order[] = {\n" 1383226633Sdim << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 1384224145Sdim for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1385234353Sdim if (RC.getOrder(oi).empty()) 1386249423Sdim OS << "),\n ArrayRef<MCPhysReg>("; 1387234353Sdim else 1388234353Sdim OS << "),\n makeArrayRef(AltOrder" << oi; 1389224145Sdim OS << ")\n };\n const unsigned Select = " << RC.getName() 1390224145Sdim << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1391224145Sdim << ");\n return Order[Select];\n}\n"; 1392280031Sdim } 1393193323Sed } 1394221345Sdim 1395234353Sdim // Now emit the actual value-initialized register class instances. 1396280031Sdim OS << "\nnamespace " << RegisterClasses.front().Namespace 1397234353Sdim << " { // Register class instances\n"; 1398234353Sdim 1399280031Sdim for (const auto &RC : RegisterClasses) { 1400280031Sdim OS << " extern const TargetRegisterClass " << RC.getName() 1401280031Sdim << "RegClass = {\n " << '&' << Target.getName() 1402280031Sdim << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " 1403327952Sdim << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1404314564Sdim << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "; 1405314564Sdim printMask(OS, RC.LaneMask); 1406314564Sdim OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " 1407288943Sdim << (RC.HasDisjunctSubRegs?"true":"false") 1408309124Sdim << ", /* HasDisjunctSubRegs */\n " 1409309124Sdim << (RC.CoveredBySubRegs?"true":"false") 1410309124Sdim << ", /* CoveredBySubRegs */\n "; 1411234353Sdim if (RC.getSuperClasses().empty()) 1412234353Sdim OS << "NullRegClasses,\n "; 1413234353Sdim else 1414234353Sdim OS << RC.getName() << "Superclasses,\n "; 1415234353Sdim if (RC.AltOrderSelect.empty()) 1416276479Sdim OS << "nullptr\n"; 1417234353Sdim else 1418234353Sdim OS << RC.getName() << "GetRawAllocationOrder\n"; 1419234353Sdim OS << " };\n\n"; 1420234353Sdim } 1421234353Sdim 1422309124Sdim OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; 1423193323Sed } 1424193323Sed 1425193323Sed OS << "\nnamespace {\n"; 1426193323Sed OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 1427280031Sdim for (const auto &RC : RegisterClasses) 1428280031Sdim OS << " &" << RC.getQualifiedName() << "RegClass,\n"; 1429193323Sed OS << " };\n"; 1430309124Sdim OS << "} // end anonymous namespace\n"; 1431193323Sed 1432224145Sdim // Emit extra information about registers. 1433224145Sdim const std::string &TargetName = Target.getName(); 1434234353Sdim OS << "\nstatic const TargetRegisterInfoDesc " 1435234353Sdim << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n"; 1436309124Sdim OS << " { 0, false },\n"; 1437221345Sdim 1438280031Sdim const auto &Regs = RegBank.getRegisters(); 1439280031Sdim for (const auto &Reg : Regs) { 1440234353Sdim OS << " { "; 1441224145Sdim OS << Reg.CostPerUse << ", " 1442309124Sdim << ( AllocatableRegs.count(Reg.TheDef) != 0 ? "true" : "false" ) 1443309124Sdim << " },\n"; 1444193323Sed } 1445234353Sdim OS << "};\n"; // End of register descriptors... 1446208599Srdivacky 1447224145Sdim 1448314564Sdim std::string ClassName = Target.getName().str() + "GenRegisterInfo"; 1449193323Sed 1450280031Sdim auto SubRegIndicesSize = 1451280031Sdim std::distance(SubRegIndices.begin(), SubRegIndices.end()); 1452280031Sdim 1453280031Sdim if (!SubRegIndices.empty()) { 1454243830Sdim emitComposeSubRegIndices(OS, RegBank, ClassName); 1455280031Sdim emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); 1456280031Sdim } 1457210299Sed 1458226633Sdim // Emit getSubClassWithSubReg. 1459239462Sdim if (!SubRegIndices.empty()) { 1460239462Sdim OS << "const TargetRegisterClass *" << ClassName 1461239462Sdim << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1462239462Sdim << " const {\n"; 1463226633Sdim // Use the smallest type that can hold a regclass ID with room for a 1464226633Sdim // sentinel. 1465226633Sdim if (RegisterClasses.size() < UINT8_MAX) 1466226633Sdim OS << " static const uint8_t Table["; 1467226633Sdim else if (RegisterClasses.size() < UINT16_MAX) 1468226633Sdim OS << " static const uint16_t Table["; 1469226633Sdim else 1470243830Sdim PrintFatalError("Too many register classes."); 1471280031Sdim OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1472280031Sdim for (const auto &RC : RegisterClasses) { 1473226633Sdim OS << " {\t// " << RC.getName() << "\n"; 1474280031Sdim for (auto &Idx : SubRegIndices) { 1475280031Sdim if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) 1476280031Sdim OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() 1477226633Sdim << " -> " << SRC->getName() << "\n"; 1478226633Sdim else 1479280031Sdim OS << " 0,\t// " << Idx.getName() << "\n"; 1480226633Sdim } 1481226633Sdim OS << " },\n"; 1482226633Sdim } 1483226633Sdim OS << " };\n assert(RC && \"Missing regclass\");\n" 1484226633Sdim << " if (!Idx) return RC;\n --Idx;\n" 1485280031Sdim << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1486226633Sdim << " unsigned TV = Table[RC->getID()][Idx];\n" 1487276479Sdim << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1488226633Sdim } 1489226633Sdim 1490234353Sdim EmitRegUnitPressure(OS, RegBank, ClassName); 1491234353Sdim 1492193323Sed // Emit the constructor of the class... 1493234353Sdim OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1494249423Sdim OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; 1495314564Sdim OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; 1496239462Sdim OS << "extern const char " << TargetName << "RegStrings[];\n"; 1497280031Sdim OS << "extern const char " << TargetName << "RegClassStrings[];\n"; 1498276479Sdim OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; 1499239462Sdim OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1500261991Sdim OS << "extern const MCRegisterInfo::SubRegCoveredBits " 1501261991Sdim << TargetName << "SubRegIdxRanges[];\n"; 1502239462Sdim OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1503224145Sdim 1504234353Sdim EmitRegMappingTables(OS, Regs, true); 1505234353Sdim 1506234353Sdim OS << ClassName << "::\n" << ClassName 1507327952Sdim << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,\n" 1508327952Sdim " unsigned PC, unsigned HwMode)\n" 1509224145Sdim << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" 1510327952Sdim << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n" 1511327952Sdim << " SubRegIndexNameTable, SubRegIndexLaneMaskTable,\n" 1512327952Sdim << " "; 1513314564Sdim printMask(OS, RegBank.CoveringLanes); 1514327952Sdim OS << ", RegClassInfos, HwMode) {\n" 1515280031Sdim << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1 1516280031Sdim << ", RA, PC,\n " << TargetName 1517234353Sdim << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1518239462Sdim << " " << TargetName << "RegUnitRoots,\n" 1519239462Sdim << " " << RegBank.getNumNativeRegUnits() << ",\n" 1520239462Sdim << " " << TargetName << "RegDiffLists,\n" 1521280031Sdim << " " << TargetName << "LaneMaskLists,\n" 1522239462Sdim << " " << TargetName << "RegStrings,\n" 1523280031Sdim << " " << TargetName << "RegClassStrings,\n" 1524239462Sdim << " " << TargetName << "SubRegIdxLists,\n" 1525280031Sdim << " " << SubRegIndicesSize + 1 << ",\n" 1526261991Sdim << " " << TargetName << "SubRegIdxRanges,\n" 1527239462Sdim << " " << TargetName << "RegEncodingTable);\n\n"; 1528193323Sed 1529226633Sdim EmitRegMapping(OS, Regs, true); 1530193323Sed 1531226633Sdim OS << "}\n\n"; 1532193323Sed 1533234353Sdim // Emit CalleeSavedRegs information. 1534234353Sdim std::vector<Record*> CSRSets = 1535234353Sdim Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1536234353Sdim for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { 1537234353Sdim Record *CSRSet = CSRSets[i]; 1538234353Sdim const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1539234353Sdim assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1540234353Sdim 1541234353Sdim // Emit the *_SaveList list of callee-saved registers. 1542249423Sdim OS << "static const MCPhysReg " << CSRSet->getName() 1543234353Sdim << "_SaveList[] = { "; 1544234353Sdim for (unsigned r = 0, re = Regs->size(); r != re; ++r) 1545234353Sdim OS << getQualifiedName((*Regs)[r]) << ", "; 1546234353Sdim OS << "0 };\n"; 1547234353Sdim 1548234353Sdim // Emit the *_RegMask bit mask of call-preserved registers. 1549261991Sdim BitVector Covered = RegBank.computeCoveredRegisters(*Regs); 1550261991Sdim 1551261991Sdim // Check for an optional OtherPreserved set. 1552261991Sdim // Add those registers to RegMask, but not to SaveList. 1553261991Sdim if (DagInit *OPDag = 1554261991Sdim dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { 1555261991Sdim SetTheory::RecSet OPSet; 1556261991Sdim RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); 1557261991Sdim Covered |= RegBank.computeCoveredRegisters( 1558261991Sdim ArrayRef<Record*>(OPSet.begin(), OPSet.end())); 1559261991Sdim } 1560261991Sdim 1561234353Sdim OS << "static const uint32_t " << CSRSet->getName() 1562234353Sdim << "_RegMask[] = { "; 1563261991Sdim printBitVectorAsHex(OS, Covered, 32); 1564234353Sdim OS << "};\n"; 1565234353Sdim } 1566234353Sdim OS << "\n\n"; 1567234353Sdim 1568288943Sdim OS << "ArrayRef<const uint32_t *> " << ClassName 1569288943Sdim << "::getRegMasks() const {\n"; 1570296417Sdim if (!CSRSets.empty()) { 1571296417Sdim OS << " static const uint32_t *const Masks[] = {\n"; 1572296417Sdim for (Record *CSRSet : CSRSets) 1573296417Sdim OS << " " << CSRSet->getName() << "_RegMask,\n"; 1574296417Sdim OS << " };\n"; 1575296417Sdim OS << " return makeArrayRef(Masks);\n"; 1576296417Sdim } else { 1577296417Sdim OS << " return None;\n"; 1578296417Sdim } 1579288943Sdim OS << "}\n\n"; 1580288943Sdim 1581288943Sdim OS << "ArrayRef<const char *> " << ClassName 1582288943Sdim << "::getRegMaskNames() const {\n"; 1583296417Sdim if (!CSRSets.empty()) { 1584296417Sdim OS << " static const char *const Names[] = {\n"; 1585296417Sdim for (Record *CSRSet : CSRSets) 1586296417Sdim OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; 1587296417Sdim OS << " };\n"; 1588296417Sdim OS << " return makeArrayRef(Names);\n"; 1589296417Sdim } else { 1590296417Sdim OS << " return None;\n"; 1591296417Sdim } 1592288943Sdim OS << "}\n\n"; 1593288943Sdim 1594296417Sdim OS << "const " << TargetName << "FrameLowering *\n" << TargetName 1595296417Sdim << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n" 1596288943Sdim << " return static_cast<const " << TargetName << "FrameLowering *>(\n" 1597288943Sdim << " MF.getSubtarget().getFrameLowering());\n" 1598288943Sdim << "}\n\n"; 1599288943Sdim 1600309124Sdim OS << "} // end namespace llvm\n\n"; 1601224145Sdim OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1602193323Sed} 1603224145Sdim 1604224145Sdimvoid RegisterInfoEmitter::run(raw_ostream &OS) { 1605224145Sdim CodeGenRegBank &RegBank = Target.getRegBank(); 1606224145Sdim runEnums(OS, Target, RegBank); 1607224145Sdim runMCDesc(OS, Target, RegBank); 1608224145Sdim runTargetHeader(OS, Target, RegBank); 1609224145Sdim runTargetDesc(OS, Target, RegBank); 1610327952Sdim 1611327952Sdim if (RegisterInfoDebug) 1612327952Sdim debugDump(errs()); 1613224145Sdim} 1614239462Sdim 1615327952Sdimvoid RegisterInfoEmitter::debugDump(raw_ostream &OS) { 1616327952Sdim CodeGenRegBank &RegBank = Target.getRegBank(); 1617327952Sdim const CodeGenHwModes &CGH = Target.getHwModes(); 1618327952Sdim unsigned NumModes = CGH.getNumModeIds(); 1619327952Sdim auto getModeName = [CGH] (unsigned M) -> StringRef { 1620327952Sdim if (M == 0) 1621327952Sdim return "Default"; 1622327952Sdim return CGH.getMode(M).Name; 1623327952Sdim }; 1624327952Sdim 1625327952Sdim for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { 1626327952Sdim OS << "RegisterClass " << RC.getName() << ":\n"; 1627327952Sdim OS << "\tSpillSize: {"; 1628327952Sdim for (unsigned M = 0; M != NumModes; ++M) 1629327952Sdim OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; 1630327952Sdim OS << " }\n\tSpillAlignment: {"; 1631327952Sdim for (unsigned M = 0; M != NumModes; ++M) 1632327952Sdim OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; 1633327952Sdim OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; 1634327952Sdim OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; 1635327952Sdim OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; 1636327952Sdim OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; 1637327952Sdim OS << "\tRegs:"; 1638327952Sdim for (const CodeGenRegister *R : RC.getMembers()) { 1639327952Sdim OS << " " << R->getName(); 1640327952Sdim } 1641327952Sdim OS << '\n'; 1642327952Sdim OS << "\tSubClasses:"; 1643327952Sdim const BitVector &SubClasses = RC.getSubClasses(); 1644327952Sdim for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { 1645327952Sdim if (!SubClasses.test(SRC.EnumValue)) 1646327952Sdim continue; 1647327952Sdim OS << " " << SRC.getName(); 1648327952Sdim } 1649327952Sdim OS << '\n'; 1650327952Sdim OS << "\tSuperClasses:"; 1651327952Sdim for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) { 1652327952Sdim OS << " " << SRC->getName(); 1653327952Sdim } 1654327952Sdim OS << '\n'; 1655327952Sdim } 1656327952Sdim 1657327952Sdim for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { 1658327952Sdim OS << "SubRegIndex " << SRI.getName() << ":\n"; 1659327952Sdim OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; 1660327952Sdim OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; 1661327952Sdim } 1662327952Sdim 1663327952Sdim for (const CodeGenRegister &R : RegBank.getRegisters()) { 1664327952Sdim OS << "Register " << R.getName() << ":\n"; 1665327952Sdim OS << "\tCostPerUse: " << R.CostPerUse << '\n'; 1666327952Sdim OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; 1667327952Sdim OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; 1668327952Sdim for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : R.getSubRegs()) { 1669327952Sdim OS << "\tSubReg " << P.first->getName() 1670327952Sdim << " = " << P.second->getName() << '\n'; 1671327952Sdim } 1672327952Sdim } 1673327952Sdim} 1674327952Sdim 1675239462Sdimnamespace llvm { 1676239462Sdim 1677239462Sdimvoid EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { 1678239462Sdim RegisterInfoEmitter(RK).run(OS); 1679239462Sdim} 1680239462Sdim 1681309124Sdim} // end namespace llvm 1682