1283625Sdim//===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===// 2283625Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6283625Sdim// 7283625Sdim//===----------------------------------------------------------------------===// 8283625Sdim// 9283625Sdim// This file defines the interfaces that BPF uses to lower LLVM code into a 10283625Sdim// selection DAG. 11283625Sdim// 12283625Sdim//===----------------------------------------------------------------------===// 13283625Sdim 14283625Sdim#include "BPFISelLowering.h" 15283625Sdim#include "BPF.h" 16309124Sdim#include "BPFSubtarget.h" 17283625Sdim#include "BPFTargetMachine.h" 18283625Sdim#include "llvm/CodeGen/CallingConvLower.h" 19283625Sdim#include "llvm/CodeGen/MachineFrameInfo.h" 20283625Sdim#include "llvm/CodeGen/MachineFunction.h" 21283625Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 22283625Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 23283625Sdim#include "llvm/CodeGen/SelectionDAGISel.h" 24283625Sdim#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 25283625Sdim#include "llvm/CodeGen/ValueTypes.h" 26309124Sdim#include "llvm/IR/DiagnosticInfo.h" 27309124Sdim#include "llvm/IR/DiagnosticPrinter.h" 28283625Sdim#include "llvm/Support/Debug.h" 29283625Sdim#include "llvm/Support/ErrorHandling.h" 30283625Sdim#include "llvm/Support/raw_ostream.h" 31283625Sdimusing namespace llvm; 32283625Sdim 33283625Sdim#define DEBUG_TYPE "bpf-lower" 34283625Sdim 35341825Sdimstatic cl::opt<bool> BPFExpandMemcpyInOrder("bpf-expand-memcpy-in-order", 36341825Sdim cl::Hidden, cl::init(false), 37341825Sdim cl::desc("Expand memcpy into load/store pairs in order")); 38341825Sdim 39321369Sdimstatic void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg) { 40309124Sdim MachineFunction &MF = DAG.getMachineFunction(); 41309124Sdim DAG.getContext()->diagnose( 42327952Sdim DiagnosticInfoUnsupported(MF.getFunction(), Msg, DL.getDebugLoc())); 43309124Sdim} 44283625Sdim 45309124Sdimstatic void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg, 46309124Sdim SDValue Val) { 47309124Sdim MachineFunction &MF = DAG.getMachineFunction(); 48309124Sdim std::string Str; 49309124Sdim raw_string_ostream OS(Str); 50309124Sdim OS << Msg; 51309124Sdim Val->print(OS); 52309124Sdim OS.flush(); 53309124Sdim DAG.getContext()->diagnose( 54327952Sdim DiagnosticInfoUnsupported(MF.getFunction(), Str, DL.getDebugLoc())); 55285181Sdim} 56283625Sdim 57283625SdimBPFTargetLowering::BPFTargetLowering(const TargetMachine &TM, 58283625Sdim const BPFSubtarget &STI) 59283625Sdim : TargetLowering(TM) { 60283625Sdim 61283625Sdim // Set up the register classes. 62283625Sdim addRegisterClass(MVT::i64, &BPF::GPRRegClass); 63341825Sdim if (STI.getHasAlu32()) 64341825Sdim addRegisterClass(MVT::i32, &BPF::GPR32RegClass); 65283625Sdim 66283625Sdim // Compute derived properties from the register classes 67283625Sdim computeRegisterProperties(STI.getRegisterInfo()); 68283625Sdim 69283625Sdim setStackPointerRegisterToSaveRestore(BPF::R11); 70283625Sdim 71283625Sdim setOperationAction(ISD::BR_CC, MVT::i64, Custom); 72283625Sdim setOperationAction(ISD::BR_JT, MVT::Other, Expand); 73292735Sdim setOperationAction(ISD::BRIND, MVT::Other, Expand); 74283625Sdim setOperationAction(ISD::BRCOND, MVT::Other, Expand); 75283625Sdim 76283625Sdim setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 77283625Sdim 78283625Sdim setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 79283625Sdim setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 80283625Sdim setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 81283625Sdim 82341825Sdim for (auto VT : { MVT::i32, MVT::i64 }) { 83341825Sdim if (VT == MVT::i32 && !STI.getHasAlu32()) 84341825Sdim continue; 85283625Sdim 86341825Sdim setOperationAction(ISD::SDIVREM, VT, Expand); 87341825Sdim setOperationAction(ISD::UDIVREM, VT, Expand); 88341825Sdim setOperationAction(ISD::SREM, VT, Expand); 89341825Sdim setOperationAction(ISD::UREM, VT, Expand); 90341825Sdim setOperationAction(ISD::MULHU, VT, Expand); 91341825Sdim setOperationAction(ISD::MULHS, VT, Expand); 92341825Sdim setOperationAction(ISD::UMUL_LOHI, VT, Expand); 93341825Sdim setOperationAction(ISD::SMUL_LOHI, VT, Expand); 94341825Sdim setOperationAction(ISD::ROTR, VT, Expand); 95341825Sdim setOperationAction(ISD::ROTL, VT, Expand); 96341825Sdim setOperationAction(ISD::SHL_PARTS, VT, Expand); 97341825Sdim setOperationAction(ISD::SRL_PARTS, VT, Expand); 98341825Sdim setOperationAction(ISD::SRA_PARTS, VT, Expand); 99341825Sdim setOperationAction(ISD::CTPOP, VT, Expand); 100283625Sdim 101341825Sdim setOperationAction(ISD::SETCC, VT, Expand); 102341825Sdim setOperationAction(ISD::SELECT, VT, Expand); 103341825Sdim setOperationAction(ISD::SELECT_CC, VT, Custom); 104341825Sdim } 105283625Sdim 106341825Sdim if (STI.getHasAlu32()) { 107341825Sdim setOperationAction(ISD::BSWAP, MVT::i32, Promote); 108353358Sdim setOperationAction(ISD::BR_CC, MVT::i32, 109353358Sdim STI.getHasJmp32() ? Custom : Promote); 110341825Sdim } 111283625Sdim 112283625Sdim setOperationAction(ISD::CTTZ, MVT::i64, Custom); 113283625Sdim setOperationAction(ISD::CTLZ, MVT::i64, Custom); 114283625Sdim setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom); 115283625Sdim setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 116283625Sdim 117283625Sdim setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 118283625Sdim setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 119283625Sdim setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 120283625Sdim setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); 121283625Sdim 122283625Sdim // Extended load operations for i1 types must be promoted 123283625Sdim for (MVT VT : MVT::integer_valuetypes()) { 124283625Sdim setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 125283625Sdim setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 126283625Sdim setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 127283625Sdim 128283625Sdim setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 129283625Sdim setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); 130283625Sdim setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); 131283625Sdim } 132283625Sdim 133283625Sdim setBooleanContents(ZeroOrOneBooleanContent); 134283625Sdim 135360784Sdim // Function alignments 136360784Sdim setMinFunctionAlignment(Align(8)); 137360784Sdim setPrefFunctionAlignment(Align(8)); 138283625Sdim 139341825Sdim if (BPFExpandMemcpyInOrder) { 140341825Sdim // LLVM generic code will try to expand memcpy into load/store pairs at this 141341825Sdim // stage which is before quite a few IR optimization passes, therefore the 142341825Sdim // loads and stores could potentially be moved apart from each other which 143341825Sdim // will cause trouble to memcpy pattern matcher inside kernel eBPF JIT 144341825Sdim // compilers. 145341825Sdim // 146341825Sdim // When -bpf-expand-memcpy-in-order specified, we want to defer the expand 147341825Sdim // of memcpy to later stage in IR optimization pipeline so those load/store 148341825Sdim // pairs won't be touched and could be kept in order. Hence, we set 149341825Sdim // MaxStoresPerMem* to zero to disable the generic getMemcpyLoadsAndStores 150341825Sdim // code path, and ask LLVM to use target expander EmitTargetCodeForMemcpy. 151341825Sdim MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 0; 152341825Sdim MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 0; 153341825Sdim MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 0; 154341825Sdim } else { 155341825Sdim // inline memcpy() for kernel to see explicit copy 156341825Sdim unsigned CommonMaxStores = 157341825Sdim STI.getSelectionDAGInfo()->getCommonMaxStoresPerMemFunc(); 158327952Sdim 159341825Sdim MaxStoresPerMemset = MaxStoresPerMemsetOptSize = CommonMaxStores; 160341825Sdim MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = CommonMaxStores; 161341825Sdim MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = CommonMaxStores; 162341825Sdim } 163341825Sdim 164327952Sdim // CPU/Feature control 165341825Sdim HasAlu32 = STI.getHasAlu32(); 166353358Sdim HasJmp32 = STI.getHasJmp32(); 167327952Sdim HasJmpExt = STI.getHasJmpExt(); 168283625Sdim} 169283625Sdim 170321369Sdimbool BPFTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 171321369Sdim return false; 172321369Sdim} 173321369Sdim 174327952Sdimstd::pair<unsigned, const TargetRegisterClass *> 175327952SdimBPFTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 176327952Sdim StringRef Constraint, 177327952Sdim MVT VT) const { 178327952Sdim if (Constraint.size() == 1) 179327952Sdim // GCC Constraint Letters 180327952Sdim switch (Constraint[0]) { 181327952Sdim case 'r': // GENERAL_REGS 182327952Sdim return std::make_pair(0U, &BPF::GPRRegClass); 183327952Sdim default: 184327952Sdim break; 185327952Sdim } 186327952Sdim 187327952Sdim return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 188327952Sdim} 189327952Sdim 190283625SdimSDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 191283625Sdim switch (Op.getOpcode()) { 192283625Sdim case ISD::BR_CC: 193283625Sdim return LowerBR_CC(Op, DAG); 194283625Sdim case ISD::GlobalAddress: 195283625Sdim return LowerGlobalAddress(Op, DAG); 196283625Sdim case ISD::SELECT_CC: 197283625Sdim return LowerSELECT_CC(Op, DAG); 198283625Sdim default: 199283625Sdim llvm_unreachable("unimplemented operand"); 200283625Sdim } 201283625Sdim} 202283625Sdim 203283625Sdim// Calling Convention Implementation 204283625Sdim#include "BPFGenCallingConv.inc" 205283625Sdim 206283625SdimSDValue BPFTargetLowering::LowerFormalArguments( 207283625Sdim SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 208309124Sdim const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 209309124Sdim SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 210283625Sdim switch (CallConv) { 211283625Sdim default: 212327952Sdim report_fatal_error("Unsupported calling convention"); 213283625Sdim case CallingConv::C: 214283625Sdim case CallingConv::Fast: 215283625Sdim break; 216283625Sdim } 217283625Sdim 218283625Sdim MachineFunction &MF = DAG.getMachineFunction(); 219283625Sdim MachineRegisterInfo &RegInfo = MF.getRegInfo(); 220283625Sdim 221283625Sdim // Assign locations to all of the incoming arguments. 222283625Sdim SmallVector<CCValAssign, 16> ArgLocs; 223283625Sdim CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 224341825Sdim CCInfo.AnalyzeFormalArguments(Ins, getHasAlu32() ? CC_BPF32 : CC_BPF64); 225283625Sdim 226283625Sdim for (auto &VA : ArgLocs) { 227283625Sdim if (VA.isRegLoc()) { 228283625Sdim // Arguments passed in registers 229283625Sdim EVT RegVT = VA.getLocVT(); 230341825Sdim MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; 231341825Sdim switch (SimpleTy) { 232283625Sdim default: { 233283625Sdim errs() << "LowerFormalArguments Unhandled argument type: " 234309124Sdim << RegVT.getEVTString() << '\n'; 235283625Sdim llvm_unreachable(0); 236283625Sdim } 237341825Sdim case MVT::i32: 238283625Sdim case MVT::i64: 239360784Sdim Register VReg = RegInfo.createVirtualRegister( 240360784Sdim SimpleTy == MVT::i64 ? &BPF::GPRRegClass : &BPF::GPR32RegClass); 241283625Sdim RegInfo.addLiveIn(VA.getLocReg(), VReg); 242283625Sdim SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); 243283625Sdim 244341825Sdim // If this is an value that has been promoted to wider types, insert an 245341825Sdim // assert[sz]ext to capture this, then truncate to the right size. 246283625Sdim if (VA.getLocInfo() == CCValAssign::SExt) 247283625Sdim ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, 248283625Sdim DAG.getValueType(VA.getValVT())); 249283625Sdim else if (VA.getLocInfo() == CCValAssign::ZExt) 250283625Sdim ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, 251283625Sdim DAG.getValueType(VA.getValVT())); 252283625Sdim 253283625Sdim if (VA.getLocInfo() != CCValAssign::Full) 254283625Sdim ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); 255283625Sdim 256283625Sdim InVals.push_back(ArgValue); 257341825Sdim 258341825Sdim break; 259283625Sdim } 260283625Sdim } else { 261309124Sdim fail(DL, DAG, "defined with too many args"); 262309124Sdim InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT())); 263283625Sdim } 264283625Sdim } 265283625Sdim 266327952Sdim if (IsVarArg || MF.getFunction().hasStructRetAttr()) { 267309124Sdim fail(DL, DAG, "functions with VarArgs or StructRet are not supported"); 268283625Sdim } 269283625Sdim 270283625Sdim return Chain; 271283625Sdim} 272283625Sdim 273309124Sdimconst unsigned BPFTargetLowering::MaxArgs = 5; 274309124Sdim 275283625SdimSDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 276283625Sdim SmallVectorImpl<SDValue> &InVals) const { 277283625Sdim SelectionDAG &DAG = CLI.DAG; 278283625Sdim auto &Outs = CLI.Outs; 279283625Sdim auto &OutVals = CLI.OutVals; 280283625Sdim auto &Ins = CLI.Ins; 281283625Sdim SDValue Chain = CLI.Chain; 282283625Sdim SDValue Callee = CLI.Callee; 283283625Sdim bool &IsTailCall = CLI.IsTailCall; 284283625Sdim CallingConv::ID CallConv = CLI.CallConv; 285283625Sdim bool IsVarArg = CLI.IsVarArg; 286283625Sdim MachineFunction &MF = DAG.getMachineFunction(); 287283625Sdim 288283625Sdim // BPF target does not support tail call optimization. 289283625Sdim IsTailCall = false; 290283625Sdim 291283625Sdim switch (CallConv) { 292283625Sdim default: 293283625Sdim report_fatal_error("Unsupported calling convention"); 294283625Sdim case CallingConv::Fast: 295283625Sdim case CallingConv::C: 296283625Sdim break; 297283625Sdim } 298283625Sdim 299283625Sdim // Analyze operands of the call, assigning locations to each operand. 300283625Sdim SmallVector<CCValAssign, 16> ArgLocs; 301283625Sdim CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 302283625Sdim 303341825Sdim CCInfo.AnalyzeCallOperands(Outs, getHasAlu32() ? CC_BPF32 : CC_BPF64); 304283625Sdim 305283625Sdim unsigned NumBytes = CCInfo.getNextStackOffset(); 306283625Sdim 307309124Sdim if (Outs.size() > MaxArgs) 308309124Sdim fail(CLI.DL, DAG, "too many args to ", Callee); 309283625Sdim 310283625Sdim for (auto &Arg : Outs) { 311283625Sdim ISD::ArgFlagsTy Flags = Arg.Flags; 312283625Sdim if (!Flags.isByVal()) 313283625Sdim continue; 314283625Sdim 315309124Sdim fail(CLI.DL, DAG, "pass by value not supported ", Callee); 316283625Sdim } 317283625Sdim 318286684Sdim auto PtrVT = getPointerTy(MF.getDataLayout()); 319321369Sdim Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL); 320283625Sdim 321309124Sdim SmallVector<std::pair<unsigned, SDValue>, MaxArgs> RegsToPass; 322283625Sdim 323283625Sdim // Walk arg assignments 324309124Sdim for (unsigned i = 0, 325309124Sdim e = std::min(static_cast<unsigned>(ArgLocs.size()), MaxArgs); 326309124Sdim i != e; ++i) { 327283625Sdim CCValAssign &VA = ArgLocs[i]; 328283625Sdim SDValue Arg = OutVals[i]; 329283625Sdim 330283625Sdim // Promote the value if needed. 331283625Sdim switch (VA.getLocInfo()) { 332283625Sdim default: 333283625Sdim llvm_unreachable("Unknown loc info"); 334283625Sdim case CCValAssign::Full: 335283625Sdim break; 336283625Sdim case CCValAssign::SExt: 337283625Sdim Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); 338283625Sdim break; 339283625Sdim case CCValAssign::ZExt: 340283625Sdim Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); 341283625Sdim break; 342283625Sdim case CCValAssign::AExt: 343283625Sdim Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg); 344283625Sdim break; 345283625Sdim } 346283625Sdim 347283625Sdim // Push arguments into RegsToPass vector 348283625Sdim if (VA.isRegLoc()) 349283625Sdim RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 350283625Sdim else 351283625Sdim llvm_unreachable("call arg pass bug"); 352283625Sdim } 353283625Sdim 354283625Sdim SDValue InFlag; 355283625Sdim 356283625Sdim // Build a sequence of copy-to-reg nodes chained together with token chain and 357283625Sdim // flag operands which copy the outgoing args into registers. The InFlag in 358283625Sdim // necessary since all emitted instructions must be stuck together. 359283625Sdim for (auto &Reg : RegsToPass) { 360283625Sdim Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag); 361283625Sdim InFlag = Chain.getValue(1); 362283625Sdim } 363283625Sdim 364283625Sdim // If the callee is a GlobalAddress node (quite common, every direct call is) 365283625Sdim // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 366283625Sdim // Likewise ExternalSymbol -> TargetExternalSymbol. 367321369Sdim if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 368286684Sdim Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, PtrVT, 369283625Sdim G->getOffset(), 0); 370321369Sdim } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) { 371286684Sdim Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0); 372321369Sdim fail(CLI.DL, DAG, Twine("A call to built-in function '" 373321369Sdim + StringRef(E->getSymbol()) 374321369Sdim + "' is not supported.")); 375321369Sdim } 376283625Sdim 377283625Sdim // Returns a chain & a flag for retval copy to use. 378283625Sdim SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 379283625Sdim SmallVector<SDValue, 8> Ops; 380283625Sdim Ops.push_back(Chain); 381283625Sdim Ops.push_back(Callee); 382283625Sdim 383283625Sdim // Add argument registers to the end of the list so that they are 384283625Sdim // known live into the call. 385283625Sdim for (auto &Reg : RegsToPass) 386283625Sdim Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); 387283625Sdim 388283625Sdim if (InFlag.getNode()) 389283625Sdim Ops.push_back(InFlag); 390283625Sdim 391283625Sdim Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops); 392283625Sdim InFlag = Chain.getValue(1); 393283625Sdim 394283625Sdim // Create the CALLSEQ_END node. 395283625Sdim Chain = DAG.getCALLSEQ_END( 396286684Sdim Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), 397286684Sdim DAG.getConstant(0, CLI.DL, PtrVT, true), InFlag, CLI.DL); 398283625Sdim InFlag = Chain.getValue(1); 399283625Sdim 400283625Sdim // Handle result values, copying them out of physregs into vregs that we 401283625Sdim // return. 402283625Sdim return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG, 403283625Sdim InVals); 404283625Sdim} 405283625Sdim 406283625SdimSDValue 407283625SdimBPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 408283625Sdim bool IsVarArg, 409283625Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 410283625Sdim const SmallVectorImpl<SDValue> &OutVals, 411309124Sdim const SDLoc &DL, SelectionDAG &DAG) const { 412309124Sdim unsigned Opc = BPFISD::RET_FLAG; 413283625Sdim 414283625Sdim // CCValAssign - represent the assignment of the return value to a location 415283625Sdim SmallVector<CCValAssign, 16> RVLocs; 416283625Sdim MachineFunction &MF = DAG.getMachineFunction(); 417283625Sdim 418283625Sdim // CCState - Info about the registers and stack slot. 419283625Sdim CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 420283625Sdim 421327952Sdim if (MF.getFunction().getReturnType()->isAggregateType()) { 422309124Sdim fail(DL, DAG, "only integer returns supported"); 423309124Sdim return DAG.getNode(Opc, DL, MVT::Other, Chain); 424283625Sdim } 425283625Sdim 426283625Sdim // Analize return values. 427341825Sdim CCInfo.AnalyzeReturn(Outs, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64); 428283625Sdim 429283625Sdim SDValue Flag; 430283625Sdim SmallVector<SDValue, 4> RetOps(1, Chain); 431283625Sdim 432283625Sdim // Copy the result values into the output registers. 433283625Sdim for (unsigned i = 0; i != RVLocs.size(); ++i) { 434283625Sdim CCValAssign &VA = RVLocs[i]; 435283625Sdim assert(VA.isRegLoc() && "Can only return in registers!"); 436283625Sdim 437283625Sdim Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); 438283625Sdim 439283625Sdim // Guarantee that all emitted copies are stuck together, 440283625Sdim // avoiding something bad. 441283625Sdim Flag = Chain.getValue(1); 442283625Sdim RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 443283625Sdim } 444283625Sdim 445283625Sdim RetOps[0] = Chain; // Update chain. 446283625Sdim 447283625Sdim // Add the flag if we have it. 448283625Sdim if (Flag.getNode()) 449283625Sdim RetOps.push_back(Flag); 450283625Sdim 451283625Sdim return DAG.getNode(Opc, DL, MVT::Other, RetOps); 452283625Sdim} 453283625Sdim 454283625SdimSDValue BPFTargetLowering::LowerCallResult( 455283625Sdim SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 456309124Sdim const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 457309124Sdim SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 458283625Sdim 459283625Sdim MachineFunction &MF = DAG.getMachineFunction(); 460283625Sdim // Assign locations to each value returned by this call. 461283625Sdim SmallVector<CCValAssign, 16> RVLocs; 462283625Sdim CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 463283625Sdim 464283625Sdim if (Ins.size() >= 2) { 465309124Sdim fail(DL, DAG, "only small returns supported"); 466309124Sdim for (unsigned i = 0, e = Ins.size(); i != e; ++i) 467309124Sdim InVals.push_back(DAG.getConstant(0, DL, Ins[i].VT)); 468309124Sdim return DAG.getCopyFromReg(Chain, DL, 1, Ins[0].VT, InFlag).getValue(1); 469283625Sdim } 470283625Sdim 471341825Sdim CCInfo.AnalyzeCallResult(Ins, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64); 472283625Sdim 473283625Sdim // Copy all of the result registers out of their specified physreg. 474283625Sdim for (auto &Val : RVLocs) { 475283625Sdim Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), 476283625Sdim Val.getValVT(), InFlag).getValue(1); 477283625Sdim InFlag = Chain.getValue(2); 478283625Sdim InVals.push_back(Chain.getValue(0)); 479283625Sdim } 480283625Sdim 481283625Sdim return Chain; 482283625Sdim} 483283625Sdim 484283625Sdimstatic void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { 485283625Sdim switch (CC) { 486283625Sdim default: 487283625Sdim break; 488283625Sdim case ISD::SETULT: 489283625Sdim case ISD::SETULE: 490283625Sdim case ISD::SETLT: 491283625Sdim case ISD::SETLE: 492283625Sdim CC = ISD::getSetCCSwappedOperands(CC); 493283625Sdim std::swap(LHS, RHS); 494283625Sdim break; 495283625Sdim } 496283625Sdim} 497283625Sdim 498283625SdimSDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 499283625Sdim SDValue Chain = Op.getOperand(0); 500283625Sdim ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 501283625Sdim SDValue LHS = Op.getOperand(2); 502283625Sdim SDValue RHS = Op.getOperand(3); 503283625Sdim SDValue Dest = Op.getOperand(4); 504283625Sdim SDLoc DL(Op); 505283625Sdim 506327952Sdim if (!getHasJmpExt()) 507327952Sdim NegateCC(LHS, RHS, CC); 508283625Sdim 509283625Sdim return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS, 510353358Sdim DAG.getConstant(CC, DL, LHS.getValueType()), Dest); 511283625Sdim} 512283625Sdim 513283625SdimSDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 514283625Sdim SDValue LHS = Op.getOperand(0); 515283625Sdim SDValue RHS = Op.getOperand(1); 516283625Sdim SDValue TrueV = Op.getOperand(2); 517283625Sdim SDValue FalseV = Op.getOperand(3); 518283625Sdim ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 519283625Sdim SDLoc DL(Op); 520283625Sdim 521327952Sdim if (!getHasJmpExt()) 522327952Sdim NegateCC(LHS, RHS, CC); 523283625Sdim 524341825Sdim SDValue TargetCC = DAG.getConstant(CC, DL, LHS.getValueType()); 525283625Sdim SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 526283625Sdim SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV}; 527283625Sdim 528283625Sdim return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops); 529283625Sdim} 530283625Sdim 531283625Sdimconst char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const { 532283625Sdim switch ((BPFISD::NodeType)Opcode) { 533283625Sdim case BPFISD::FIRST_NUMBER: 534283625Sdim break; 535283625Sdim case BPFISD::RET_FLAG: 536283625Sdim return "BPFISD::RET_FLAG"; 537283625Sdim case BPFISD::CALL: 538283625Sdim return "BPFISD::CALL"; 539283625Sdim case BPFISD::SELECT_CC: 540283625Sdim return "BPFISD::SELECT_CC"; 541283625Sdim case BPFISD::BR_CC: 542283625Sdim return "BPFISD::BR_CC"; 543283625Sdim case BPFISD::Wrapper: 544283625Sdim return "BPFISD::Wrapper"; 545341825Sdim case BPFISD::MEMCPY: 546341825Sdim return "BPFISD::MEMCPY"; 547283625Sdim } 548283625Sdim return nullptr; 549283625Sdim} 550283625Sdim 551283625SdimSDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op, 552283625Sdim SelectionDAG &DAG) const { 553321369Sdim auto N = cast<GlobalAddressSDNode>(Op); 554321369Sdim assert(N->getOffset() == 0 && "Invalid offset for global address"); 555321369Sdim 556283625Sdim SDLoc DL(Op); 557321369Sdim const GlobalValue *GV = N->getGlobal(); 558283625Sdim SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64); 559283625Sdim 560283625Sdim return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA); 561283625Sdim} 562283625Sdim 563341825Sdimunsigned 564341825SdimBPFTargetLowering::EmitSubregExt(MachineInstr &MI, MachineBasicBlock *BB, 565341825Sdim unsigned Reg, bool isSigned) const { 566341825Sdim const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); 567341825Sdim const TargetRegisterClass *RC = getRegClassFor(MVT::i64); 568341825Sdim int RShiftOp = isSigned ? BPF::SRA_ri : BPF::SRL_ri; 569341825Sdim MachineFunction *F = BB->getParent(); 570341825Sdim DebugLoc DL = MI.getDebugLoc(); 571341825Sdim 572341825Sdim MachineRegisterInfo &RegInfo = F->getRegInfo(); 573360784Sdim Register PromotedReg0 = RegInfo.createVirtualRegister(RC); 574360784Sdim Register PromotedReg1 = RegInfo.createVirtualRegister(RC); 575360784Sdim Register PromotedReg2 = RegInfo.createVirtualRegister(RC); 576341825Sdim BuildMI(BB, DL, TII.get(BPF::MOV_32_64), PromotedReg0).addReg(Reg); 577341825Sdim BuildMI(BB, DL, TII.get(BPF::SLL_ri), PromotedReg1) 578341825Sdim .addReg(PromotedReg0).addImm(32); 579341825Sdim BuildMI(BB, DL, TII.get(RShiftOp), PromotedReg2) 580341825Sdim .addReg(PromotedReg1).addImm(32); 581341825Sdim 582341825Sdim return PromotedReg2; 583341825Sdim} 584341825Sdim 585283625SdimMachineBasicBlock * 586341825SdimBPFTargetLowering::EmitInstrWithCustomInserterMemcpy(MachineInstr &MI, 587341825Sdim MachineBasicBlock *BB) 588341825Sdim const { 589341825Sdim MachineFunction *MF = MI.getParent()->getParent(); 590341825Sdim MachineRegisterInfo &MRI = MF->getRegInfo(); 591341825Sdim MachineInstrBuilder MIB(*MF, MI); 592341825Sdim unsigned ScratchReg; 593341825Sdim 594341825Sdim // This function does custom insertion during lowering BPFISD::MEMCPY which 595341825Sdim // only has two register operands from memcpy semantics, the copy source 596341825Sdim // address and the copy destination address. 597341825Sdim // 598341825Sdim // Because we will expand BPFISD::MEMCPY into load/store pairs, we will need 599341825Sdim // a third scratch register to serve as the destination register of load and 600341825Sdim // source register of store. 601341825Sdim // 602341825Sdim // The scratch register here is with the Define | Dead | EarlyClobber flags. 603341825Sdim // The EarlyClobber flag has the semantic property that the operand it is 604341825Sdim // attached to is clobbered before the rest of the inputs are read. Hence it 605341825Sdim // must be unique among the operands to the instruction. The Define flag is 606341825Sdim // needed to coerce the machine verifier that an Undef value isn't a problem 607341825Sdim // as we anyway is loading memory into it. The Dead flag is needed as the 608341825Sdim // value in scratch isn't supposed to be used by any other instruction. 609341825Sdim ScratchReg = MRI.createVirtualRegister(&BPF::GPRRegClass); 610341825Sdim MIB.addReg(ScratchReg, 611341825Sdim RegState::Define | RegState::Dead | RegState::EarlyClobber); 612341825Sdim 613341825Sdim return BB; 614341825Sdim} 615341825Sdim 616341825SdimMachineBasicBlock * 617309124SdimBPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 618283625Sdim MachineBasicBlock *BB) const { 619283625Sdim const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); 620309124Sdim DebugLoc DL = MI.getDebugLoc(); 621341825Sdim unsigned Opc = MI.getOpcode(); 622341825Sdim bool isSelectRROp = (Opc == BPF::Select || 623341825Sdim Opc == BPF::Select_64_32 || 624341825Sdim Opc == BPF::Select_32 || 625341825Sdim Opc == BPF::Select_32_64); 626283625Sdim 627341825Sdim bool isMemcpyOp = Opc == BPF::MEMCPY; 628283625Sdim 629341825Sdim#ifndef NDEBUG 630341825Sdim bool isSelectRIOp = (Opc == BPF::Select_Ri || 631341825Sdim Opc == BPF::Select_Ri_64_32 || 632341825Sdim Opc == BPF::Select_Ri_32 || 633341825Sdim Opc == BPF::Select_Ri_32_64); 634341825Sdim 635341825Sdim 636341825Sdim assert((isSelectRROp || isSelectRIOp || isMemcpyOp) && 637341825Sdim "Unexpected instr type to insert"); 638341825Sdim#endif 639341825Sdim 640341825Sdim if (isMemcpyOp) 641341825Sdim return EmitInstrWithCustomInserterMemcpy(MI, BB); 642341825Sdim 643341825Sdim bool is32BitCmp = (Opc == BPF::Select_32 || 644341825Sdim Opc == BPF::Select_32_64 || 645341825Sdim Opc == BPF::Select_Ri_32 || 646341825Sdim Opc == BPF::Select_Ri_32_64); 647341825Sdim 648283625Sdim // To "insert" a SELECT instruction, we actually have to insert the diamond 649283625Sdim // control-flow pattern. The incoming instruction knows the destination vreg 650283625Sdim // to set, the condition code register to branch on, the true/false values to 651283625Sdim // select between, and a branch opcode to use. 652283625Sdim const BasicBlock *LLVM_BB = BB->getBasicBlock(); 653296417Sdim MachineFunction::iterator I = ++BB->getIterator(); 654283625Sdim 655283625Sdim // ThisMBB: 656283625Sdim // ... 657283625Sdim // TrueVal = ... 658283625Sdim // jmp_XX r1, r2 goto Copy1MBB 659283625Sdim // fallthrough --> Copy0MBB 660283625Sdim MachineBasicBlock *ThisMBB = BB; 661283625Sdim MachineFunction *F = BB->getParent(); 662283625Sdim MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 663283625Sdim MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 664283625Sdim 665283625Sdim F->insert(I, Copy0MBB); 666283625Sdim F->insert(I, Copy1MBB); 667283625Sdim // Update machine-CFG edges by transferring all successors of the current 668283625Sdim // block to the new block which will contain the Phi node for the select. 669283625Sdim Copy1MBB->splice(Copy1MBB->begin(), BB, 670283625Sdim std::next(MachineBasicBlock::iterator(MI)), BB->end()); 671283625Sdim Copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 672283625Sdim // Next, add the true and fallthrough blocks as its successors. 673283625Sdim BB->addSuccessor(Copy0MBB); 674283625Sdim BB->addSuccessor(Copy1MBB); 675283625Sdim 676283625Sdim // Insert Branch if Flag 677309124Sdim int CC = MI.getOperand(3).getImm(); 678321369Sdim int NewCC; 679283625Sdim switch (CC) { 680353358Sdim#define SET_NEWCC(X, Y) \ 681353358Sdim case ISD::X: \ 682353358Sdim if (is32BitCmp && HasJmp32) \ 683353358Sdim NewCC = isSelectRROp ? BPF::Y##_rr_32 : BPF::Y##_ri_32; \ 684353358Sdim else \ 685353358Sdim NewCC = isSelectRROp ? BPF::Y##_rr : BPF::Y##_ri; \ 686353358Sdim break 687353358Sdim SET_NEWCC(SETGT, JSGT); 688353358Sdim SET_NEWCC(SETUGT, JUGT); 689353358Sdim SET_NEWCC(SETGE, JSGE); 690353358Sdim SET_NEWCC(SETUGE, JUGE); 691353358Sdim SET_NEWCC(SETEQ, JEQ); 692353358Sdim SET_NEWCC(SETNE, JNE); 693353358Sdim SET_NEWCC(SETLT, JSLT); 694353358Sdim SET_NEWCC(SETULT, JULT); 695353358Sdim SET_NEWCC(SETLE, JSLE); 696353358Sdim SET_NEWCC(SETULE, JULE); 697283625Sdim default: 698283625Sdim report_fatal_error("unimplemented select CondCode " + Twine(CC)); 699283625Sdim } 700341825Sdim 701360784Sdim Register LHS = MI.getOperand(1).getReg(); 702341825Sdim bool isSignedCmp = (CC == ISD::SETGT || 703341825Sdim CC == ISD::SETGE || 704341825Sdim CC == ISD::SETLT || 705341825Sdim CC == ISD::SETLE); 706341825Sdim 707341825Sdim // eBPF at the moment only has 64-bit comparison. Any 32-bit comparison need 708341825Sdim // to be promoted, however if the 32-bit comparison operands are destination 709341825Sdim // registers then they are implicitly zero-extended already, there is no 710341825Sdim // need of explicit zero-extend sequence for them. 711341825Sdim // 712341825Sdim // We simply do extension for all situations in this method, but we will 713341825Sdim // try to remove those unnecessary in BPFMIPeephole pass. 714353358Sdim if (is32BitCmp && !HasJmp32) 715341825Sdim LHS = EmitSubregExt(MI, BB, LHS, isSignedCmp); 716341825Sdim 717341825Sdim if (isSelectRROp) { 718360784Sdim Register RHS = MI.getOperand(2).getReg(); 719341825Sdim 720353358Sdim if (is32BitCmp && !HasJmp32) 721341825Sdim RHS = EmitSubregExt(MI, BB, RHS, isSignedCmp); 722341825Sdim 723341825Sdim BuildMI(BB, DL, TII.get(NewCC)).addReg(LHS).addReg(RHS).addMBB(Copy1MBB); 724341825Sdim } else { 725326909Sdim int64_t imm32 = MI.getOperand(2).getImm(); 726326909Sdim // sanity check before we build J*_ri instruction. 727326909Sdim assert (isInt<32>(imm32)); 728321369Sdim BuildMI(BB, DL, TII.get(NewCC)) 729341825Sdim .addReg(LHS).addImm(imm32).addMBB(Copy1MBB); 730326909Sdim } 731283625Sdim 732283625Sdim // Copy0MBB: 733283625Sdim // %FalseValue = ... 734283625Sdim // # fallthrough to Copy1MBB 735283625Sdim BB = Copy0MBB; 736283625Sdim 737283625Sdim // Update machine-CFG edges 738283625Sdim BB->addSuccessor(Copy1MBB); 739283625Sdim 740283625Sdim // Copy1MBB: 741283625Sdim // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ] 742283625Sdim // ... 743283625Sdim BB = Copy1MBB; 744309124Sdim BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg()) 745309124Sdim .addReg(MI.getOperand(5).getReg()) 746283625Sdim .addMBB(Copy0MBB) 747309124Sdim .addReg(MI.getOperand(4).getReg()) 748283625Sdim .addMBB(ThisMBB); 749283625Sdim 750309124Sdim MI.eraseFromParent(); // The pseudo instruction is gone now. 751283625Sdim return BB; 752283625Sdim} 753341825Sdim 754341825SdimEVT BPFTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 755341825Sdim EVT VT) const { 756341825Sdim return getHasAlu32() ? MVT::i32 : MVT::i64; 757341825Sdim} 758341825Sdim 759341825SdimMVT BPFTargetLowering::getScalarShiftAmountTy(const DataLayout &DL, 760341825Sdim EVT VT) const { 761341825Sdim return (getHasAlu32() && VT == MVT::i32) ? MVT::i32 : MVT::i64; 762341825Sdim} 763