/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | CallingConvLower.h | 343 /// in the set, or Regs.size() if they are all allocated. 344 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { 345 for (unsigned i = 0; i < Regs.size(); ++i) 346 if (!isAllocated(Regs[i])) 348 return Regs.size(); 371 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { argument 372 unsigned FirstUnalloc = getFirstUnallocated(Regs); 373 if (FirstUnalloc == Regs.size()) 377 unsigned Reg = Regs[FirstUnalloc]; 385 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigne argument 412 AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) argument [all...] |
H A D | RegisterPressure.h | 275 RegSet Regs; 297 RegSet::const_iterator I = Regs.find(SparseIndex); 298 if (I == Regs.end()) 307 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask)); 320 RegSet::iterator I = Regs.find(SparseIndex); 321 if (I == Regs.end()) 329 return Regs.size(); 334 for (const IndexMaskPair &P : Regs) { 411 void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/ |
H A D | HWEventListener.h | 74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, argument 77 UsedPhysRegs(Regs), MicroOpcodes(UOps) {} 95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) argument 97 FreedPhysRegs(Regs) {}
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 83 const unsigned *Regs, unsigned Size) { 85 RegNo = Regs[RegNo]; 292 const unsigned *Regs) { 296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 302 const unsigned *Regs) { 306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 312 const unsigned *Regs) { 317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 319 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); 324 const unsigned *Regs) { 82 decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned *Regs, unsigned Size) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | CallLowering.h | 47 SmallVector<Register, 4> Regs; member in struct:llvm::CallLowering::ArgInfo 56 ArgInfo(ArrayRef<Register> Regs, Type *Ty, argument 59 : Regs(Regs.begin(), Regs.end()), Ty(Ty), 61 if (!Regs.empty() && Flags.empty()) 64 assert((Ty->isVoidTy() == (Regs.empty() || Regs[0] == 0)) &&
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMUnwindOpAsm.cpp | 107 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { 108 while (Regs) { 110 auto RangeMSB = 32 - countLeadingZeros(Regs); 111 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB)); 121 Regs &= ~(-1u << RangeLSB);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86CallLowering.cpp | 64 assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet"); 74 SplitArgs.emplace_back(OrigArg.Regs[0], VT.getTypeForEVT(Context), 89 SplitRegs.push_back(Info.Regs[0]); 212 [&](ArrayRef<Register> Regs) { 213 MIRBuilder.buildUnmerge(Regs, VRegs[i]); 357 [&](ArrayRef<Register> Regs) { 358 MIRBuilder.buildMerge(VRegs[Idx][0], Regs); 414 if (OrigArg.Regs.size() > 1) 418 [&](ArrayRef<Register> Regs) { 419 MIRBuilder.buildUnmerge(Regs, OrigAr [all...] |
/freebsd-11-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
H A D | Taint.cpp | 136 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap(); local 138 Regs = F.add(Regs, SubRegion, Kind); 139 ProgramStateRef NewState = State->set<DerivedSymTaint>(ParentSym, Regs); 202 if (const TaintedSubRegions *Regs = 205 for (auto I : *Regs) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CallLowering.cpp | 142 assert(LLTs.size() == SrcRegs.size() && "Regs / types mismatch"); 165 assert(LLTs.size() == DstRegs.size() && "Regs / types mismatch"); 228 Args[i].OrigRegs.push_back(Args[i].Regs[0]); 229 Args[i].Regs.clear(); 246 Args[i].Regs.push_back(Reg); 262 Register LargeReg = Args[i].Regs[0]; 268 Args[i].Regs.clear(); 279 Args[i].Regs.push_back(Unmerge.getReg(PartIdx)); 301 Register ArgReg = Args[i].Regs[0]; 309 unsigned NumArgRegs = Args[i].Regs [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 86 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs, 89 const std::deque<CodeGenRegister> &Regs, 204 const CodeGenRegister::Vec &Regs = RC.getMembers(); local 205 if (Regs.empty() || RC.Artificial) 210 OS << " {" << (*Regs.begin())->getWeight(RegBank) 371 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 377 for (auto &RE : Regs) { 395 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 443 for (auto &RE : Regs) { 506 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, boo 370 EmitRegMappingTables( raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) argument 505 EmitRegMapping( raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) argument 870 const auto &Regs = RegBank.getRegisters(); local 1438 const auto &Regs = RegBank.getRegisters(); local 1538 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); local [all...] |
H A D | CodeGenRegisters.cpp | 212 RegUnitIterator(const CodeGenRegister::Vec &Regs): argument 213 RegI(Regs.begin()), RegE(Regs.end()) { 1114 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); local 1115 llvm::sort(Regs, LessRecordRegister()); 1117 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 1118 getReg(Regs[i]); 1570 CodeGenRegister::Vec Regs; member in struct:__anon2913::UberRegSet 1599 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); local 1600 if (Regs 2386 computeCoveredRegisters(ArrayRef<Record*> Regs) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCallLowering.cpp | 166 assert(OrigArg.Regs.size() == SplitVTs.size()); 178 SplitArgs.emplace_back(OrigArg.Regs[SplitIdx], Ty, 281 [&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) { 282 unpackRegsToOrigType(B, Regs, VRegs[VTSplitIdx], LLTy, PartLLT); 491 ArrayRef<Register> Regs, 495 B.buildMerge(OrigRegs[0], Regs); 505 B.buildConcatVectors(OrigRegs[0], Regs); 512 auto RoundedConcat = B.buildConcatVectors(RoundedDestTy, Regs); 535 for (Register Reg : Regs) 539 B.buildBuildVector(OrigRegs[0], Regs); 489 packSplitRegsToOrigType(MachineIRBuilder &B, ArrayRef<Register> OrigRegs, ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ExecutionDomainFix.cpp | 329 SmallVector<int, 4> Regs; 341 auto I = partition_point(Regs, [&](int I) { 344 Regs.insert(I, rx); 350 while (!Regs.empty()) { 352 dv = LiveRegs[Regs.pop_back_val()]; 359 DomainValue *Latest = LiveRegs[Regs.pop_back_val()];
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H A D | RDFRegisters.cpp | 324 auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) { 327 Regs.set(*S); 334 BitVector Regs(PRI.getTRI().getNumRegs()); 335 AliasedRegs(U, Regs); 343 Regs &= AR; 351 int F = Regs.find_first();
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H A D | AggressiveAntiDepBreaker.cpp | 85 std::vector<unsigned> &Regs, 90 Regs.push_back(Reg); 562 std::vector<unsigned> Regs; 563 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); 564 assert(!Regs.empty() && "Empty register group!"); 565 if (Regs.empty()) 575 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 576 unsigned Reg = Regs[i]; 598 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 599 unsigned Reg = Regs[ 83 GetGroupRegs( unsigned Group, std::vector<unsigned> &Regs, std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs) argument [all...] |
H A D | AggressiveAntiDepBreaker.h | 99 std::vector<unsigned> &Regs,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRegisterInfo.cpp | 135 static const unsigned Regs[2][2] = { local 140 return Regs[TFI->hasFP(MF)][TT.isArch64Bit()];
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/ |
H A D | RegisterFile.h | 223 unsigned isAvailable(ArrayRef<MCPhysReg> Regs) const;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
H A D | AMDGPUPALMetadata.cpp | 161 auto Regs = getRegisters(); local 162 auto It = Regs.find(MsgPackDoc.getNode(Reg)); 163 if (It == Regs.end()) 555 auto Regs = getRegisters(); local 556 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { 557 if (I != Regs.begin())
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMCallLowering.cpp | 142 assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet"); 160 MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]); 200 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch"); 207 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx), 230 Register PartReg = OrigArg.Regs[i]; 366 assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet"); 392 MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
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H A D | ARMLoadStoreOptimizer.cpp | 176 ArrayRef<std::pair<unsigned, bool>> Regs, 182 ArrayRef<std::pair<unsigned, bool>> Regs, 580 /// Return the first register of class \p RegClass that is not in \p Regs. 612 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs, argument 614 for (const std::pair<unsigned, bool> &R : Regs) 621 /// Regs as the register operands that would be loaded / stored. It returns 627 ArrayRef<std::pair<unsigned, bool>> Regs, 629 unsigned NumRegs = Regs.size(); 643 if (isThumb1 && ContainsReg(Regs, Base)) { 683 NewBase = Regs[NumReg 623 CreateLoadStoreMulti( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base, bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, ArrayRef<std::pair<unsigned, bool>> Regs, ArrayRef<MachineInstr*> Instrs) argument 830 CreateLoadStoreDouble( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base, bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, ArrayRef<std::pair<unsigned, bool>> Regs, ArrayRef<MachineInstr*> Instrs) const argument 860 SmallVector<std::pair<unsigned, bool>, 8> Regs; local [all...] |
H A D | ARMFrameLowering.cpp | 986 SmallVector<RegAndKill, 4> Regs; 1013 Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn)); 1016 if (Regs.empty()) 1019 llvm::sort(Regs, [&](const RegAndKill &LHS, const RegAndKill &RHS) { 1023 if (Regs.size() > 1 || StrOpc== 0) { 1028 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 1029 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 1030 } else if (Regs.size() == 1) { 1032 .addReg(Regs[ 1074 SmallVector<unsigned, 4> Regs; local [all...] |
H A D | Thumb2ITBlockPass.cpp | 99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { 100 for (unsigned Reg : Regs)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 410 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, 414 RegisterGroup Group, const unsigned *Regs, 427 MemoryKind MemKind, const unsigned *Regs, 735 // Parse a register of group Group. If Regs is nonnull, use it to map 742 const unsigned *Regs, bool IsAddress) { 747 if (Regs && Regs[Reg.Num] == 0) 751 if (Regs) 752 Reg.Num = Regs[Reg.Num]; 759 const unsigned *Regs, RegisterKin 741 parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, bool IsAddress) argument 758 parseRegister(OperandVector &Operands, RegisterGroup Group, const unsigned *Regs, RegisterKind Kind) argument 896 parseAddress(OperandVector &Operands, MemoryKind MemKind, const unsigned *Regs, RegisterKind RegKind) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.h | 850 SmallVector<unsigned, 4> Regs; member in struct:llvm::RegsForValue 874 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 875 RegCount.push_back(RHS.Regs.size());
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