Lines Matching refs:Regs
176 ArrayRef<std::pair<unsigned, bool>> Regs,
182 ArrayRef<std::pair<unsigned, bool>> Regs,
580 /// Return the first register of class \p RegClass that is not in \p Regs.
612 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs,
614 for (const std::pair<unsigned, bool> &R : Regs)
621 /// Regs as the register operands that would be loaded / stored. It returns
627 ArrayRef<std::pair<unsigned, bool>> Regs,
629 unsigned NumRegs = Regs.size();
643 if (isThumb1 && ContainsReg(Regs, Base)) {
683 NewBase = Regs[NumRegs-1].first;
688 // The merged instruction does not exist yet but will use several Regs if
691 for (const std::pair<unsigned, bool> &R : Regs)
725 (!isi32Store(Opcode) || !ContainsReg(Regs, Base));
799 assert(!(ContainsReg(Regs, Base)) && "Thumb1 can't LDM ! with Base in Regs");
822 for (const std::pair<unsigned, bool> &R : Regs)
834 ArrayRef<std::pair<unsigned, bool>> Regs,
840 assert(Regs.size() == 2);
844 MIB.addReg(Regs[0].first, RegState::Define)
845 .addReg(Regs[1].first, RegState::Define);
847 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))
848 .addReg(Regs[1].first, getKillRegState(Regs[1].second));
860 SmallVector<std::pair<unsigned, bool>, 8> Regs;
871 Regs.push_back(std::make_pair(Reg, IsKill));
909 Opcode, Pred, PredReg, DL, Regs,
913 Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);