1327952Sdim//===- SelectionDAGBuilder.h - Selection-DAG building -----------*- C++ -*-===// 2199989Srdivacky// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6199989Srdivacky// 7199989Srdivacky//===----------------------------------------------------------------------===// 8199989Srdivacky// 9199989Srdivacky// This implements routines for translating from LLVM IR into SelectionDAG IR. 10199989Srdivacky// 11199989Srdivacky//===----------------------------------------------------------------------===// 12199989Srdivacky 13280031Sdim#ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H 14280031Sdim#define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H 15199989Srdivacky 16280031Sdim#include "StatepointLowering.h" 17199989Srdivacky#include "llvm/ADT/APInt.h" 18327952Sdim#include "llvm/ADT/ArrayRef.h" 19199989Srdivacky#include "llvm/ADT/DenseMap.h" 20353358Sdim#include "llvm/ADT/MapVector.h" 21327952Sdim#include "llvm/ADT/SmallVector.h" 22296417Sdim#include "llvm/Analysis/AliasAnalysis.h" 23327952Sdim#include "llvm/CodeGen/ISDOpcodes.h" 24249423Sdim#include "llvm/CodeGen/SelectionDAG.h" 25199989Srdivacky#include "llvm/CodeGen/SelectionDAGNodes.h" 26353358Sdim#include "llvm/CodeGen/SwitchLoweringUtils.h" 27327952Sdim#include "llvm/CodeGen/TargetLowering.h" 28327952Sdim#include "llvm/CodeGen/ValueTypes.h" 29276479Sdim#include "llvm/IR/CallSite.h" 30327952Sdim#include "llvm/IR/DebugLoc.h" 31327952Sdim#include "llvm/IR/Instruction.h" 32288943Sdim#include "llvm/IR/Statepoint.h" 33327952Sdim#include "llvm/Support/BranchProbability.h" 34327952Sdim#include "llvm/Support/CodeGen.h" 35199989Srdivacky#include "llvm/Support/ErrorHandling.h" 36341825Sdim#include "llvm/Support/MachineValueType.h" 37327952Sdim#include <algorithm> 38327952Sdim#include <cassert> 39327952Sdim#include <cstdint> 40309124Sdim#include <utility> 41199989Srdivacky#include <vector> 42199989Srdivacky 43199989Srdivackynamespace llvm { 44199989Srdivacky 45199989Srdivackyclass AllocaInst; 46327952Sdimclass AtomicCmpXchgInst; 47327952Sdimclass AtomicRMWInst; 48199989Srdivackyclass BasicBlock; 49199989Srdivackyclass BranchInst; 50199989Srdivackyclass CallInst; 51353358Sdimclass CallBrInst; 52327952Sdimclass CatchPadInst; 53327952Sdimclass CatchReturnInst; 54327952Sdimclass CatchSwitchInst; 55327952Sdimclass CleanupPadInst; 56327952Sdimclass CleanupReturnInst; 57327952Sdimclass Constant; 58327952Sdimclass ConstantInt; 59327952Sdimclass ConstrainedFPIntrinsic; 60207618Srdivackyclass DbgValueInst; 61327952Sdimclass DataLayout; 62327952Sdimclass DIExpression; 63327952Sdimclass DILocalVariable; 64327952Sdimclass DILocation; 65327952Sdimclass FenceInst; 66199989Srdivackyclass FunctionLoweringInfo; 67199989Srdivackyclass GCFunctionInfo; 68327952Sdimclass GCRelocateInst; 69327952Sdimclass GCResultInst; 70199989Srdivackyclass IndirectBrInst; 71199989Srdivackyclass InvokeInst; 72327952Sdimclass LandingPadInst; 73327952Sdimclass LLVMContext; 74199989Srdivackyclass LoadInst; 75199989Srdivackyclass MachineBasicBlock; 76199989Srdivackyclass PHINode; 77327952Sdimclass ResumeInst; 78199989Srdivackyclass ReturnInst; 79212904Sdimclass SDDbgValue; 80199989Srdivackyclass StoreInst; 81353358Sdimclass SwiftErrorValueTracking; 82199989Srdivackyclass SwitchInst; 83234353Sdimclass TargetLibraryInfo; 84327952Sdimclass TargetMachine; 85327952Sdimclass Type; 86327952Sdimclass VAArgInst; 87199989Srdivackyclass UnreachableInst; 88327952Sdimclass Use; 89327952Sdimclass User; 90327952Sdimclass Value; 91199989Srdivacky 92199989Srdivacky//===----------------------------------------------------------------------===// 93199989Srdivacky/// SelectionDAGBuilder - This is the common target-independent lowering 94199989Srdivacky/// implementation that is parameterized by a TargetLowering object. 95199989Srdivacky/// 96199989Srdivackyclass SelectionDAGBuilder { 97353358Sdim /// The current instruction being visited. 98327952Sdim const Instruction *CurInst = nullptr; 99199989Srdivacky 100199989Srdivacky DenseMap<const Value*, SDValue> NodeMap; 101261991Sdim 102353358Sdim /// Maps argument value for unused arguments. This is used 103210299Sed /// to preserve debug information for incoming arguments. 104210299Sed DenseMap<const Value*, SDValue> UnusedArgNodeMap; 105199989Srdivacky 106353358Sdim /// Helper type for DanglingDebugInfoMap. 107212904Sdim class DanglingDebugInfo { 108327952Sdim const DbgValueInst* DI = nullptr; 109212904Sdim DebugLoc dl; 110327952Sdim unsigned SDNodeOrder = 0; 111327952Sdim 112212904Sdim public: 113327952Sdim DanglingDebugInfo() = default; 114309124Sdim DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) 115309124Sdim : DI(di), dl(std::move(DL)), SDNodeOrder(SDNO) {} 116327952Sdim 117212904Sdim const DbgValueInst* getDI() { return DI; } 118212904Sdim DebugLoc getdl() { return dl; } 119212904Sdim unsigned getSDNodeOrder() { return SDNodeOrder; } 120212904Sdim }; 121212904Sdim 122353358Sdim /// Helper type for DanglingDebugInfoMap. 123341825Sdim typedef std::vector<DanglingDebugInfo> DanglingDebugInfoVector; 124341825Sdim 125353358Sdim /// Keeps track of dbg_values for which we have not yet seen the referent. 126353358Sdim /// We defer handling these until we do see it. 127353358Sdim MapVector<const Value*, DanglingDebugInfoVector> DanglingDebugInfoMap; 128212904Sdim 129201360Srdivackypublic: 130353358Sdim /// Loads are not emitted to the program immediately. We bunch them up and 131353358Sdim /// then emit token factor nodes when possible. This allows us to get simple 132353358Sdim /// disambiguation between loads without worrying about alias analysis. 133199989Srdivacky SmallVector<SDValue, 8> PendingLoads; 134280031Sdim 135280031Sdim /// State used while lowering a statepoint sequence (gc_statepoint, 136280031Sdim /// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details. 137280031Sdim StatepointLoweringState StatepointLowering; 138327952Sdim 139201360Srdivackyprivate: 140353358Sdim /// CopyToReg nodes that copy values to virtual registers for export to other 141353358Sdim /// blocks need to be emitted before any terminator instruction, but they have 142353358Sdim /// no other ordering requirements. We bunch them up and the emit a single 143353358Sdim /// tokenfactor for them just before terminator instructions. 144199989Srdivacky SmallVector<SDValue, 8> PendingExports; 145199989Srdivacky 146360784Sdim /// Similar to loads, nodes corresponding to constrained FP intrinsics are 147360784Sdim /// bunched up and emitted when necessary. These can be moved across each 148360784Sdim /// other and any (normal) memory operation (load or store), but not across 149360784Sdim /// calls or instructions having unspecified side effects. As a special 150360784Sdim /// case, constrained FP intrinsics using fpexcept.strict may not be deleted 151360784Sdim /// even if otherwise unused, so they need to be chained before any 152360784Sdim /// terminator instruction (like PendingExports). We track the latter 153360784Sdim /// set of nodes in a separate list. 154360784Sdim SmallVector<SDValue, 8> PendingConstrainedFP; 155360784Sdim SmallVector<SDValue, 8> PendingConstrainedFPStrict; 156360784Sdim 157360784Sdim /// Update root to include all chains from the Pending list. 158360784Sdim SDValue updateRoot(SmallVectorImpl<SDValue> &Pending); 159360784Sdim 160353358Sdim /// A unique monotonically increasing number used to order the SDNodes we 161353358Sdim /// create. 162201360Srdivacky unsigned SDNodeOrder; 163201360Srdivacky 164288943Sdim /// Determine the rank by weight of CC in [First,Last]. If CC has more weight 165288943Sdim /// than each cluster in the range, its rank is 0. 166353358Sdim unsigned caseClusterRank(const SwitchCG::CaseCluster &CC, 167353358Sdim SwitchCG::CaseClusterIt First, 168353358Sdim SwitchCG::CaseClusterIt Last); 169288943Sdim 170288943Sdim /// Emit comparison and split W into two subtrees. 171353358Sdim void splitWorkItem(SwitchCG::SwitchWorkList &WorkList, 172353358Sdim const SwitchCG::SwitchWorkListItem &W, Value *Cond, 173353358Sdim MachineBasicBlock *SwitchMBB); 174288943Sdim 175288943Sdim /// Lower W. 176353358Sdim void lowerWorkItem(SwitchCG::SwitchWorkListItem W, Value *Cond, 177288943Sdim MachineBasicBlock *SwitchMBB, 178288943Sdim MachineBasicBlock *DefaultMBB); 179288943Sdim 180327952Sdim /// Peel the top probability case if it exceeds the threshold 181353358Sdim MachineBasicBlock * 182353358Sdim peelDominantCaseCluster(const SwitchInst &SI, 183353358Sdim SwitchCG::CaseClusterVector &Clusters, 184353358Sdim BranchProbability &PeeledCaseProb); 185288943Sdim 186261991Sdim /// A class which encapsulates all of the information needed to generate a 187261991Sdim /// stack protector check and signals to isel via its state being initialized 188261991Sdim /// that a stack protector needs to be generated. 189261991Sdim /// 190261991Sdim /// *NOTE* The following is a high level documentation of SelectionDAG Stack 191261991Sdim /// Protector Generation. The reason that it is placed here is for a lack of 192261991Sdim /// other good places to stick it. 193261991Sdim /// 194261991Sdim /// High Level Overview of SelectionDAG Stack Protector Generation: 195261991Sdim /// 196261991Sdim /// Previously, generation of stack protectors was done exclusively in the 197261991Sdim /// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated 198261991Sdim /// splitting basic blocks at the IR level to create the success/failure basic 199261991Sdim /// blocks in the tail of the basic block in question. As a result of this, 200261991Sdim /// calls that would have qualified for the sibling call optimization were no 201261991Sdim /// longer eligible for optimization since said calls were no longer right in 202261991Sdim /// the "tail position" (i.e. the immediate predecessor of a ReturnInst 203261991Sdim /// instruction). 204261991Sdim /// 205261991Sdim /// Then it was noticed that since the sibling call optimization causes the 206261991Sdim /// callee to reuse the caller's stack, if we could delay the generation of 207261991Sdim /// the stack protector check until later in CodeGen after the sibling call 208261991Sdim /// decision was made, we get both the tail call optimization and the stack 209261991Sdim /// protector check! 210261991Sdim /// 211261991Sdim /// A few goals in solving this problem were: 212261991Sdim /// 213261991Sdim /// 1. Preserve the architecture independence of stack protector generation. 214261991Sdim /// 215261991Sdim /// 2. Preserve the normal IR level stack protector check for platforms like 216276479Sdim /// OpenBSD for which we support platform-specific stack protector 217261991Sdim /// generation. 218261991Sdim /// 219261991Sdim /// The main problem that guided the present solution is that one can not 220261991Sdim /// solve this problem in an architecture independent manner at the IR level 221261991Sdim /// only. This is because: 222261991Sdim /// 223261991Sdim /// 1. The decision on whether or not to perform a sibling call on certain 224261991Sdim /// platforms (for instance i386) requires lower level information 225261991Sdim /// related to available registers that can not be known at the IR level. 226261991Sdim /// 227261991Sdim /// 2. Even if the previous point were not true, the decision on whether to 228261991Sdim /// perform a tail call is done in LowerCallTo in SelectionDAG which 229261991Sdim /// occurs after the Stack Protector Pass. As a result, one would need to 230261991Sdim /// put the relevant callinst into the stack protector check success 231261991Sdim /// basic block (where the return inst is placed) and then move it back 232261991Sdim /// later at SelectionDAG/MI time before the stack protector check if the 233261991Sdim /// tail call optimization failed. The MI level option was nixed 234276479Sdim /// immediately since it would require platform-specific pattern 235261991Sdim /// matching. The SelectionDAG level option was nixed because 236261991Sdim /// SelectionDAG only processes one IR level basic block at a time 237261991Sdim /// implying one could not create a DAG Combine to move the callinst. 238261991Sdim /// 239261991Sdim /// To get around this problem a few things were realized: 240261991Sdim /// 241261991Sdim /// 1. While one can not handle multiple IR level basic blocks at the 242261991Sdim /// SelectionDAG Level, one can generate multiple machine basic blocks 243261991Sdim /// for one IR level basic block. This is how we handle bit tests and 244261991Sdim /// switches. 245261991Sdim /// 246261991Sdim /// 2. At the MI level, tail calls are represented via a special return 247261991Sdim /// MIInst called "tcreturn". Thus if we know the basic block in which we 248261991Sdim /// wish to insert the stack protector check, we get the correct behavior 249261991Sdim /// by always inserting the stack protector check right before the return 250261991Sdim /// statement. This is a "magical transformation" since no matter where 251261991Sdim /// the stack protector check intrinsic is, we always insert the stack 252261991Sdim /// protector check code at the end of the BB. 253261991Sdim /// 254261991Sdim /// Given the aforementioned constraints, the following solution was devised: 255261991Sdim /// 256261991Sdim /// 1. On platforms that do not support SelectionDAG stack protector check 257261991Sdim /// generation, allow for the normal IR level stack protector check 258261991Sdim /// generation to continue. 259261991Sdim /// 260261991Sdim /// 2. On platforms that do support SelectionDAG stack protector check 261261991Sdim /// generation: 262261991Sdim /// 263261991Sdim /// a. Use the IR level stack protector pass to decide if a stack 264261991Sdim /// protector is required/which BB we insert the stack protector check 265261991Sdim /// in by reusing the logic already therein. If we wish to generate a 266261991Sdim /// stack protector check in a basic block, we place a special IR 267261991Sdim /// intrinsic called llvm.stackprotectorcheck right before the BB's 268261991Sdim /// returninst or if there is a callinst that could potentially be 269261991Sdim /// sibling call optimized, before the call inst. 270261991Sdim /// 271261991Sdim /// b. Then when a BB with said intrinsic is processed, we codegen the BB 272261991Sdim /// normally via SelectBasicBlock. In said process, when we visit the 273261991Sdim /// stack protector check, we do not actually emit anything into the 274261991Sdim /// BB. Instead, we just initialize the stack protector descriptor 275261991Sdim /// class (which involves stashing information/creating the success 276261991Sdim /// mbbb and the failure mbb if we have not created one for this 277261991Sdim /// function yet) and export the guard variable that we are going to 278261991Sdim /// compare. 279261991Sdim /// 280261991Sdim /// c. After we finish selecting the basic block, in FinishBasicBlock if 281261991Sdim /// the StackProtectorDescriptor attached to the SelectionDAGBuilder is 282309124Sdim /// initialized, we produce the validation code with one of these 283309124Sdim /// techniques: 284309124Sdim /// 1) with a call to a guard check function 285309124Sdim /// 2) with inlined instrumentation 286309124Sdim /// 287309124Sdim /// 1) We insert a call to the check function before the terminator. 288309124Sdim /// 289309124Sdim /// 2) We first find a splice point in the parent basic block 290261991Sdim /// before the terminator and then splice the terminator of said basic 291261991Sdim /// block into the success basic block. Then we code-gen a new tail for 292261991Sdim /// the parent basic block consisting of the two loads, the comparison, 293261991Sdim /// and finally two branches to the success/failure basic blocks. We 294261991Sdim /// conclude by code-gening the failure basic block if we have not 295261991Sdim /// code-gened it already (all stack protector checks we generate in 296261991Sdim /// the same function, use the same failure basic block). 297261991Sdim class StackProtectorDescriptor { 298261991Sdim public: 299327952Sdim StackProtectorDescriptor() = default; 300261991Sdim 301261991Sdim /// Returns true if all fields of the stack protector descriptor are 302261991Sdim /// initialized implying that we should/are ready to emit a stack protector. 303261991Sdim bool shouldEmitStackProtector() const { 304309124Sdim return ParentMBB && SuccessMBB && FailureMBB; 305261991Sdim } 306261991Sdim 307309124Sdim bool shouldEmitFunctionBasedCheckStackProtector() const { 308309124Sdim return ParentMBB && !SuccessMBB && !FailureMBB; 309309124Sdim } 310309124Sdim 311261991Sdim /// Initialize the stack protector descriptor structure for a new basic 312261991Sdim /// block. 313309124Sdim void initialize(const BasicBlock *BB, MachineBasicBlock *MBB, 314309124Sdim bool FunctionBasedInstrumentation) { 315261991Sdim // Make sure we are not initialized yet. 316261991Sdim assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is " 317261991Sdim "already initialized!"); 318261991Sdim ParentMBB = MBB; 319309124Sdim if (!FunctionBasedInstrumentation) { 320309124Sdim SuccessMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ true); 321309124Sdim FailureMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ false, FailureMBB); 322309124Sdim } 323261991Sdim } 324261991Sdim 325261991Sdim /// Reset state that changes when we handle different basic blocks. 326261991Sdim /// 327261991Sdim /// This currently includes: 328261991Sdim /// 329261991Sdim /// 1. The specific basic block we are generating a 330261991Sdim /// stack protector for (ParentMBB). 331261991Sdim /// 332261991Sdim /// 2. The successor machine basic block that will contain the tail of 333261991Sdim /// parent mbb after we create the stack protector check (SuccessMBB). This 334261991Sdim /// BB is visited only on stack protector check success. 335261991Sdim void resetPerBBState() { 336276479Sdim ParentMBB = nullptr; 337276479Sdim SuccessMBB = nullptr; 338261991Sdim } 339261991Sdim 340261991Sdim /// Reset state that only changes when we switch functions. 341261991Sdim /// 342261991Sdim /// This currently includes: 343261991Sdim /// 344261991Sdim /// 1. FailureMBB since we reuse the failure code path for all stack 345261991Sdim /// protector checks created in an individual function. 346261991Sdim /// 347261991Sdim /// 2.The guard variable since the guard variable we are checking against is 348261991Sdim /// always the same. 349261991Sdim void resetPerFunctionState() { 350276479Sdim FailureMBB = nullptr; 351261991Sdim } 352261991Sdim 353261991Sdim MachineBasicBlock *getParentMBB() { return ParentMBB; } 354261991Sdim MachineBasicBlock *getSuccessMBB() { return SuccessMBB; } 355261991Sdim MachineBasicBlock *getFailureMBB() { return FailureMBB; } 356261991Sdim 357261991Sdim private: 358261991Sdim /// The basic block for which we are generating the stack protector. 359261991Sdim /// 360261991Sdim /// As a result of stack protector generation, we will splice the 361261991Sdim /// terminators of this basic block into the successor mbb SuccessMBB and 362261991Sdim /// replace it with a compare/branch to the successor mbbs 363261991Sdim /// SuccessMBB/FailureMBB depending on whether or not the stack protector 364261991Sdim /// was violated. 365327952Sdim MachineBasicBlock *ParentMBB = nullptr; 366261991Sdim 367261991Sdim /// A basic block visited on stack protector check success that contains the 368261991Sdim /// terminators of ParentMBB. 369327952Sdim MachineBasicBlock *SuccessMBB = nullptr; 370261991Sdim 371261991Sdim /// This basic block visited on stack protector check failure that will 372261991Sdim /// contain a call to __stack_chk_fail(). 373327952Sdim MachineBasicBlock *FailureMBB = nullptr; 374261991Sdim 375261991Sdim /// Add a successor machine basic block to ParentMBB. If the successor mbb 376261991Sdim /// has not been created yet (i.e. if SuccMBB = 0), then the machine basic 377280031Sdim /// block will be created. Assign a large weight if IsLikely is true. 378261991Sdim MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB, 379261991Sdim MachineBasicBlock *ParentMBB, 380280031Sdim bool IsLikely, 381276479Sdim MachineBasicBlock *SuccMBB = nullptr); 382261991Sdim }; 383261991Sdim 384261991Sdimprivate: 385261991Sdim const TargetMachine &TM; 386327952Sdim 387199989Srdivackypublic: 388276479Sdim /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling 389276479Sdim /// nodes without a corresponding SDNode. 390276479Sdim static const unsigned LowestSDNodeOrder = 1; 391276479Sdim 392199989Srdivacky SelectionDAG &DAG; 393327952Sdim const DataLayout *DL = nullptr; 394327952Sdim AliasAnalysis *AA = nullptr; 395234353Sdim const TargetLibraryInfo *LibInfo; 396199989Srdivacky 397353358Sdim class SDAGSwitchLowering : public SwitchCG::SwitchLowering { 398353358Sdim public: 399353358Sdim SDAGSwitchLowering(SelectionDAGBuilder *sdb, FunctionLoweringInfo &funcinfo) 400353358Sdim : SwitchCG::SwitchLowering(funcinfo), SDB(sdb) {} 401327952Sdim 402353358Sdim virtual void addSuccessorWithProb( 403353358Sdim MachineBasicBlock *Src, MachineBasicBlock *Dst, 404353358Sdim BranchProbability Prob = BranchProbability::getUnknown()) override { 405353358Sdim SDB->addSuccessorWithProb(Src, Dst, Prob); 406353358Sdim } 407327952Sdim 408353358Sdim private: 409353358Sdim SelectionDAGBuilder *SDB; 410353358Sdim }; 411327952Sdim 412353358Sdim std::unique_ptr<SDAGSwitchLowering> SL; 413353358Sdim 414261991Sdim /// A StackProtectorDescriptor structure used to communicate stack protector 415261991Sdim /// information in between SelectBasicBlock and FinishBasicBlock. 416261991Sdim StackProtectorDescriptor SPDescriptor; 417199989Srdivacky 418199989Srdivacky // Emit PHI-node-operand constants only once even if used by multiple 419199989Srdivacky // PHI nodes. 420207618Srdivacky DenseMap<const Constant *, unsigned> ConstantsOut; 421199989Srdivacky 422353358Sdim /// Information about the function as a whole. 423199989Srdivacky FunctionLoweringInfo &FuncInfo; 424199989Srdivacky 425353358Sdim /// Information about the swifterror values used throughout the function. 426353358Sdim SwiftErrorValueTracking &SwiftError; 427353358Sdim 428353358Sdim /// Garbage collection metadata for the function. 429199989Srdivacky GCFunctionInfo *GFI; 430199989Srdivacky 431353358Sdim /// Map a landing pad to the call site indexes. 432327952Sdim DenseMap<MachineBasicBlock *, SmallVector<unsigned, 4>> LPadToCallSiteMap; 433226633Sdim 434353358Sdim /// This is set to true if a call in the current block has been translated as 435353358Sdim /// a tail call. In this case, no subsequent DAG nodes should be created. 436327952Sdim bool HasTailCall = false; 437199989Srdivacky 438199989Srdivacky LLVMContext *Context; 439199989Srdivacky 440207618Srdivacky SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo, 441353358Sdim SwiftErrorValueTracking &swifterror, CodeGenOpt::Level ol) 442353358Sdim : SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()), DAG(dag), 443360784Sdim SL(std::make_unique<SDAGSwitchLowering>(this, funcinfo)), FuncInfo(funcinfo), 444353358Sdim SwiftError(swifterror) {} 445199989Srdivacky 446321369Sdim void init(GCFunctionInfo *gfi, AliasAnalysis *AA, 447234353Sdim const TargetLibraryInfo *li); 448199989Srdivacky 449321369Sdim /// Clear out the current SelectionDAG and the associated state and prepare 450321369Sdim /// this SelectionDAGBuilder object to be used for a new block. This doesn't 451321369Sdim /// clear out information about additional blocks that are needed to complete 452321369Sdim /// switch lowering or PHI node updating; that information is cleared out as 453321369Sdim /// it is consumed. 454199989Srdivacky void clear(); 455199989Srdivacky 456321369Sdim /// Clear the dangling debug information map. This function is separated from 457321369Sdim /// the clear so that debug information that is dangling in a basic block can 458321369Sdim /// be properly resolved in a different basic block. This allows the 459321369Sdim /// SelectionDAG to resolve dangling debug information attached to PHI nodes. 460223017Sdim void clearDanglingDebugInfo(); 461223017Sdim 462321369Sdim /// Return the current virtual root of the Selection DAG, flushing any 463321369Sdim /// PendingLoad items. This must be done before emitting a store or any other 464360784Sdim /// memory node that may need to be ordered after any prior load instructions. 465360784Sdim SDValue getMemoryRoot(); 466360784Sdim 467360784Sdim /// Similar to getMemoryRoot, but also flushes PendingConstrainedFP(Strict) 468360784Sdim /// items. This must be done before emitting any call other any other node 469360784Sdim /// that may need to be ordered after FP instructions due to other side 470360784Sdim /// effects. 471199989Srdivacky SDValue getRoot(); 472199989Srdivacky 473321369Sdim /// Similar to getRoot, but instead of flushing all the PendingLoad items, 474360784Sdim /// flush all the PendingExports (and PendingConstrainedFPStrict) items. 475360784Sdim /// It is necessary to do this before emitting a terminator instruction. 476199989Srdivacky SDValue getControlRoot(); 477199989Srdivacky 478261991Sdim SDLoc getCurSDLoc() const { 479261991Sdim return SDLoc(CurInst, SDNodeOrder); 480261991Sdim } 481219077Sdim 482261991Sdim DebugLoc getCurDebugLoc() const { 483261991Sdim return CurInst ? CurInst->getDebugLoc() : DebugLoc(); 484261991Sdim } 485261991Sdim 486207618Srdivacky void CopyValueToVirtualRegister(const Value *V, unsigned Reg); 487199989Srdivacky 488207618Srdivacky void visit(const Instruction &I); 489199989Srdivacky 490207618Srdivacky void visit(unsigned Opcode, const User &I); 491199989Srdivacky 492353358Sdim /// If there was virtual register allocated for the value V emit CopyFromReg 493353358Sdim /// of the specified type Ty. Return empty SDValue() otherwise. 494288943Sdim SDValue getCopyFromRegs(const Value *V, Type *Ty); 495288943Sdim 496341825Sdim /// If we have dangling debug info that describes \p Variable, or an 497341825Sdim /// overlapping part of variable considering the \p Expr, then this method 498353358Sdim /// will drop that debug info as it isn't valid any longer. 499341825Sdim void dropDanglingDebugInfo(const DILocalVariable *Variable, 500341825Sdim const DIExpression *Expr); 501341825Sdim 502353358Sdim /// If we saw an earlier dbg_value referring to V, generate the debug data 503353358Sdim /// structures now that we've seen its definition. 504212904Sdim void resolveDanglingDebugInfo(const Value *V, SDValue Val); 505327952Sdim 506353358Sdim /// For the given dangling debuginfo record, perform last-ditch efforts to 507353358Sdim /// resolve the debuginfo to something that is represented in this DAG. If 508353358Sdim /// this cannot be done, produce an Undef debug value record. 509353358Sdim void salvageUnresolvedDbgValue(DanglingDebugInfo &DDI); 510353358Sdim 511353358Sdim /// For a given Value, attempt to create and record a SDDbgValue in the 512353358Sdim /// SelectionDAG. 513353358Sdim bool handleDebugValue(const Value *V, DILocalVariable *Var, 514353358Sdim DIExpression *Expr, DebugLoc CurDL, 515353358Sdim DebugLoc InstDL, unsigned Order); 516353358Sdim 517353358Sdim /// Evict any dangling debug information, attempting to salvage it first. 518353358Sdim void resolveOrClearDbgInfo(); 519353358Sdim 520199989Srdivacky SDValue getValue(const Value *V); 521288943Sdim bool findValue(const Value *V) const; 522288943Sdim 523341825Sdim /// Return the SDNode for the specified IR value if it exists. 524341825Sdim SDNode *getNodeForIRValue(const Value *V) { 525341825Sdim if (NodeMap.find(V) == NodeMap.end()) 526341825Sdim return nullptr; 527341825Sdim return NodeMap[V].getNode(); 528341825Sdim } 529341825Sdim 530210299Sed SDValue getNonRegisterValue(const Value *V); 531210299Sed SDValue getValueImpl(const Value *V); 532199989Srdivacky 533199989Srdivacky void setValue(const Value *V, SDValue NewN) { 534199989Srdivacky SDValue &N = NodeMap[V]; 535276479Sdim assert(!N.getNode() && "Already set a value for this node!"); 536199989Srdivacky N = NewN; 537199989Srdivacky } 538261991Sdim 539210299Sed void setUnusedArgValue(const Value *V, SDValue NewN) { 540210299Sed SDValue &N = UnusedArgNodeMap[V]; 541276479Sdim assert(!N.getNode() && "Already set a value for this node!"); 542210299Sed N = NewN; 543210299Sed } 544199989Srdivacky 545207618Srdivacky void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, 546199989Srdivacky MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 547296417Sdim MachineBasicBlock *SwitchBB, 548341825Sdim Instruction::BinaryOps Opc, BranchProbability TProb, 549341825Sdim BranchProbability FProb, bool InvertCond); 550207618Srdivacky void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, 551199989Srdivacky MachineBasicBlock *FBB, 552207618Srdivacky MachineBasicBlock *CurBB, 553276479Sdim MachineBasicBlock *SwitchBB, 554341825Sdim BranchProbability TProb, BranchProbability FProb, 555321369Sdim bool InvertCond); 556353358Sdim bool ShouldEmitAsBranches(const std::vector<SwitchCG::CaseBlock> &Cases); 557207618Srdivacky bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB); 558207618Srdivacky void CopyToExportRegsIfNeeded(const Value *V); 559207618Srdivacky void ExportFromCurrentBlock(const Value *V); 560207618Srdivacky void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall, 561296417Sdim const BasicBlock *EHPadBB = nullptr); 562199989Srdivacky 563309124Sdim // Lower range metadata from 0 to N to assert zext to an integer of nearest 564309124Sdim // floor power of two. 565309124Sdim SDValue lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I, 566309124Sdim SDValue Op); 567261991Sdim 568309124Sdim void populateCallLoweringInfo(TargetLowering::CallLoweringInfo &CLI, 569353358Sdim const CallBase *Call, unsigned ArgIdx, 570309124Sdim unsigned NumArgs, SDValue Callee, 571309124Sdim Type *ReturnTy, bool IsPatchPoint); 572309124Sdim 573309124Sdim std::pair<SDValue, SDValue> 574309124Sdim lowerInvokable(TargetLowering::CallLoweringInfo &CLI, 575309124Sdim const BasicBlock *EHPadBB = nullptr); 576309124Sdim 577353358Sdim /// When an MBB was split during scheduling, update the 578276479Sdim /// references that need to refer to the last resulting block. 579218893Sdim void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last); 580218893Sdim 581309124Sdim /// Describes a gc.statepoint or a gc.statepoint like thing for the purposes 582309124Sdim /// of lowering into a STATEPOINT node. 583309124Sdim struct StatepointLoweringInfo { 584309124Sdim /// Bases[i] is the base pointer for Ptrs[i]. Together they denote the set 585309124Sdim /// of gc pointers this STATEPOINT has to relocate. 586309124Sdim SmallVector<const Value *, 16> Bases; 587309124Sdim SmallVector<const Value *, 16> Ptrs; 588309124Sdim 589309124Sdim /// The set of gc.relocate calls associated with this gc.statepoint. 590309124Sdim SmallVector<const GCRelocateInst *, 16> GCRelocates; 591309124Sdim 592309124Sdim /// The full list of gc arguments to the gc.statepoint being lowered. 593309124Sdim ArrayRef<const Use> GCArgs; 594309124Sdim 595309124Sdim /// The gc.statepoint instruction. 596309124Sdim const Instruction *StatepointInstr = nullptr; 597309124Sdim 598309124Sdim /// The list of gc transition arguments present in the gc.statepoint being 599309124Sdim /// lowered. 600309124Sdim ArrayRef<const Use> GCTransitionArgs; 601309124Sdim 602309124Sdim /// The ID that the resulting STATEPOINT instruction has to report. 603309124Sdim unsigned ID = -1; 604309124Sdim 605309124Sdim /// Information regarding the underlying call instruction. 606309124Sdim TargetLowering::CallLoweringInfo CLI; 607309124Sdim 608309124Sdim /// The deoptimization state associated with this gc.statepoint call, if 609309124Sdim /// any. 610309124Sdim ArrayRef<const Use> DeoptState; 611309124Sdim 612309124Sdim /// Flags associated with the meta arguments being lowered. 613309124Sdim uint64_t StatepointFlags = -1; 614309124Sdim 615309124Sdim /// The number of patchable bytes the call needs to get lowered into. 616309124Sdim unsigned NumPatchBytes = -1; 617309124Sdim 618309124Sdim /// The exception handling unwind destination, in case this represents an 619309124Sdim /// invoke of gc.statepoint. 620309124Sdim const BasicBlock *EHPadBB = nullptr; 621309124Sdim 622309124Sdim explicit StatepointLoweringInfo(SelectionDAG &DAG) : CLI(DAG) {} 623309124Sdim }; 624309124Sdim 625309124Sdim /// Lower \p SLI into a STATEPOINT instruction. 626341825Sdim SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SI); 627309124Sdim 628288943Sdim // This function is responsible for the whole statepoint lowering process. 629288943Sdim // It uniformly handles invoke and call statepoints. 630341825Sdim void LowerStatepoint(ImmutableStatepoint ISP, 631296417Sdim const BasicBlock *EHPadBB = nullptr); 632309124Sdim 633353358Sdim void LowerCallSiteWithDeoptBundle(const CallBase *Call, SDValue Callee, 634309124Sdim const BasicBlock *EHPadBB); 635309124Sdim 636309124Sdim void LowerDeoptimizeCall(const CallInst *CI); 637309124Sdim void LowerDeoptimizingReturn(); 638309124Sdim 639353358Sdim void LowerCallSiteWithDeoptBundleImpl(const CallBase *Call, SDValue Callee, 640309124Sdim const BasicBlock *EHPadBB, 641309124Sdim bool VarArgDisallowed, 642309124Sdim bool ForceVoidReturnTy); 643309124Sdim 644321369Sdim /// Returns the type of FrameIndex and TargetFrameIndex nodes. 645321369Sdim MVT getFrameIndexTy() { 646321369Sdim return DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout()); 647321369Sdim } 648321369Sdim 649199989Srdivackyprivate: 650199989Srdivacky // Terminator instructions. 651207618Srdivacky void visitRet(const ReturnInst &I); 652207618Srdivacky void visitBr(const BranchInst &I); 653207618Srdivacky void visitSwitch(const SwitchInst &I); 654207618Srdivacky void visitIndirectBr(const IndirectBrInst &I); 655276479Sdim void visitUnreachable(const UnreachableInst &I); 656296417Sdim void visitCleanupRet(const CleanupReturnInst &I); 657296417Sdim void visitCatchSwitch(const CatchSwitchInst &I); 658296417Sdim void visitCatchRet(const CatchReturnInst &I); 659296417Sdim void visitCatchPad(const CatchPadInst &I); 660296417Sdim void visitCleanupPad(const CleanupPadInst &CPI); 661199989Srdivacky 662296417Sdim BranchProbability getEdgeProbability(const MachineBasicBlock *Src, 663296417Sdim const MachineBasicBlock *Dst) const; 664296417Sdim void addSuccessorWithProb( 665296417Sdim MachineBasicBlock *Src, MachineBasicBlock *Dst, 666296417Sdim BranchProbability Prob = BranchProbability::getUnknown()); 667296417Sdim 668199989Srdivackypublic: 669353358Sdim void visitSwitchCase(SwitchCG::CaseBlock &CB, MachineBasicBlock *SwitchBB); 670261991Sdim void visitSPDescriptorParent(StackProtectorDescriptor &SPD, 671261991Sdim MachineBasicBlock *ParentBB); 672261991Sdim void visitSPDescriptorFailure(StackProtectorDescriptor &SPD); 673353358Sdim void visitBitTestHeader(SwitchCG::BitTestBlock &B, 674353358Sdim MachineBasicBlock *SwitchBB); 675353358Sdim void visitBitTestCase(SwitchCG::BitTestBlock &BB, MachineBasicBlock *NextMBB, 676353358Sdim BranchProbability BranchProbToNext, unsigned Reg, 677353358Sdim SwitchCG::BitTestCase &B, MachineBasicBlock *SwitchBB); 678353358Sdim void visitJumpTable(SwitchCG::JumpTable &JT); 679353358Sdim void visitJumpTableHeader(SwitchCG::JumpTable &JT, 680353358Sdim SwitchCG::JumpTableHeader &JTH, 681207618Srdivacky MachineBasicBlock *SwitchBB); 682261991Sdim 683199989Srdivackyprivate: 684199989Srdivacky // These all get lowered before this pass. 685207618Srdivacky void visitInvoke(const InvokeInst &I); 686353358Sdim void visitCallBr(const CallBrInst &I); 687226633Sdim void visitResume(const ResumeInst &I); 688199989Srdivacky 689344779Sdim void visitUnary(const User &I, unsigned Opcode); 690344779Sdim void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); } 691344779Sdim 692341825Sdim void visitBinary(const User &I, unsigned Opcode); 693207618Srdivacky void visitShift(const User &I, unsigned Opcode); 694207618Srdivacky void visitAdd(const User &I) { visitBinary(I, ISD::ADD); } 695207618Srdivacky void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); } 696207618Srdivacky void visitSub(const User &I) { visitBinary(I, ISD::SUB); } 697207618Srdivacky void visitFSub(const User &I); 698207618Srdivacky void visitMul(const User &I) { visitBinary(I, ISD::MUL); } 699207618Srdivacky void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); } 700207618Srdivacky void visitURem(const User &I) { visitBinary(I, ISD::UREM); } 701207618Srdivacky void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } 702207618Srdivacky void visitFRem(const User &I) { visitBinary(I, ISD::FREM); } 703207618Srdivacky void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); } 704224145Sdim void visitSDiv(const User &I); 705207618Srdivacky void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); } 706207618Srdivacky void visitAnd (const User &I) { visitBinary(I, ISD::AND); } 707207618Srdivacky void visitOr (const User &I) { visitBinary(I, ISD::OR); } 708207618Srdivacky void visitXor (const User &I) { visitBinary(I, ISD::XOR); } 709207618Srdivacky void visitShl (const User &I) { visitShift(I, ISD::SHL); } 710207618Srdivacky void visitLShr(const User &I) { visitShift(I, ISD::SRL); } 711207618Srdivacky void visitAShr(const User &I) { visitShift(I, ISD::SRA); } 712207618Srdivacky void visitICmp(const User &I); 713207618Srdivacky void visitFCmp(const User &I); 714199989Srdivacky // Visit the conversion instructions 715207618Srdivacky void visitTrunc(const User &I); 716207618Srdivacky void visitZExt(const User &I); 717207618Srdivacky void visitSExt(const User &I); 718207618Srdivacky void visitFPTrunc(const User &I); 719207618Srdivacky void visitFPExt(const User &I); 720207618Srdivacky void visitFPToUI(const User &I); 721207618Srdivacky void visitFPToSI(const User &I); 722207618Srdivacky void visitUIToFP(const User &I); 723207618Srdivacky void visitSIToFP(const User &I); 724207618Srdivacky void visitPtrToInt(const User &I); 725207618Srdivacky void visitIntToPtr(const User &I); 726207618Srdivacky void visitBitCast(const User &I); 727261991Sdim void visitAddrSpaceCast(const User &I); 728199989Srdivacky 729207618Srdivacky void visitExtractElement(const User &I); 730207618Srdivacky void visitInsertElement(const User &I); 731207618Srdivacky void visitShuffleVector(const User &I); 732199989Srdivacky 733321369Sdim void visitExtractValue(const User &I); 734321369Sdim void visitInsertValue(const User &I); 735341825Sdim void visitLandingPad(const LandingPadInst &LP); 736199989Srdivacky 737207618Srdivacky void visitGetElementPtr(const User &I); 738207618Srdivacky void visitSelect(const User &I); 739199989Srdivacky 740207618Srdivacky void visitAlloca(const AllocaInst &I); 741207618Srdivacky void visitLoad(const LoadInst &I); 742207618Srdivacky void visitStore(const StoreInst &I); 743314564Sdim void visitMaskedLoad(const CallInst &I, bool IsExpanding = false); 744314564Sdim void visitMaskedStore(const CallInst &I, bool IsCompressing = false); 745288943Sdim void visitMaskedGather(const CallInst &I); 746288943Sdim void visitMaskedScatter(const CallInst &I); 747226633Sdim void visitAtomicCmpXchg(const AtomicCmpXchgInst &I); 748226633Sdim void visitAtomicRMW(const AtomicRMWInst &I); 749226633Sdim void visitFence(const FenceInst &I); 750207618Srdivacky void visitPHI(const PHINode &I); 751207618Srdivacky void visitCall(const CallInst &I); 752207618Srdivacky bool visitMemCmpCall(const CallInst &I); 753314564Sdim bool visitMemPCpyCall(const CallInst &I); 754261991Sdim bool visitMemChrCall(const CallInst &I); 755261991Sdim bool visitStrCpyCall(const CallInst &I, bool isStpcpy); 756261991Sdim bool visitStrCmpCall(const CallInst &I); 757261991Sdim bool visitStrLenCall(const CallInst &I); 758261991Sdim bool visitStrNLenCall(const CallInst &I); 759239462Sdim bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode); 760280031Sdim bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode); 761226633Sdim void visitAtomicLoad(const LoadInst &I); 762226633Sdim void visitAtomicStore(const StoreInst &I); 763309124Sdim void visitLoadFromSwiftError(const LoadInst &I); 764309124Sdim void visitStoreToSwiftError(const StoreInst &I); 765360784Sdim void visitFreeze(const FreezeInst &I); 766226633Sdim 767207618Srdivacky void visitInlineAsm(ImmutableCallSite CS); 768353358Sdim void visitIntrinsicCall(const CallInst &I, unsigned Intrinsic); 769207618Srdivacky void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic); 770321369Sdim void visitConstrainedFPIntrinsic(const ConstrainedFPIntrinsic &FPI); 771199989Srdivacky 772207618Srdivacky void visitVAStart(const CallInst &I); 773207618Srdivacky void visitVAArg(const VAArgInst &I); 774207618Srdivacky void visitVAEnd(const CallInst &I); 775207618Srdivacky void visitVACopy(const CallInst &I); 776261991Sdim void visitStackmap(const CallInst &I); 777280031Sdim void visitPatchpoint(ImmutableCallSite CS, 778296417Sdim const BasicBlock *EHPadBB = nullptr); 779199989Srdivacky 780309124Sdim // These two are implemented in StatepointLowering.cpp 781341825Sdim void visitGCRelocate(const GCRelocateInst &Relocate); 782309124Sdim void visitGCResult(const GCResultInst &I); 783280031Sdim 784321369Sdim void visitVectorReduce(const CallInst &I, unsigned Intrinsic); 785321369Sdim 786207618Srdivacky void visitUserOp1(const Instruction &I) { 787199989Srdivacky llvm_unreachable("UserOp1 should not exist at instruction selection time!"); 788199989Srdivacky } 789207618Srdivacky void visitUserOp2(const Instruction &I) { 790199989Srdivacky llvm_unreachable("UserOp2 should not exist at instruction selection time!"); 791199989Srdivacky } 792207618Srdivacky 793261991Sdim void processIntegerCallValue(const Instruction &I, 794261991Sdim SDValue Value, bool IsSigned); 795261991Sdim 796207618Srdivacky void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB); 797207618Srdivacky 798309124Sdim void emitInlineAsmError(ImmutableCallSite CS, const Twine &Message); 799309124Sdim 800327952Sdim /// If V is an function argument then create corresponding DBG_VALUE machine 801327952Sdim /// instruction for it now. At the end of instruction selection, they will be 802327952Sdim /// inserted to the entry BB. 803288943Sdim bool EmitFuncArgumentDbgValue(const Value *V, DILocalVariable *Variable, 804288943Sdim DIExpression *Expr, DILocation *DL, 805327952Sdim bool IsDbgDeclare, const SDValue &N); 806288943Sdim 807288943Sdim /// Return the next block after MBB, or nullptr if there is none. 808288943Sdim MachineBasicBlock *NextBlock(MachineBasicBlock *MBB); 809288943Sdim 810288943Sdim /// Update the DAG and DAG builder with the relevant information after 811288943Sdim /// a new root node has been created which could be a tail call. 812288943Sdim void updateDAGForMaybeTailCall(SDValue MaybeTC); 813314564Sdim 814314564Sdim /// Return the appropriate SDDbgValue based on N. 815314564Sdim SDDbgValue *getDbgValue(SDValue N, DILocalVariable *Variable, 816327952Sdim DIExpression *Expr, const DebugLoc &dl, 817327952Sdim unsigned DbgSDNodeOrder); 818353358Sdim 819353358Sdim /// Lowers CallInst to an external symbol. 820353358Sdim void lowerCallToExternalSymbol(const CallInst &I, const char *FunctionName); 821199989Srdivacky}; 822199989Srdivacky 823353358Sdim/// This struct represents the registers (physical or virtual) 824288943Sdim/// that a particular set of values is assigned, and the type information about 825288943Sdim/// the value. The most common situation is to represent one value at a time, 826288943Sdim/// but struct or array values are handled element-wise as multiple values. The 827288943Sdim/// splitting of aggregates is performed recursively, so that we never have 828288943Sdim/// aggregate-typed registers. The values at this point do not necessarily have 829288943Sdim/// legal types, so each value may require one or more registers of some legal 830288943Sdim/// type. 831288943Sdim/// 832288943Sdimstruct RegsForValue { 833321369Sdim /// The value types of the values, which may not be legal, and 834288943Sdim /// may need be promoted or synthesized from one or more registers. 835288943Sdim SmallVector<EVT, 4> ValueVTs; 836288943Sdim 837321369Sdim /// The value types of the registers. This is the same size as ValueVTs and it 838321369Sdim /// records, for each value, what the type of the assigned register or 839321369Sdim /// registers are. (Individual values are never synthesized from more than one 840321369Sdim /// type of register.) 841288943Sdim /// 842288943Sdim /// With virtual registers, the contents of RegVTs is redundant with TLI's 843288943Sdim /// getRegisterType member function, however when with physical registers 844288943Sdim /// it is necessary to have a separate record of the types. 845288943Sdim SmallVector<MVT, 4> RegVTs; 846288943Sdim 847321369Sdim /// This list holds the registers assigned to the values. 848288943Sdim /// Each legal or promoted value requires one register, and each 849288943Sdim /// expanded value requires multiple registers. 850288943Sdim SmallVector<unsigned, 4> Regs; 851288943Sdim 852321369Sdim /// This list holds the number of registers for each value. 853321369Sdim SmallVector<unsigned, 4> RegCount; 854321369Sdim 855321369Sdim /// Records if this value needs to be treated in an ABI dependant manner, 856321369Sdim /// different to normal type legalization. 857341825Sdim Optional<CallingConv::ID> CallConv; 858321369Sdim 859327952Sdim RegsForValue() = default; 860321369Sdim RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt, 861341825Sdim Optional<CallingConv::ID> CC = None); 862288943Sdim RegsForValue(LLVMContext &Context, const TargetLowering &TLI, 863321369Sdim const DataLayout &DL, unsigned Reg, Type *Ty, 864341825Sdim Optional<CallingConv::ID> CC); 865288943Sdim 866341825Sdim bool isABIMangled() const { 867341825Sdim return CallConv.hasValue(); 868341825Sdim } 869341825Sdim 870321369Sdim /// Add the specified values to this one. 871288943Sdim void append(const RegsForValue &RHS) { 872288943Sdim ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 873288943Sdim RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 874288943Sdim Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 875321369Sdim RegCount.push_back(RHS.Regs.size()); 876288943Sdim } 877288943Sdim 878321369Sdim /// Emit a series of CopyFromReg nodes that copies from this value and returns 879321369Sdim /// the result as a ValueVTs value. This uses Chain/Flag as the input and 880321369Sdim /// updates them for the output Chain/Flag. If the Flag pointer is NULL, no 881321369Sdim /// flag is used. 882288943Sdim SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 883309124Sdim const SDLoc &dl, SDValue &Chain, SDValue *Flag, 884288943Sdim const Value *V = nullptr) const; 885288943Sdim 886321369Sdim /// Emit a series of CopyToReg nodes that copies the specified value into the 887321369Sdim /// registers specified by this object. This uses Chain/Flag as the input and 888321369Sdim /// updates them for the output Chain/Flag. If the Flag pointer is nullptr, no 889321369Sdim /// flag is used. If V is not nullptr, then it is used in printing better 890321369Sdim /// diagnostic messages on error. 891309124Sdim void getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl, 892309124Sdim SDValue &Chain, SDValue *Flag, const Value *V = nullptr, 893309124Sdim ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const; 894288943Sdim 895321369Sdim /// Add this value to the specified inlineasm node operand list. This adds the 896321369Sdim /// code marker, matching input operand index (if applicable), and includes 897321369Sdim /// the number of values added into it. 898341825Sdim void AddInlineAsmOperands(unsigned Code, bool HasMatching, 899309124Sdim unsigned MatchingIdx, const SDLoc &dl, 900309124Sdim SelectionDAG &DAG, std::vector<SDValue> &Ops) const; 901341825Sdim 902341825Sdim /// Check if the total RegCount is greater than one. 903341825Sdim bool occupiesMultipleRegs() const { 904341825Sdim return std::accumulate(RegCount.begin(), RegCount.end(), 0) > 1; 905341825Sdim } 906341825Sdim 907341825Sdim /// Return a list of registers and their sizes. 908341825Sdim SmallVector<std::pair<unsigned, unsigned>, 4> getRegsAndSizes() const; 909288943Sdim}; 910288943Sdim 911199989Srdivacky} // end namespace llvm 912199989Srdivacky 913327952Sdim#endif // LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H 914