Lines Matching refs:Regs
212 RegUnitIterator(const CodeGenRegister::Vec &Regs):
213 RegI(Regs.begin()), RegE(Regs.end()) {
1114 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
1115 llvm::sort(Regs, LessRecordRegister());
1117 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1118 getReg(Regs[i]);
1570 CodeGenRegister::Vec Regs;
1599 const CodeGenRegister::Vec &Regs = RegClass.getMembers();
1600 if (Regs.empty())
1603 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue);
1606 AllocatableRegs.insert((*Regs.begin())->EnumValue);
1607 for (auto I = std::next(Regs.begin()), E = Regs.end(); I != E; ++I) {
1637 USet->Regs.push_back(&Reg);
1638 sortAndUniqueRegisters(USet->Regs);
1653 for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) {
1675 : I->Regs) dbgs()
1683 for (const auto R : I->Regs) {
2386 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
2389 // First add Regs with all sub-registers.
2390 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2391 CodeGenRegister *Reg = getReg(Regs[i]);