Searched refs:ROTL (Results 1 - 25 of 33) sorted by relevance

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/freebsd-11-stable/crypto/openssl/crypto/cast/
H A Dcast_lcl.h154 # define ROTL(a,n) (_lrotl(a,n)) macro
156 # define ROTL(a,n) ((((a)<<(n))&0xffffffffL)|((a)>>((32-(n))&31))) macro
158 # define ROTL(a,n) ((((a)<<(n))&0xffffffffL)|((a)>>(32-(n)))) macro
174 t=ROTL(t,i); \
191 w=ROTL(w,i); \
211 t=ROTL(t,(key[n*2+1])); \
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2294 { ISD::ROTL, MVT::v8i64, 1 },
2295 { ISD::ROTL, MVT::v4i64, 1 },
2296 { ISD::ROTL, MVT::v2i64, 1 },
2297 { ISD::ROTL, MVT::v16i32, 1 },
2298 { ISD::ROTL, MVT::v8i32, 1 },
2299 { ISD::ROTL, MVT::v4i32, 1 },
2307 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y))
2309 { ISD::ROTL, MVT::v4i64, 4 },
2310 { ISD::ROTL, MVT::v8i32, 4 },
2311 { ISD::ROTL, MV
[all...]
H A DX86ISelDAGToDAG.cpp687 if (U0.getOpcode() == ISD::ROTL) {
693 if (U1.getOpcode() == ISD::ROTL) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp91 setOperationAction(ISD::ROTL, MVT::i8, Custom);
92 setOperationAction(ISD::ROTL, MVT::i16, Expand);
297 case ISD::ROTL:
316 case ISD::ROTL:
690 case ISD::ROTL:
/freebsd-11-stable/crypto/openssl/crypto/bn/asm/
H A Dppc.pl126 $ROTL= "rotlwi"; # rotate left by immediate
150 $ROTL= "rotldi"; # rotate left by immediate
1719 $ROTL r3,r11,`$BITS/2` # rotate by $BITS/2 and store in r3
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp95 setOperationAction(ISD::ROTL, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp244 case ISD::ROTL: return "rotl";
H A DLegalizeVectorOps.cpp390 case ISD::ROTL:
920 case ISD::ROTL:
H A DLegalizeDAG.cpp1180 case ISD::ROTL:
2672 return DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
3405 case ISD::ROTL:
H A DDAGCombiner.cpp1550 case ISD::ROTL: return visitRotate(N);
5713 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
5714 return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt);
6266 bool HasROTL = hasOperation(ISD::ROTL, VT);
6344 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
6390 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
6395 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
7205 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT) && N0Opcode == ISD::SHL &&
7207 return DAG.getNode(ISD::ROTL, DL, VT, DAG.getConstant(~1, DL, VT),
7433 if (NextOp == ISD::ROTL || NextO
[all...]
H A DTargetLowering.cpp2568 case ISD::ROTL:
5989 bool IsLeft = Node->getOpcode() == ISD::ROTL;
5998 unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL;
H A DLegalizeIntegerTypes.cpp1305 case ISD::ROTL:
3790 case ISD::ROTL:
H A DSelectionDAG.cpp3754 case ISD::ROTL:
4797 case ISD::ROTL: return C1.rotl(C2);
5231 case ISD::ROTL:
9300 case ISD::ROTL:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1429 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1478 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1615 setOperationAction(ISD::ROTL, MVT::i32, Legal);
1616 setOperationAction(ISD::ROTL, MVT::i64, Legal);
2920 case ISD::ROTL: return LowerROTL(Op, DAG);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp82 setOperationAction(ISD::ROTL, MVT::i8, Expand);
84 setOperationAction(ISD::ROTL, MVT::i16, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp832 case ISD::ROTL: {
1522 case ISD::ROTL:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp421 // TODO: we may consider expanding ROTL/ROTR on older GPUs. Currently on GPUs
424 setOperationAction(ISD::ROTL, MVT::i64, Legal);
426 setOperationAction(ISD::ROTL, MVT::i32, Legal);
429 setOperationAction(ISD::ROTL, MVT::i16, Expand);
431 setOperationAction(ISD::ROTL, MVT::i8, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp120 setOperationAction(ISD::ROTL, MVT::i32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp614 } else if (Opcode == ISD::ROTL) {
1228 case ISD::ROTL:
3676 case ISD::ROTL:
4398 N->getOperand(0).getOpcode() != ISD::ROTL) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp332 // The hardware supports 32-bit ROTR, but not ROTL.
333 setOperationAction(ISD::ROTL, MVT::i32, Expand);
334 setOperationAction(ISD::ROTL, MVT::i64, Expand);
373 setOperationAction(ISD::ROTL, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp177 ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp108 setOperationAction(ISD::ROTL , MVT::i32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1570 setOperationAction(ISD::ROTL , MVT::i64, Expand);
1633 setOperationAction(ISD::ROTL , MVT::i32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp423 setOperationAction(ISD::ROTL, MVT::i32, Expand);
424 setOperationAction(ISD::ROTL, MVT::i64, Expand);

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