1251607Sdim//===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===// 2251607Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6251607Sdim// 7251607Sdim//===----------------------------------------------------------------------===// 8251607Sdim// 9251607Sdim// This file defines an instruction selector for the SystemZ target. 10251607Sdim// 11251607Sdim//===----------------------------------------------------------------------===// 12251607Sdim 13251607Sdim#include "SystemZTargetMachine.h" 14353358Sdim#include "SystemZISelLowering.h" 15261991Sdim#include "llvm/Analysis/AliasAnalysis.h" 16251607Sdim#include "llvm/CodeGen/SelectionDAGISel.h" 17251607Sdim#include "llvm/Support/Debug.h" 18321369Sdim#include "llvm/Support/KnownBits.h" 19251607Sdim#include "llvm/Support/raw_ostream.h" 20251607Sdim 21251607Sdimusing namespace llvm; 22251607Sdim 23276479Sdim#define DEBUG_TYPE "systemz-isel" 24276479Sdim 25251607Sdimnamespace { 26251607Sdim// Used to build addressing modes. 27251607Sdimstruct SystemZAddressingMode { 28251607Sdim // The shape of the address. 29251607Sdim enum AddrForm { 30251607Sdim // base+displacement 31251607Sdim FormBD, 32251607Sdim 33251607Sdim // base+displacement+index for load and store operands 34251607Sdim FormBDXNormal, 35251607Sdim 36251607Sdim // base+displacement+index for load address operands 37251607Sdim FormBDXLA, 38251607Sdim 39251607Sdim // base+displacement+index+ADJDYNALLOC 40251607Sdim FormBDXDynAlloc 41251607Sdim }; 42251607Sdim AddrForm Form; 43251607Sdim 44251607Sdim // The type of displacement. The enum names here correspond directly 45251607Sdim // to the definitions in SystemZOperand.td. We could split them into 46251607Sdim // flags -- single/pair, 128-bit, etc. -- but it hardly seems worth it. 47251607Sdim enum DispRange { 48251607Sdim Disp12Only, 49251607Sdim Disp12Pair, 50251607Sdim Disp20Only, 51251607Sdim Disp20Only128, 52251607Sdim Disp20Pair 53251607Sdim }; 54251607Sdim DispRange DR; 55251607Sdim 56251607Sdim // The parts of the address. The address is equivalent to: 57251607Sdim // 58251607Sdim // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0) 59251607Sdim SDValue Base; 60251607Sdim int64_t Disp; 61251607Sdim SDValue Index; 62251607Sdim bool IncludesDynAlloc; 63251607Sdim 64251607Sdim SystemZAddressingMode(AddrForm form, DispRange dr) 65251607Sdim : Form(form), DR(dr), Base(), Disp(0), Index(), 66251607Sdim IncludesDynAlloc(false) {} 67251607Sdim 68251607Sdim // True if the address can have an index register. 69251607Sdim bool hasIndexField() { return Form != FormBD; } 70251607Sdim 71251607Sdim // True if the address can (and must) include ADJDYNALLOC. 72251607Sdim bool isDynAlloc() { return Form == FormBDXDynAlloc; } 73251607Sdim 74344779Sdim void dump(const llvm::SelectionDAG *DAG) { 75251607Sdim errs() << "SystemZAddressingMode " << this << '\n'; 76251607Sdim 77251607Sdim errs() << " Base "; 78276479Sdim if (Base.getNode()) 79344779Sdim Base.getNode()->dump(DAG); 80251607Sdim else 81251607Sdim errs() << "null\n"; 82251607Sdim 83251607Sdim if (hasIndexField()) { 84251607Sdim errs() << " Index "; 85276479Sdim if (Index.getNode()) 86344779Sdim Index.getNode()->dump(DAG); 87251607Sdim else 88251607Sdim errs() << "null\n"; 89251607Sdim } 90251607Sdim 91251607Sdim errs() << " Disp " << Disp; 92251607Sdim if (IncludesDynAlloc) 93251607Sdim errs() << " + ADJDYNALLOC"; 94251607Sdim errs() << '\n'; 95251607Sdim } 96251607Sdim}; 97251607Sdim 98261991Sdim// Return a mask with Count low bits set. 99261991Sdimstatic uint64_t allOnes(unsigned int Count) { 100288943Sdim assert(Count <= 64); 101288943Sdim if (Count > 63) 102288943Sdim return UINT64_MAX; 103288943Sdim return (uint64_t(1) << Count) - 1; 104261991Sdim} 105261991Sdim 106261991Sdim// Represents operands 2 to 5 of the ROTATE AND ... SELECTED BITS operation 107261991Sdim// given by Opcode. The operands are: Input (R2), Start (I3), End (I4) and 108261991Sdim// Rotate (I5). The combined operand value is effectively: 109261991Sdim// 110261991Sdim// (or (rotl Input, Rotate), ~Mask) 111261991Sdim// 112261991Sdim// for RNSBG and: 113261991Sdim// 114261991Sdim// (and (rotl Input, Rotate), Mask) 115261991Sdim// 116261991Sdim// otherwise. The output value has BitSize bits, although Input may be 117309124Sdim// narrower (in which case the upper bits are don't care), or wider (in which 118309124Sdim// case the result will be truncated as part of the operation). 119261991Sdimstruct RxSBGOperands { 120261991Sdim RxSBGOperands(unsigned Op, SDValue N) 121314564Sdim : Opcode(Op), BitSize(N.getValueSizeInBits()), 122261991Sdim Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63), 123261991Sdim Rotate(0) {} 124261991Sdim 125261991Sdim unsigned Opcode; 126261991Sdim unsigned BitSize; 127261991Sdim uint64_t Mask; 128261991Sdim SDValue Input; 129261991Sdim unsigned Start; 130261991Sdim unsigned End; 131261991Sdim unsigned Rotate; 132261991Sdim}; 133261991Sdim 134251607Sdimclass SystemZDAGToDAGISel : public SelectionDAGISel { 135288943Sdim const SystemZSubtarget *Subtarget; 136251607Sdim 137251607Sdim // Used by SystemZOperands.td to create integer constants. 138261991Sdim inline SDValue getImm(const SDNode *Node, uint64_t Imm) const { 139288943Sdim return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0)); 140251607Sdim } 141251607Sdim 142261991Sdim const SystemZTargetMachine &getTargetMachine() const { 143261991Sdim return static_cast<const SystemZTargetMachine &>(TM); 144261991Sdim } 145261991Sdim 146261991Sdim const SystemZInstrInfo *getInstrInfo() const { 147288943Sdim return Subtarget->getInstrInfo(); 148261991Sdim } 149261991Sdim 150251607Sdim // Try to fold more of the base or index of AM into AM, where IsBase 151251607Sdim // selects between the base and index. 152261991Sdim bool expandAddress(SystemZAddressingMode &AM, bool IsBase) const; 153251607Sdim 154251607Sdim // Try to describe N in AM, returning true on success. 155261991Sdim bool selectAddress(SDValue N, SystemZAddressingMode &AM) const; 156251607Sdim 157251607Sdim // Extract individual target operands from matched address AM. 158251607Sdim void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 159261991Sdim SDValue &Base, SDValue &Disp) const; 160251607Sdim void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 161261991Sdim SDValue &Base, SDValue &Disp, SDValue &Index) const; 162251607Sdim 163251607Sdim // Try to match Addr as a FormBD address with displacement type DR. 164251607Sdim // Return true on success, storing the base and displacement in 165251607Sdim // Base and Disp respectively. 166251607Sdim bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, 167261991Sdim SDValue &Base, SDValue &Disp) const; 168251607Sdim 169261991Sdim // Try to match Addr as a FormBDX address with displacement type DR. 170261991Sdim // Return true on success and if the result had no index. Store the 171261991Sdim // base and displacement in Base and Disp respectively. 172261991Sdim bool selectMVIAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, 173261991Sdim SDValue &Base, SDValue &Disp) const; 174261991Sdim 175251607Sdim // Try to match Addr as a FormBDX* address of form Form with 176251607Sdim // displacement type DR. Return true on success, storing the base, 177251607Sdim // displacement and index in Base, Disp and Index respectively. 178251607Sdim bool selectBDXAddr(SystemZAddressingMode::AddrForm Form, 179251607Sdim SystemZAddressingMode::DispRange DR, SDValue Addr, 180261991Sdim SDValue &Base, SDValue &Disp, SDValue &Index) const; 181251607Sdim 182251607Sdim // PC-relative address matching routines used by SystemZOperands.td. 183261991Sdim bool selectPCRelAddress(SDValue Addr, SDValue &Target) const { 184261991Sdim if (SystemZISD::isPCREL(Addr.getOpcode())) { 185251607Sdim Target = Addr.getOperand(0); 186251607Sdim return true; 187251607Sdim } 188251607Sdim return false; 189251607Sdim } 190251607Sdim 191251607Sdim // BD matching routines used by SystemZOperands.td. 192261991Sdim bool selectBDAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp) const { 193251607Sdim return selectBDAddr(SystemZAddressingMode::Disp12Only, Addr, Base, Disp); 194251607Sdim } 195261991Sdim bool selectBDAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 196251607Sdim return selectBDAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp); 197251607Sdim } 198261991Sdim bool selectBDAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp) const { 199251607Sdim return selectBDAddr(SystemZAddressingMode::Disp20Only, Addr, Base, Disp); 200251607Sdim } 201261991Sdim bool selectBDAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 202251607Sdim return selectBDAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp); 203251607Sdim } 204251607Sdim 205261991Sdim // MVI matching routines used by SystemZOperands.td. 206261991Sdim bool selectMVIAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 207261991Sdim return selectMVIAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp); 208261991Sdim } 209261991Sdim bool selectMVIAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 210261991Sdim return selectMVIAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp); 211261991Sdim } 212261991Sdim 213251607Sdim // BDX matching routines used by SystemZOperands.td. 214251607Sdim bool selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp, 215261991Sdim SDValue &Index) const { 216251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 217251607Sdim SystemZAddressingMode::Disp12Only, 218251607Sdim Addr, Base, Disp, Index); 219251607Sdim } 220251607Sdim bool selectBDXAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 221261991Sdim SDValue &Index) const { 222251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 223251607Sdim SystemZAddressingMode::Disp12Pair, 224251607Sdim Addr, Base, Disp, Index); 225251607Sdim } 226251607Sdim bool selectDynAlloc12Only(SDValue Addr, SDValue &Base, SDValue &Disp, 227261991Sdim SDValue &Index) const { 228251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXDynAlloc, 229251607Sdim SystemZAddressingMode::Disp12Only, 230251607Sdim Addr, Base, Disp, Index); 231251607Sdim } 232251607Sdim bool selectBDXAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp, 233261991Sdim SDValue &Index) const { 234251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 235251607Sdim SystemZAddressingMode::Disp20Only, 236251607Sdim Addr, Base, Disp, Index); 237251607Sdim } 238251607Sdim bool selectBDXAddr20Only128(SDValue Addr, SDValue &Base, SDValue &Disp, 239261991Sdim SDValue &Index) const { 240251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 241251607Sdim SystemZAddressingMode::Disp20Only128, 242251607Sdim Addr, Base, Disp, Index); 243251607Sdim } 244251607Sdim bool selectBDXAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 245261991Sdim SDValue &Index) const { 246251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 247251607Sdim SystemZAddressingMode::Disp20Pair, 248251607Sdim Addr, Base, Disp, Index); 249251607Sdim } 250251607Sdim bool selectLAAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 251261991Sdim SDValue &Index) const { 252251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXLA, 253251607Sdim SystemZAddressingMode::Disp12Pair, 254251607Sdim Addr, Base, Disp, Index); 255251607Sdim } 256251607Sdim bool selectLAAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 257261991Sdim SDValue &Index) const { 258251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXLA, 259251607Sdim SystemZAddressingMode::Disp20Pair, 260251607Sdim Addr, Base, Disp, Index); 261251607Sdim } 262251607Sdim 263288943Sdim // Try to match Addr as an address with a base, 12-bit displacement 264288943Sdim // and index, where the index is element Elem of a vector. 265288943Sdim // Return true on success, storing the base, displacement and vector 266288943Sdim // in Base, Disp and Index respectively. 267288943Sdim bool selectBDVAddr12Only(SDValue Addr, SDValue Elem, SDValue &Base, 268288943Sdim SDValue &Disp, SDValue &Index) const; 269288943Sdim 270261991Sdim // Check whether (or Op (and X InsertMask)) is effectively an insertion 271261991Sdim // of X into bits InsertMask of some Y != Op. Return true if so and 272261991Sdim // set Op to that Y. 273261991Sdim bool detectOrAndInsertion(SDValue &Op, uint64_t InsertMask) const; 274261991Sdim 275261991Sdim // Try to update RxSBG so that only the bits of RxSBG.Input in Mask are used. 276261991Sdim // Return true on success. 277261991Sdim bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask) const; 278261991Sdim 279261991Sdim // Try to fold some of RxSBG.Input into other fields of RxSBG. 280261991Sdim // Return true on success. 281261991Sdim bool expandRxSBG(RxSBGOperands &RxSBG) const; 282261991Sdim 283261991Sdim // Return an undefined value of type VT. 284309124Sdim SDValue getUNDEF(const SDLoc &DL, EVT VT) const; 285261991Sdim 286261991Sdim // Convert N to VT, if it isn't already. 287309124Sdim SDValue convertTo(const SDLoc &DL, EVT VT, SDValue N) const; 288261991Sdim 289261991Sdim // Try to implement AND or shift node N using RISBG with the zero flag set. 290261991Sdim // Return the selected node on success, otherwise return null. 291309124Sdim bool tryRISBGZero(SDNode *N); 292261991Sdim 293261991Sdim // Try to use RISBG or Opcode to implement OR or XOR node N. 294261991Sdim // Return the selected node on success, otherwise return null. 295309124Sdim bool tryRxSBG(SDNode *N, unsigned Opcode); 296261991Sdim 297251607Sdim // If Op0 is null, then Node is a constant that can be loaded using: 298251607Sdim // 299251607Sdim // (Opcode UpperVal LowerVal) 300251607Sdim // 301251607Sdim // If Op0 is nonnull, then Node can be implemented using: 302251607Sdim // 303251607Sdim // (Opcode (Opcode Op0 UpperVal) LowerVal) 304309124Sdim void splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, 305309124Sdim uint64_t UpperVal, uint64_t LowerVal); 306251607Sdim 307353358Sdim void loadVectorConstant(const SystemZVectorConstantInfo &VCI, 308353358Sdim SDNode *Node); 309353358Sdim 310288943Sdim // Try to use gather instruction Opcode to implement vector insertion N. 311309124Sdim bool tryGather(SDNode *N, unsigned Opcode); 312288943Sdim 313288943Sdim // Try to use scatter instruction Opcode to implement store Store. 314309124Sdim bool tryScatter(StoreSDNode *Store, unsigned Opcode); 315288943Sdim 316341825Sdim // Change a chain of {load; op; store} of the same value into a simple op 317341825Sdim // through memory of that value, if the uses of the modified value and its 318341825Sdim // address are suitable. 319341825Sdim bool tryFoldLoadStoreIntoMemOperand(SDNode *Node); 320341825Sdim 321261991Sdim // Return true if Load and Store are loads and stores of the same size 322261991Sdim // and are guaranteed not to overlap. Such operations can be implemented 323261991Sdim // using block (SS-format) instructions. 324261991Sdim // 325261991Sdim // Partial overlap would lead to incorrect code, since the block operations 326261991Sdim // are logically bytewise, even though they have a fast path for the 327261991Sdim // non-overlapping case. We also need to avoid full overlap (i.e. two 328261991Sdim // addresses that might be equal at run time) because although that case 329261991Sdim // would be handled correctly, it might be implemented by millicode. 330261991Sdim bool canUseBlockOperation(StoreSDNode *Store, LoadSDNode *Load) const; 331261991Sdim 332261991Sdim // N is a (store (load Y), X) pattern. Return true if it can use an MVC 333261991Sdim // from Y to X. 334261991Sdim bool storeLoadCanUseMVC(SDNode *N) const; 335261991Sdim 336261991Sdim // N is a (store (op (load A[0]), (load A[1])), X) pattern. Return true 337261991Sdim // if A[1 - I] == X and if N can use a block operation like NC from A[I] 338261991Sdim // to X. 339261991Sdim bool storeLoadCanUseBlockBinary(SDNode *N, unsigned I) const; 340261991Sdim 341341825Sdim // Try to expand a boolean SELECT_CCMASK using an IPM sequence. 342341825Sdim SDValue expandSelectBoolean(SDNode *Node); 343341825Sdim 344251607Sdimpublic: 345251607Sdim SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel) 346288943Sdim : SelectionDAGISel(TM, OptLevel) {} 347251607Sdim 348288943Sdim bool runOnMachineFunction(MachineFunction &MF) override { 349360784Sdim const Function &F = MF.getFunction(); 350360784Sdim if (F.getFnAttribute("fentry-call").getValueAsString() != "true") { 351360784Sdim if (F.hasFnAttribute("mnop-mcount")) 352360784Sdim report_fatal_error("mnop-mcount only supported with fentry-call"); 353360784Sdim if (F.hasFnAttribute("mrecord-mcount")) 354360784Sdim report_fatal_error("mrecord-mcount only supported with fentry-call"); 355360784Sdim } 356360784Sdim 357288943Sdim Subtarget = &MF.getSubtarget<SystemZSubtarget>(); 358288943Sdim return SelectionDAGISel::runOnMachineFunction(MF); 359288943Sdim } 360288943Sdim 361251607Sdim // Override MachineFunctionPass. 362314564Sdim StringRef getPassName() const override { 363251607Sdim return "SystemZ DAG->DAG Pattern Instruction Selection"; 364251607Sdim } 365251607Sdim 366251607Sdim // Override SelectionDAGISel. 367309124Sdim void Select(SDNode *Node) override; 368288943Sdim bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, 369276479Sdim std::vector<SDValue> &OutOps) override; 370341825Sdim bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override; 371341825Sdim void PreprocessISelDAG() override; 372251607Sdim 373251607Sdim // Include the pieces autogenerated from the target description. 374251607Sdim #include "SystemZGenDAGISel.inc" 375251607Sdim}; 376251607Sdim} // end anonymous namespace 377251607Sdim 378251607SdimFunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM, 379251607Sdim CodeGenOpt::Level OptLevel) { 380251607Sdim return new SystemZDAGToDAGISel(TM, OptLevel); 381251607Sdim} 382251607Sdim 383251607Sdim// Return true if Val should be selected as a displacement for an address 384251607Sdim// with range DR. Here we're interested in the range of both the instruction 385251607Sdim// described by DR and of any pairing instruction. 386251607Sdimstatic bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val) { 387251607Sdim switch (DR) { 388251607Sdim case SystemZAddressingMode::Disp12Only: 389251607Sdim return isUInt<12>(Val); 390251607Sdim 391251607Sdim case SystemZAddressingMode::Disp12Pair: 392251607Sdim case SystemZAddressingMode::Disp20Only: 393251607Sdim case SystemZAddressingMode::Disp20Pair: 394251607Sdim return isInt<20>(Val); 395251607Sdim 396251607Sdim case SystemZAddressingMode::Disp20Only128: 397251607Sdim return isInt<20>(Val) && isInt<20>(Val + 8); 398251607Sdim } 399251607Sdim llvm_unreachable("Unhandled displacement range"); 400251607Sdim} 401251607Sdim 402251607Sdim// Change the base or index in AM to Value, where IsBase selects 403251607Sdim// between the base and index. 404251607Sdimstatic void changeComponent(SystemZAddressingMode &AM, bool IsBase, 405251607Sdim SDValue Value) { 406251607Sdim if (IsBase) 407251607Sdim AM.Base = Value; 408251607Sdim else 409251607Sdim AM.Index = Value; 410251607Sdim} 411251607Sdim 412251607Sdim// The base or index of AM is equivalent to Value + ADJDYNALLOC, 413251607Sdim// where IsBase selects between the base and index. Try to fold the 414251607Sdim// ADJDYNALLOC into AM. 415251607Sdimstatic bool expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase, 416251607Sdim SDValue Value) { 417251607Sdim if (AM.isDynAlloc() && !AM.IncludesDynAlloc) { 418251607Sdim changeComponent(AM, IsBase, Value); 419251607Sdim AM.IncludesDynAlloc = true; 420251607Sdim return true; 421251607Sdim } 422251607Sdim return false; 423251607Sdim} 424251607Sdim 425251607Sdim// The base of AM is equivalent to Base + Index. Try to use Index as 426251607Sdim// the index register. 427251607Sdimstatic bool expandIndex(SystemZAddressingMode &AM, SDValue Base, 428251607Sdim SDValue Index) { 429251607Sdim if (AM.hasIndexField() && !AM.Index.getNode()) { 430251607Sdim AM.Base = Base; 431251607Sdim AM.Index = Index; 432251607Sdim return true; 433251607Sdim } 434251607Sdim return false; 435251607Sdim} 436251607Sdim 437251607Sdim// The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 438251607Sdim// between the base and index. Try to fold Op1 into AM's displacement. 439251607Sdimstatic bool expandDisp(SystemZAddressingMode &AM, bool IsBase, 440261991Sdim SDValue Op0, uint64_t Op1) { 441251607Sdim // First try adjusting the displacement. 442261991Sdim int64_t TestDisp = AM.Disp + Op1; 443251607Sdim if (selectDisp(AM.DR, TestDisp)) { 444251607Sdim changeComponent(AM, IsBase, Op0); 445251607Sdim AM.Disp = TestDisp; 446251607Sdim return true; 447251607Sdim } 448251607Sdim 449251607Sdim // We could consider forcing the displacement into a register and 450251607Sdim // using it as an index, but it would need to be carefully tuned. 451251607Sdim return false; 452251607Sdim} 453251607Sdim 454251607Sdimbool SystemZDAGToDAGISel::expandAddress(SystemZAddressingMode &AM, 455261991Sdim bool IsBase) const { 456251607Sdim SDValue N = IsBase ? AM.Base : AM.Index; 457251607Sdim unsigned Opcode = N.getOpcode(); 458251607Sdim if (Opcode == ISD::TRUNCATE) { 459251607Sdim N = N.getOperand(0); 460251607Sdim Opcode = N.getOpcode(); 461251607Sdim } 462251607Sdim if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) { 463251607Sdim SDValue Op0 = N.getOperand(0); 464251607Sdim SDValue Op1 = N.getOperand(1); 465251607Sdim 466251607Sdim unsigned Op0Code = Op0->getOpcode(); 467251607Sdim unsigned Op1Code = Op1->getOpcode(); 468251607Sdim 469251607Sdim if (Op0Code == SystemZISD::ADJDYNALLOC) 470251607Sdim return expandAdjDynAlloc(AM, IsBase, Op1); 471251607Sdim if (Op1Code == SystemZISD::ADJDYNALLOC) 472251607Sdim return expandAdjDynAlloc(AM, IsBase, Op0); 473251607Sdim 474251607Sdim if (Op0Code == ISD::Constant) 475261991Sdim return expandDisp(AM, IsBase, Op1, 476261991Sdim cast<ConstantSDNode>(Op0)->getSExtValue()); 477251607Sdim if (Op1Code == ISD::Constant) 478261991Sdim return expandDisp(AM, IsBase, Op0, 479261991Sdim cast<ConstantSDNode>(Op1)->getSExtValue()); 480251607Sdim 481251607Sdim if (IsBase && expandIndex(AM, Op0, Op1)) 482251607Sdim return true; 483251607Sdim } 484261991Sdim if (Opcode == SystemZISD::PCREL_OFFSET) { 485261991Sdim SDValue Full = N.getOperand(0); 486261991Sdim SDValue Base = N.getOperand(1); 487261991Sdim SDValue Anchor = Base.getOperand(0); 488261991Sdim uint64_t Offset = (cast<GlobalAddressSDNode>(Full)->getOffset() - 489261991Sdim cast<GlobalAddressSDNode>(Anchor)->getOffset()); 490261991Sdim return expandDisp(AM, IsBase, Base, Offset); 491261991Sdim } 492251607Sdim return false; 493251607Sdim} 494251607Sdim 495251607Sdim// Return true if an instruction with displacement range DR should be 496251607Sdim// used for displacement value Val. selectDisp(DR, Val) must already hold. 497251607Sdimstatic bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val) { 498251607Sdim assert(selectDisp(DR, Val) && "Invalid displacement"); 499251607Sdim switch (DR) { 500251607Sdim case SystemZAddressingMode::Disp12Only: 501251607Sdim case SystemZAddressingMode::Disp20Only: 502251607Sdim case SystemZAddressingMode::Disp20Only128: 503251607Sdim return true; 504251607Sdim 505251607Sdim case SystemZAddressingMode::Disp12Pair: 506251607Sdim // Use the other instruction if the displacement is too large. 507251607Sdim return isUInt<12>(Val); 508251607Sdim 509251607Sdim case SystemZAddressingMode::Disp20Pair: 510251607Sdim // Use the other instruction if the displacement is small enough. 511251607Sdim return !isUInt<12>(Val); 512251607Sdim } 513251607Sdim llvm_unreachable("Unhandled displacement range"); 514251607Sdim} 515251607Sdim 516251607Sdim// Return true if Base + Disp + Index should be performed by LA(Y). 517251607Sdimstatic bool shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index) { 518251607Sdim // Don't use LA(Y) for constants. 519251607Sdim if (!Base) 520251607Sdim return false; 521251607Sdim 522251607Sdim // Always use LA(Y) for frame addresses, since we know that the destination 523251607Sdim // register is almost always (perhaps always) going to be different from 524251607Sdim // the frame register. 525251607Sdim if (Base->getOpcode() == ISD::FrameIndex) 526251607Sdim return true; 527251607Sdim 528251607Sdim if (Disp) { 529251607Sdim // Always use LA(Y) if there is a base, displacement and index. 530251607Sdim if (Index) 531251607Sdim return true; 532251607Sdim 533251607Sdim // Always use LA if the displacement is small enough. It should always 534251607Sdim // be no worse than AGHI (and better if it avoids a move). 535251607Sdim if (isUInt<12>(Disp)) 536251607Sdim return true; 537251607Sdim 538251607Sdim // For similar reasons, always use LAY if the constant is too big for AGHI. 539251607Sdim // LAY should be no worse than AGFI. 540251607Sdim if (!isInt<16>(Disp)) 541251607Sdim return true; 542251607Sdim } else { 543251607Sdim // Don't use LA for plain registers. 544251607Sdim if (!Index) 545251607Sdim return false; 546251607Sdim 547251607Sdim // Don't use LA for plain addition if the index operand is only used 548251607Sdim // once. It should be a natural two-operand addition in that case. 549251607Sdim if (Index->hasOneUse()) 550251607Sdim return false; 551251607Sdim 552251607Sdim // Prefer addition if the second operation is sign-extended, in the 553251607Sdim // hope of using AGF. 554251607Sdim unsigned IndexOpcode = Index->getOpcode(); 555251607Sdim if (IndexOpcode == ISD::SIGN_EXTEND || 556251607Sdim IndexOpcode == ISD::SIGN_EXTEND_INREG) 557251607Sdim return false; 558251607Sdim } 559251607Sdim 560251607Sdim // Don't use LA for two-operand addition if either operand is only 561251607Sdim // used once. The addition instructions are better in that case. 562251607Sdim if (Base->hasOneUse()) 563251607Sdim return false; 564251607Sdim 565251607Sdim return true; 566251607Sdim} 567251607Sdim 568251607Sdim// Return true if Addr is suitable for AM, updating AM if so. 569251607Sdimbool SystemZDAGToDAGISel::selectAddress(SDValue Addr, 570261991Sdim SystemZAddressingMode &AM) const { 571251607Sdim // Start out assuming that the address will need to be loaded separately, 572251607Sdim // then try to extend it as much as we can. 573251607Sdim AM.Base = Addr; 574251607Sdim 575251607Sdim // First try treating the address as a constant. 576251607Sdim if (Addr.getOpcode() == ISD::Constant && 577261991Sdim expandDisp(AM, true, SDValue(), 578261991Sdim cast<ConstantSDNode>(Addr)->getSExtValue())) 579251607Sdim ; 580309124Sdim // Also see if it's a bare ADJDYNALLOC. 581309124Sdim else if (Addr.getOpcode() == SystemZISD::ADJDYNALLOC && 582309124Sdim expandAdjDynAlloc(AM, true, SDValue())) 583309124Sdim ; 584251607Sdim else 585251607Sdim // Otherwise try expanding each component. 586251607Sdim while (expandAddress(AM, true) || 587251607Sdim (AM.Index.getNode() && expandAddress(AM, false))) 588251607Sdim continue; 589251607Sdim 590251607Sdim // Reject cases where it isn't profitable to use LA(Y). 591251607Sdim if (AM.Form == SystemZAddressingMode::FormBDXLA && 592251607Sdim !shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode())) 593251607Sdim return false; 594251607Sdim 595251607Sdim // Reject cases where the other instruction in a pair should be used. 596251607Sdim if (!isValidDisp(AM.DR, AM.Disp)) 597251607Sdim return false; 598251607Sdim 599251607Sdim // Make sure that ADJDYNALLOC is included where necessary. 600251607Sdim if (AM.isDynAlloc() && !AM.IncludesDynAlloc) 601251607Sdim return false; 602251607Sdim 603344779Sdim LLVM_DEBUG(AM.dump(CurDAG)); 604251607Sdim return true; 605251607Sdim} 606251607Sdim 607251607Sdim// Insert a node into the DAG at least before Pos. This will reposition 608251607Sdim// the node as needed, and will assign it a node ID that is <= Pos's ID. 609251607Sdim// Note that this does *not* preserve the uniqueness of node IDs! 610251607Sdim// The selection DAG must no longer depend on their uniqueness when this 611251607Sdim// function is used. 612251607Sdimstatic void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N) { 613341825Sdim if (N->getNodeId() == -1 || 614341825Sdim (SelectionDAGISel::getUninvalidatedNodeId(N.getNode()) > 615341825Sdim SelectionDAGISel::getUninvalidatedNodeId(Pos))) { 616296417Sdim DAG->RepositionNode(Pos->getIterator(), N.getNode()); 617341825Sdim // Mark Node as invalid for pruning as after this it may be a successor to a 618341825Sdim // selected node but otherwise be in the same position of Pos. 619341825Sdim // Conservatively mark it with the same -abs(Id) to assure node id 620341825Sdim // invariant is preserved. 621341825Sdim N->setNodeId(Pos->getNodeId()); 622341825Sdim SelectionDAGISel::InvalidateNodeId(N.getNode()); 623251607Sdim } 624251607Sdim} 625251607Sdim 626251607Sdimvoid SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM, 627251607Sdim EVT VT, SDValue &Base, 628261991Sdim SDValue &Disp) const { 629251607Sdim Base = AM.Base; 630251607Sdim if (!Base.getNode()) 631251607Sdim // Register 0 means "no base". This is mostly useful for shifts. 632251607Sdim Base = CurDAG->getRegister(0, VT); 633251607Sdim else if (Base.getOpcode() == ISD::FrameIndex) { 634251607Sdim // Lower a FrameIndex to a TargetFrameIndex. 635251607Sdim int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex(); 636251607Sdim Base = CurDAG->getTargetFrameIndex(FrameIndex, VT); 637251607Sdim } else if (Base.getValueType() != VT) { 638251607Sdim // Truncate values from i64 to i32, for shifts. 639251607Sdim assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 && 640251607Sdim "Unexpected truncation"); 641261991Sdim SDLoc DL(Base); 642251607Sdim SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base); 643251607Sdim insertDAGNode(CurDAG, Base.getNode(), Trunc); 644251607Sdim Base = Trunc; 645251607Sdim } 646251607Sdim 647251607Sdim // Lower the displacement to a TargetConstant. 648288943Sdim Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(Base), VT); 649251607Sdim} 650251607Sdim 651251607Sdimvoid SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM, 652251607Sdim EVT VT, SDValue &Base, 653261991Sdim SDValue &Disp, 654261991Sdim SDValue &Index) const { 655251607Sdim getAddressOperands(AM, VT, Base, Disp); 656251607Sdim 657251607Sdim Index = AM.Index; 658251607Sdim if (!Index.getNode()) 659251607Sdim // Register 0 means "no index". 660251607Sdim Index = CurDAG->getRegister(0, VT); 661251607Sdim} 662251607Sdim 663251607Sdimbool SystemZDAGToDAGISel::selectBDAddr(SystemZAddressingMode::DispRange DR, 664251607Sdim SDValue Addr, SDValue &Base, 665261991Sdim SDValue &Disp) const { 666251607Sdim SystemZAddressingMode AM(SystemZAddressingMode::FormBD, DR); 667251607Sdim if (!selectAddress(Addr, AM)) 668251607Sdim return false; 669251607Sdim 670251607Sdim getAddressOperands(AM, Addr.getValueType(), Base, Disp); 671251607Sdim return true; 672251607Sdim} 673251607Sdim 674261991Sdimbool SystemZDAGToDAGISel::selectMVIAddr(SystemZAddressingMode::DispRange DR, 675261991Sdim SDValue Addr, SDValue &Base, 676261991Sdim SDValue &Disp) const { 677261991Sdim SystemZAddressingMode AM(SystemZAddressingMode::FormBDXNormal, DR); 678261991Sdim if (!selectAddress(Addr, AM) || AM.Index.getNode()) 679261991Sdim return false; 680261991Sdim 681261991Sdim getAddressOperands(AM, Addr.getValueType(), Base, Disp); 682261991Sdim return true; 683261991Sdim} 684261991Sdim 685251607Sdimbool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm Form, 686251607Sdim SystemZAddressingMode::DispRange DR, 687251607Sdim SDValue Addr, SDValue &Base, 688261991Sdim SDValue &Disp, SDValue &Index) const { 689251607Sdim SystemZAddressingMode AM(Form, DR); 690251607Sdim if (!selectAddress(Addr, AM)) 691251607Sdim return false; 692251607Sdim 693251607Sdim getAddressOperands(AM, Addr.getValueType(), Base, Disp, Index); 694251607Sdim return true; 695251607Sdim} 696251607Sdim 697288943Sdimbool SystemZDAGToDAGISel::selectBDVAddr12Only(SDValue Addr, SDValue Elem, 698288943Sdim SDValue &Base, 699288943Sdim SDValue &Disp, 700288943Sdim SDValue &Index) const { 701288943Sdim SDValue Regs[2]; 702288943Sdim if (selectBDXAddr12Only(Addr, Regs[0], Disp, Regs[1]) && 703288943Sdim Regs[0].getNode() && Regs[1].getNode()) { 704288943Sdim for (unsigned int I = 0; I < 2; ++I) { 705288943Sdim Base = Regs[I]; 706288943Sdim Index = Regs[1 - I]; 707288943Sdim // We can't tell here whether the index vector has the right type 708288943Sdim // for the access; the caller needs to do that instead. 709288943Sdim if (Index.getOpcode() == ISD::ZERO_EXTEND) 710288943Sdim Index = Index.getOperand(0); 711288943Sdim if (Index.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 712288943Sdim Index.getOperand(1) == Elem) { 713288943Sdim Index = Index.getOperand(0); 714288943Sdim return true; 715288943Sdim } 716288943Sdim } 717288943Sdim } 718288943Sdim return false; 719288943Sdim} 720288943Sdim 721261991Sdimbool SystemZDAGToDAGISel::detectOrAndInsertion(SDValue &Op, 722261991Sdim uint64_t InsertMask) const { 723261991Sdim // We're only interested in cases where the insertion is into some operand 724261991Sdim // of Op, rather than into Op itself. The only useful case is an AND. 725261991Sdim if (Op.getOpcode() != ISD::AND) 726261991Sdim return false; 727261991Sdim 728261991Sdim // We need a constant mask. 729276479Sdim auto *MaskNode = dyn_cast<ConstantSDNode>(Op.getOperand(1).getNode()); 730261991Sdim if (!MaskNode) 731261991Sdim return false; 732261991Sdim 733261991Sdim // It's not an insertion of Op.getOperand(0) if the two masks overlap. 734261991Sdim uint64_t AndMask = MaskNode->getZExtValue(); 735261991Sdim if (InsertMask & AndMask) 736261991Sdim return false; 737261991Sdim 738261991Sdim // It's only an insertion if all bits are covered or are known to be zero. 739261991Sdim // The inner check covers all cases but is more expensive. 740314564Sdim uint64_t Used = allOnes(Op.getValueSizeInBits()); 741261991Sdim if (Used != (AndMask | InsertMask)) { 742344779Sdim KnownBits Known = CurDAG->computeKnownBits(Op.getOperand(0)); 743321369Sdim if (Used != (AndMask | InsertMask | Known.Zero.getZExtValue())) 744261991Sdim return false; 745261991Sdim } 746261991Sdim 747261991Sdim Op = Op.getOperand(0); 748261991Sdim return true; 749261991Sdim} 750261991Sdim 751261991Sdimbool SystemZDAGToDAGISel::refineRxSBGMask(RxSBGOperands &RxSBG, 752261991Sdim uint64_t Mask) const { 753261991Sdim const SystemZInstrInfo *TII = getInstrInfo(); 754261991Sdim if (RxSBG.Rotate != 0) 755261991Sdim Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate)); 756261991Sdim Mask &= RxSBG.Mask; 757261991Sdim if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) { 758261991Sdim RxSBG.Mask = Mask; 759261991Sdim return true; 760261991Sdim } 761261991Sdim return false; 762261991Sdim} 763261991Sdim 764261991Sdim// Return true if any bits of (RxSBG.Input & Mask) are significant. 765261991Sdimstatic bool maskMatters(RxSBGOperands &RxSBG, uint64_t Mask) { 766261991Sdim // Rotate the mask in the same way as RxSBG.Input is rotated. 767261991Sdim if (RxSBG.Rotate != 0) 768261991Sdim Mask = ((Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate))); 769261991Sdim return (Mask & RxSBG.Mask) != 0; 770261991Sdim} 771261991Sdim 772261991Sdimbool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const { 773261991Sdim SDValue N = RxSBG.Input; 774261991Sdim unsigned Opcode = N.getOpcode(); 775261991Sdim switch (Opcode) { 776309124Sdim case ISD::TRUNCATE: { 777309124Sdim if (RxSBG.Opcode == SystemZ::RNSBG) 778309124Sdim return false; 779314564Sdim uint64_t BitSize = N.getValueSizeInBits(); 780309124Sdim uint64_t Mask = allOnes(BitSize); 781309124Sdim if (!refineRxSBGMask(RxSBG, Mask)) 782309124Sdim return false; 783309124Sdim RxSBG.Input = N.getOperand(0); 784309124Sdim return true; 785309124Sdim } 786261991Sdim case ISD::AND: { 787261991Sdim if (RxSBG.Opcode == SystemZ::RNSBG) 788261991Sdim return false; 789261991Sdim 790276479Sdim auto *MaskNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 791261991Sdim if (!MaskNode) 792261991Sdim return false; 793261991Sdim 794261991Sdim SDValue Input = N.getOperand(0); 795261991Sdim uint64_t Mask = MaskNode->getZExtValue(); 796261991Sdim if (!refineRxSBGMask(RxSBG, Mask)) { 797261991Sdim // If some bits of Input are already known zeros, those bits will have 798261991Sdim // been removed from the mask. See if adding them back in makes the 799261991Sdim // mask suitable. 800344779Sdim KnownBits Known = CurDAG->computeKnownBits(Input); 801321369Sdim Mask |= Known.Zero.getZExtValue(); 802261991Sdim if (!refineRxSBGMask(RxSBG, Mask)) 803261991Sdim return false; 804261991Sdim } 805261991Sdim RxSBG.Input = Input; 806261991Sdim return true; 807261991Sdim } 808261991Sdim 809261991Sdim case ISD::OR: { 810261991Sdim if (RxSBG.Opcode != SystemZ::RNSBG) 811261991Sdim return false; 812261991Sdim 813276479Sdim auto *MaskNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 814261991Sdim if (!MaskNode) 815261991Sdim return false; 816261991Sdim 817261991Sdim SDValue Input = N.getOperand(0); 818261991Sdim uint64_t Mask = ~MaskNode->getZExtValue(); 819261991Sdim if (!refineRxSBGMask(RxSBG, Mask)) { 820261991Sdim // If some bits of Input are already known ones, those bits will have 821261991Sdim // been removed from the mask. See if adding them back in makes the 822261991Sdim // mask suitable. 823344779Sdim KnownBits Known = CurDAG->computeKnownBits(Input); 824321369Sdim Mask &= ~Known.One.getZExtValue(); 825261991Sdim if (!refineRxSBGMask(RxSBG, Mask)) 826261991Sdim return false; 827261991Sdim } 828261991Sdim RxSBG.Input = Input; 829261991Sdim return true; 830261991Sdim } 831261991Sdim 832261991Sdim case ISD::ROTL: { 833261991Sdim // Any 64-bit rotate left can be merged into the RxSBG. 834261991Sdim if (RxSBG.BitSize != 64 || N.getValueType() != MVT::i64) 835261991Sdim return false; 836276479Sdim auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 837261991Sdim if (!CountNode) 838261991Sdim return false; 839261991Sdim 840261991Sdim RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63; 841261991Sdim RxSBG.Input = N.getOperand(0); 842261991Sdim return true; 843261991Sdim } 844296417Sdim 845276479Sdim case ISD::ANY_EXTEND: 846276479Sdim // Bits above the extended operand are don't-care. 847276479Sdim RxSBG.Input = N.getOperand(0); 848276479Sdim return true; 849276479Sdim 850261991Sdim case ISD::ZERO_EXTEND: 851276479Sdim if (RxSBG.Opcode != SystemZ::RNSBG) { 852276479Sdim // Restrict the mask to the extended operand. 853314564Sdim unsigned InnerBitSize = N.getOperand(0).getValueSizeInBits(); 854276479Sdim if (!refineRxSBGMask(RxSBG, allOnes(InnerBitSize))) 855276479Sdim return false; 856276479Sdim 857276479Sdim RxSBG.Input = N.getOperand(0); 858276479Sdim return true; 859276479Sdim } 860314564Sdim LLVM_FALLTHROUGH; 861296417Sdim 862276479Sdim case ISD::SIGN_EXTEND: { 863261991Sdim // Check that the extension bits are don't-care (i.e. are masked out 864261991Sdim // by the final mask). 865327952Sdim unsigned BitSize = N.getValueSizeInBits(); 866314564Sdim unsigned InnerBitSize = N.getOperand(0).getValueSizeInBits(); 867327952Sdim if (maskMatters(RxSBG, allOnes(BitSize) - allOnes(InnerBitSize))) { 868327952Sdim // In the case where only the sign bit is active, increase Rotate with 869327952Sdim // the extension width. 870327952Sdim if (RxSBG.Mask == 1 && RxSBG.Rotate == 1) 871327952Sdim RxSBG.Rotate += (BitSize - InnerBitSize); 872327952Sdim else 873327952Sdim return false; 874327952Sdim } 875261991Sdim 876261991Sdim RxSBG.Input = N.getOperand(0); 877261991Sdim return true; 878261991Sdim } 879261991Sdim 880261991Sdim case ISD::SHL: { 881276479Sdim auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 882261991Sdim if (!CountNode) 883261991Sdim return false; 884261991Sdim 885261991Sdim uint64_t Count = CountNode->getZExtValue(); 886314564Sdim unsigned BitSize = N.getValueSizeInBits(); 887261991Sdim if (Count < 1 || Count >= BitSize) 888261991Sdim return false; 889261991Sdim 890261991Sdim if (RxSBG.Opcode == SystemZ::RNSBG) { 891261991Sdim // Treat (shl X, count) as (rotl X, size-count) as long as the bottom 892261991Sdim // count bits from RxSBG.Input are ignored. 893261991Sdim if (maskMatters(RxSBG, allOnes(Count))) 894261991Sdim return false; 895261991Sdim } else { 896261991Sdim // Treat (shl X, count) as (and (rotl X, count), ~0<<count). 897261991Sdim if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count) << Count)) 898261991Sdim return false; 899261991Sdim } 900261991Sdim 901261991Sdim RxSBG.Rotate = (RxSBG.Rotate + Count) & 63; 902261991Sdim RxSBG.Input = N.getOperand(0); 903261991Sdim return true; 904261991Sdim } 905261991Sdim 906261991Sdim case ISD::SRL: 907261991Sdim case ISD::SRA: { 908276479Sdim auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 909261991Sdim if (!CountNode) 910261991Sdim return false; 911261991Sdim 912261991Sdim uint64_t Count = CountNode->getZExtValue(); 913314564Sdim unsigned BitSize = N.getValueSizeInBits(); 914261991Sdim if (Count < 1 || Count >= BitSize) 915261991Sdim return false; 916261991Sdim 917261991Sdim if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) { 918261991Sdim // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top 919261991Sdim // count bits from RxSBG.Input are ignored. 920261991Sdim if (maskMatters(RxSBG, allOnes(Count) << (BitSize - Count))) 921261991Sdim return false; 922261991Sdim } else { 923261991Sdim // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count), 924261991Sdim // which is similar to SLL above. 925261991Sdim if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count))) 926261991Sdim return false; 927261991Sdim } 928261991Sdim 929261991Sdim RxSBG.Rotate = (RxSBG.Rotate - Count) & 63; 930261991Sdim RxSBG.Input = N.getOperand(0); 931261991Sdim return true; 932261991Sdim } 933261991Sdim default: 934261991Sdim return false; 935261991Sdim } 936261991Sdim} 937261991Sdim 938309124SdimSDValue SystemZDAGToDAGISel::getUNDEF(const SDLoc &DL, EVT VT) const { 939261991Sdim SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT); 940261991Sdim return SDValue(N, 0); 941261991Sdim} 942261991Sdim 943309124SdimSDValue SystemZDAGToDAGISel::convertTo(const SDLoc &DL, EVT VT, 944309124Sdim SDValue N) const { 945261991Sdim if (N.getValueType() == MVT::i32 && VT == MVT::i64) 946261991Sdim return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32, 947261991Sdim DL, VT, getUNDEF(DL, MVT::i64), N); 948261991Sdim if (N.getValueType() == MVT::i64 && VT == MVT::i32) 949261991Sdim return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N); 950261991Sdim assert(N.getValueType() == VT && "Unexpected value types"); 951261991Sdim return N; 952261991Sdim} 953261991Sdim 954309124Sdimbool SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) { 955288943Sdim SDLoc DL(N); 956261991Sdim EVT VT = N->getValueType(0); 957288943Sdim if (!VT.isInteger() || VT.getSizeInBits() > 64) 958309124Sdim return false; 959261991Sdim RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0)); 960261991Sdim unsigned Count = 0; 961261991Sdim while (expandRxSBG(RISBG)) 962309124Sdim // The widening or narrowing is expected to be free. 963309124Sdim // Counting widening or narrowing as a saved operation will result in 964309124Sdim // preferring an R*SBG over a simple shift/logical instruction. 965309124Sdim if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND && 966309124Sdim RISBG.Input.getOpcode() != ISD::TRUNCATE) 967261991Sdim Count += 1; 968261991Sdim if (Count == 0) 969309124Sdim return false; 970261991Sdim 971314564Sdim // Prefer to use normal shift instructions over RISBG, since they can handle 972314564Sdim // all cases and are sometimes shorter. 973314564Sdim if (Count == 1 && N->getOpcode() != ISD::AND) 974314564Sdim return false; 975314564Sdim 976314564Sdim // Prefer register extensions like LLC over RISBG. Also prefer to start 977314564Sdim // out with normal ANDs if one instruction would be enough. We can convert 978314564Sdim // these ANDs into an RISBG later if a three-address instruction is useful. 979314564Sdim if (RISBG.Rotate == 0) { 980314564Sdim bool PreferAnd = false; 981314564Sdim // Prefer AND for any 32-bit and-immediate operation. 982314564Sdim if (VT == MVT::i32) 983314564Sdim PreferAnd = true; 984314564Sdim // As well as for any 64-bit operation that can be implemented via LLC(R), 985314564Sdim // LLH(R), LLGT(R), or one of the and-immediate instructions. 986314564Sdim else if (RISBG.Mask == 0xff || 987314564Sdim RISBG.Mask == 0xffff || 988314564Sdim RISBG.Mask == 0x7fffffff || 989314564Sdim SystemZ::isImmLF(~RISBG.Mask) || 990314564Sdim SystemZ::isImmHF(~RISBG.Mask)) 991314564Sdim PreferAnd = true; 992314564Sdim // And likewise for the LLZRGF instruction, which doesn't have a register 993314564Sdim // to register version. 994314564Sdim else if (auto *Load = dyn_cast<LoadSDNode>(RISBG.Input)) { 995314564Sdim if (Load->getMemoryVT() == MVT::i32 && 996314564Sdim (Load->getExtensionType() == ISD::EXTLOAD || 997314564Sdim Load->getExtensionType() == ISD::ZEXTLOAD) && 998314564Sdim RISBG.Mask == 0xffffff00 && 999314564Sdim Subtarget->hasLoadAndZeroRightmostByte()) 1000314564Sdim PreferAnd = true; 1001314564Sdim } 1002314564Sdim if (PreferAnd) { 1003314564Sdim // Replace the current node with an AND. Note that the current node 1004314564Sdim // might already be that same AND, in which case it is already CSE'd 1005314564Sdim // with it, and we must not call ReplaceNode. 1006314564Sdim SDValue In = convertTo(DL, VT, RISBG.Input); 1007314564Sdim SDValue Mask = CurDAG->getConstant(RISBG.Mask, DL, VT); 1008314564Sdim SDValue New = CurDAG->getNode(ISD::AND, DL, VT, In, Mask); 1009314564Sdim if (N != New.getNode()) { 1010314564Sdim insertDAGNode(CurDAG, N, Mask); 1011314564Sdim insertDAGNode(CurDAG, N, New); 1012314564Sdim ReplaceNode(N, New.getNode()); 1013314564Sdim N = New.getNode(); 1014261991Sdim } 1015314564Sdim // Now, select the machine opcode to implement this operation. 1016341825Sdim if (!N->isMachineOpcode()) 1017341825Sdim SelectCode(N); 1018314564Sdim return true; 1019261991Sdim } 1020296417Sdim } 1021261991Sdim 1022261991Sdim unsigned Opcode = SystemZ::RISBG; 1023288943Sdim // Prefer RISBGN if available, since it does not clobber CC. 1024288943Sdim if (Subtarget->hasMiscellaneousExtensions()) 1025288943Sdim Opcode = SystemZ::RISBGN; 1026261991Sdim EVT OpcodeVT = MVT::i64; 1027327952Sdim if (VT == MVT::i32 && Subtarget->hasHighWord() && 1028327952Sdim // We can only use the 32-bit instructions if all source bits are 1029327952Sdim // in the low 32 bits without wrapping, both after rotation (because 1030327952Sdim // of the smaller range for Start and End) and before rotation 1031327952Sdim // (because the input value is truncated). 1032327952Sdim RISBG.Start >= 32 && RISBG.End >= RISBG.Start && 1033327952Sdim ((RISBG.Start + RISBG.Rotate) & 63) >= 32 && 1034327952Sdim ((RISBG.End + RISBG.Rotate) & 63) >= 1035327952Sdim ((RISBG.Start + RISBG.Rotate) & 63)) { 1036261991Sdim Opcode = SystemZ::RISBMux; 1037261991Sdim OpcodeVT = MVT::i32; 1038261991Sdim RISBG.Start &= 31; 1039261991Sdim RISBG.End &= 31; 1040261991Sdim } 1041261991Sdim SDValue Ops[5] = { 1042288943Sdim getUNDEF(DL, OpcodeVT), 1043288943Sdim convertTo(DL, OpcodeVT, RISBG.Input), 1044288943Sdim CurDAG->getTargetConstant(RISBG.Start, DL, MVT::i32), 1045288943Sdim CurDAG->getTargetConstant(RISBG.End | 128, DL, MVT::i32), 1046288943Sdim CurDAG->getTargetConstant(RISBG.Rotate, DL, MVT::i32) 1047261991Sdim }; 1048309124Sdim SDValue New = convertTo( 1049309124Sdim DL, VT, SDValue(CurDAG->getMachineNode(Opcode, DL, OpcodeVT, Ops), 0)); 1050341825Sdim ReplaceNode(N, New.getNode()); 1051309124Sdim return true; 1052261991Sdim} 1053261991Sdim 1054309124Sdimbool SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) { 1055288943Sdim SDLoc DL(N); 1056288943Sdim EVT VT = N->getValueType(0); 1057288943Sdim if (!VT.isInteger() || VT.getSizeInBits() > 64) 1058309124Sdim return false; 1059261991Sdim // Try treating each operand of N as the second operand of the RxSBG 1060261991Sdim // and see which goes deepest. 1061261991Sdim RxSBGOperands RxSBG[] = { 1062261991Sdim RxSBGOperands(Opcode, N->getOperand(0)), 1063261991Sdim RxSBGOperands(Opcode, N->getOperand(1)) 1064261991Sdim }; 1065261991Sdim unsigned Count[] = { 0, 0 }; 1066261991Sdim for (unsigned I = 0; I < 2; ++I) 1067261991Sdim while (expandRxSBG(RxSBG[I])) 1068309124Sdim // The widening or narrowing is expected to be free. 1069309124Sdim // Counting widening or narrowing as a saved operation will result in 1070309124Sdim // preferring an R*SBG over a simple shift/logical instruction. 1071309124Sdim if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND && 1072309124Sdim RxSBG[I].Input.getOpcode() != ISD::TRUNCATE) 1073261991Sdim Count[I] += 1; 1074261991Sdim 1075261991Sdim // Do nothing if neither operand is suitable. 1076261991Sdim if (Count[0] == 0 && Count[1] == 0) 1077309124Sdim return false; 1078261991Sdim 1079261991Sdim // Pick the deepest second operand. 1080261991Sdim unsigned I = Count[0] > Count[1] ? 0 : 1; 1081261991Sdim SDValue Op0 = N->getOperand(I ^ 1); 1082261991Sdim 1083261991Sdim // Prefer IC for character insertions from memory. 1084261991Sdim if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0) 1085276479Sdim if (auto *Load = dyn_cast<LoadSDNode>(Op0.getNode())) 1086261991Sdim if (Load->getMemoryVT() == MVT::i8) 1087309124Sdim return false; 1088261991Sdim 1089261991Sdim // See whether we can avoid an AND in the first operand by converting 1090261991Sdim // ROSBG to RISBG. 1091288943Sdim if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask)) { 1092261991Sdim Opcode = SystemZ::RISBG; 1093288943Sdim // Prefer RISBGN if available, since it does not clobber CC. 1094288943Sdim if (Subtarget->hasMiscellaneousExtensions()) 1095288943Sdim Opcode = SystemZ::RISBGN; 1096288943Sdim } 1097288943Sdim 1098261991Sdim SDValue Ops[5] = { 1099288943Sdim convertTo(DL, MVT::i64, Op0), 1100288943Sdim convertTo(DL, MVT::i64, RxSBG[I].Input), 1101288943Sdim CurDAG->getTargetConstant(RxSBG[I].Start, DL, MVT::i32), 1102288943Sdim CurDAG->getTargetConstant(RxSBG[I].End, DL, MVT::i32), 1103288943Sdim CurDAG->getTargetConstant(RxSBG[I].Rotate, DL, MVT::i32) 1104261991Sdim }; 1105309124Sdim SDValue New = convertTo( 1106309124Sdim DL, VT, SDValue(CurDAG->getMachineNode(Opcode, DL, MVT::i64, Ops), 0)); 1107309124Sdim ReplaceNode(N, New.getNode()); 1108309124Sdim return true; 1109261991Sdim} 1110261991Sdim 1111309124Sdimvoid SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node, 1112309124Sdim SDValue Op0, uint64_t UpperVal, 1113309124Sdim uint64_t LowerVal) { 1114251607Sdim EVT VT = Node->getValueType(0); 1115261991Sdim SDLoc DL(Node); 1116288943Sdim SDValue Upper = CurDAG->getConstant(UpperVal, DL, VT); 1117251607Sdim if (Op0.getNode()) 1118251607Sdim Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper); 1119251607Sdim 1120309124Sdim { 1121309124Sdim // When we haven't passed in Op0, Upper will be a constant. In order to 1122309124Sdim // prevent folding back to the large immediate in `Or = getNode(...)` we run 1123309124Sdim // SelectCode first and end up with an opaque machine node. This means that 1124309124Sdim // we need to use a handle to keep track of Upper in case it gets CSE'd by 1125309124Sdim // SelectCode. 1126309124Sdim // 1127309124Sdim // Note that in the case where Op0 is passed in we could just call 1128309124Sdim // SelectCode(Upper) later, along with the SelectCode(Or), and avoid needing 1129309124Sdim // the handle at all, but it's fine to do it here. 1130309124Sdim // 1131309124Sdim // TODO: This is a pretty hacky way to do this. Can we do something that 1132309124Sdim // doesn't require a two paragraph explanation? 1133309124Sdim HandleSDNode Handle(Upper); 1134309124Sdim SelectCode(Upper.getNode()); 1135309124Sdim Upper = Handle.getValue(); 1136309124Sdim } 1137309124Sdim 1138288943Sdim SDValue Lower = CurDAG->getConstant(LowerVal, DL, VT); 1139251607Sdim SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower); 1140309124Sdim 1141341825Sdim ReplaceNode(Node, Or.getNode()); 1142309124Sdim 1143309124Sdim SelectCode(Or.getNode()); 1144251607Sdim} 1145251607Sdim 1146353358Sdimvoid SystemZDAGToDAGISel::loadVectorConstant( 1147353358Sdim const SystemZVectorConstantInfo &VCI, SDNode *Node) { 1148353358Sdim assert((VCI.Opcode == SystemZISD::BYTE_MASK || 1149353358Sdim VCI.Opcode == SystemZISD::REPLICATE || 1150353358Sdim VCI.Opcode == SystemZISD::ROTATE_MASK) && 1151353358Sdim "Bad opcode!"); 1152353358Sdim assert(VCI.VecVT.getSizeInBits() == 128 && "Expected a vector type"); 1153353358Sdim EVT VT = Node->getValueType(0); 1154353358Sdim SDLoc DL(Node); 1155353358Sdim SmallVector<SDValue, 2> Ops; 1156353358Sdim for (unsigned OpVal : VCI.OpVals) 1157360784Sdim Ops.push_back(CurDAG->getTargetConstant(OpVal, DL, MVT::i32)); 1158353358Sdim SDValue Op = CurDAG->getNode(VCI.Opcode, DL, VCI.VecVT, Ops); 1159353358Sdim 1160353358Sdim if (VCI.VecVT == VT.getSimpleVT()) 1161353358Sdim ReplaceNode(Node, Op.getNode()); 1162353358Sdim else if (VT.getSizeInBits() == 128) { 1163353358Sdim SDValue BitCast = CurDAG->getNode(ISD::BITCAST, DL, VT, Op); 1164353358Sdim ReplaceNode(Node, BitCast.getNode()); 1165353358Sdim SelectCode(BitCast.getNode()); 1166353358Sdim } else { // float or double 1167353358Sdim unsigned SubRegIdx = 1168353358Sdim (VT.getSizeInBits() == 32 ? SystemZ::subreg_h32 : SystemZ::subreg_h64); 1169353358Sdim ReplaceNode( 1170353358Sdim Node, CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, Op).getNode()); 1171353358Sdim } 1172353358Sdim SelectCode(Op.getNode()); 1173353358Sdim} 1174353358Sdim 1175309124Sdimbool SystemZDAGToDAGISel::tryGather(SDNode *N, unsigned Opcode) { 1176288943Sdim SDValue ElemV = N->getOperand(2); 1177288943Sdim auto *ElemN = dyn_cast<ConstantSDNode>(ElemV); 1178288943Sdim if (!ElemN) 1179309124Sdim return false; 1180288943Sdim 1181288943Sdim unsigned Elem = ElemN->getZExtValue(); 1182288943Sdim EVT VT = N->getValueType(0); 1183288943Sdim if (Elem >= VT.getVectorNumElements()) 1184309124Sdim return false; 1185288943Sdim 1186288943Sdim auto *Load = dyn_cast<LoadSDNode>(N->getOperand(1)); 1187344779Sdim if (!Load || !Load->hasNUsesOfValue(1, 0)) 1188309124Sdim return false; 1189288943Sdim if (Load->getMemoryVT().getSizeInBits() != 1190288943Sdim Load->getValueType(0).getSizeInBits()) 1191309124Sdim return false; 1192288943Sdim 1193288943Sdim SDValue Base, Disp, Index; 1194288943Sdim if (!selectBDVAddr12Only(Load->getBasePtr(), ElemV, Base, Disp, Index) || 1195288943Sdim Index.getValueType() != VT.changeVectorElementTypeToInteger()) 1196309124Sdim return false; 1197288943Sdim 1198288943Sdim SDLoc DL(Load); 1199288943Sdim SDValue Ops[] = { 1200288943Sdim N->getOperand(0), Base, Disp, Index, 1201288943Sdim CurDAG->getTargetConstant(Elem, DL, MVT::i32), Load->getChain() 1202288943Sdim }; 1203288943Sdim SDNode *Res = CurDAG->getMachineNode(Opcode, DL, VT, MVT::Other, Ops); 1204288943Sdim ReplaceUses(SDValue(Load, 1), SDValue(Res, 1)); 1205309124Sdim ReplaceNode(N, Res); 1206309124Sdim return true; 1207288943Sdim} 1208288943Sdim 1209309124Sdimbool SystemZDAGToDAGISel::tryScatter(StoreSDNode *Store, unsigned Opcode) { 1210288943Sdim SDValue Value = Store->getValue(); 1211288943Sdim if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT) 1212309124Sdim return false; 1213314564Sdim if (Store->getMemoryVT().getSizeInBits() != Value.getValueSizeInBits()) 1214309124Sdim return false; 1215288943Sdim 1216288943Sdim SDValue ElemV = Value.getOperand(1); 1217288943Sdim auto *ElemN = dyn_cast<ConstantSDNode>(ElemV); 1218288943Sdim if (!ElemN) 1219309124Sdim return false; 1220288943Sdim 1221288943Sdim SDValue Vec = Value.getOperand(0); 1222288943Sdim EVT VT = Vec.getValueType(); 1223288943Sdim unsigned Elem = ElemN->getZExtValue(); 1224288943Sdim if (Elem >= VT.getVectorNumElements()) 1225309124Sdim return false; 1226288943Sdim 1227288943Sdim SDValue Base, Disp, Index; 1228288943Sdim if (!selectBDVAddr12Only(Store->getBasePtr(), ElemV, Base, Disp, Index) || 1229288943Sdim Index.getValueType() != VT.changeVectorElementTypeToInteger()) 1230309124Sdim return false; 1231288943Sdim 1232288943Sdim SDLoc DL(Store); 1233288943Sdim SDValue Ops[] = { 1234288943Sdim Vec, Base, Disp, Index, CurDAG->getTargetConstant(Elem, DL, MVT::i32), 1235288943Sdim Store->getChain() 1236288943Sdim }; 1237309124Sdim ReplaceNode(Store, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops)); 1238309124Sdim return true; 1239288943Sdim} 1240288943Sdim 1241341825Sdim// Check whether or not the chain ending in StoreNode is suitable for doing 1242341825Sdim// the {load; op; store} to modify transformation. 1243341825Sdimstatic bool isFusableLoadOpStorePattern(StoreSDNode *StoreNode, 1244341825Sdim SDValue StoredVal, SelectionDAG *CurDAG, 1245341825Sdim LoadSDNode *&LoadNode, 1246341825Sdim SDValue &InputChain) { 1247341825Sdim // Is the stored value result 0 of the operation? 1248341825Sdim if (StoredVal.getResNo() != 0) 1249341825Sdim return false; 1250341825Sdim 1251341825Sdim // Are there other uses of the loaded value than the operation? 1252341825Sdim if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) 1253341825Sdim return false; 1254341825Sdim 1255341825Sdim // Is the store non-extending and non-indexed? 1256341825Sdim if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal()) 1257341825Sdim return false; 1258341825Sdim 1259341825Sdim SDValue Load = StoredVal->getOperand(0); 1260341825Sdim // Is the stored value a non-extending and non-indexed load? 1261341825Sdim if (!ISD::isNormalLoad(Load.getNode())) 1262341825Sdim return false; 1263341825Sdim 1264341825Sdim // Return LoadNode by reference. 1265341825Sdim LoadNode = cast<LoadSDNode>(Load); 1266341825Sdim 1267341825Sdim // Is store the only read of the loaded value? 1268341825Sdim if (!Load.hasOneUse()) 1269341825Sdim return false; 1270341825Sdim 1271341825Sdim // Is the address of the store the same as the load? 1272341825Sdim if (LoadNode->getBasePtr() != StoreNode->getBasePtr() || 1273341825Sdim LoadNode->getOffset() != StoreNode->getOffset()) 1274341825Sdim return false; 1275341825Sdim 1276341825Sdim // Check if the chain is produced by the load or is a TokenFactor with 1277341825Sdim // the load output chain as an operand. Return InputChain by reference. 1278341825Sdim SDValue Chain = StoreNode->getChain(); 1279341825Sdim 1280341825Sdim bool ChainCheck = false; 1281341825Sdim if (Chain == Load.getValue(1)) { 1282341825Sdim ChainCheck = true; 1283341825Sdim InputChain = LoadNode->getChain(); 1284341825Sdim } else if (Chain.getOpcode() == ISD::TokenFactor) { 1285341825Sdim SmallVector<SDValue, 4> ChainOps; 1286353358Sdim SmallVector<const SDNode *, 4> LoopWorklist; 1287353358Sdim SmallPtrSet<const SDNode *, 16> Visited; 1288353358Sdim const unsigned int Max = 1024; 1289341825Sdim for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) { 1290341825Sdim SDValue Op = Chain.getOperand(i); 1291341825Sdim if (Op == Load.getValue(1)) { 1292341825Sdim ChainCheck = true; 1293341825Sdim // Drop Load, but keep its chain. No cycle check necessary. 1294341825Sdim ChainOps.push_back(Load.getOperand(0)); 1295341825Sdim continue; 1296341825Sdim } 1297353358Sdim LoopWorklist.push_back(Op.getNode()); 1298341825Sdim ChainOps.push_back(Op); 1299341825Sdim } 1300341825Sdim 1301353358Sdim if (ChainCheck) { 1302353358Sdim // Add the other operand of StoredVal to worklist. 1303353358Sdim for (SDValue Op : StoredVal->ops()) 1304353358Sdim if (Op.getNode() != LoadNode) 1305353358Sdim LoopWorklist.push_back(Op.getNode()); 1306353358Sdim 1307353358Sdim // Check if Load is reachable from any of the nodes in the worklist. 1308353358Sdim if (SDNode::hasPredecessorHelper(Load.getNode(), Visited, LoopWorklist, Max, 1309353358Sdim true)) 1310353358Sdim return false; 1311353358Sdim 1312341825Sdim // Make a new TokenFactor with all the other input chains except 1313341825Sdim // for the load. 1314341825Sdim InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), 1315341825Sdim MVT::Other, ChainOps); 1316353358Sdim } 1317341825Sdim } 1318341825Sdim if (!ChainCheck) 1319341825Sdim return false; 1320341825Sdim 1321341825Sdim return true; 1322341825Sdim} 1323341825Sdim 1324341825Sdim// Change a chain of {load; op; store} of the same value into a simple op 1325341825Sdim// through memory of that value, if the uses of the modified value and its 1326341825Sdim// address are suitable. 1327341825Sdim// 1328341825Sdim// The tablegen pattern memory operand pattern is currently not able to match 1329341825Sdim// the case where the CC on the original operation are used. 1330341825Sdim// 1331341825Sdim// See the equivalent routine in X86ISelDAGToDAG for further comments. 1332341825Sdimbool SystemZDAGToDAGISel::tryFoldLoadStoreIntoMemOperand(SDNode *Node) { 1333341825Sdim StoreSDNode *StoreNode = cast<StoreSDNode>(Node); 1334341825Sdim SDValue StoredVal = StoreNode->getOperand(1); 1335341825Sdim unsigned Opc = StoredVal->getOpcode(); 1336341825Sdim SDLoc DL(StoreNode); 1337341825Sdim 1338341825Sdim // Before we try to select anything, make sure this is memory operand size 1339341825Sdim // and opcode we can handle. Note that this must match the code below that 1340341825Sdim // actually lowers the opcodes. 1341341825Sdim EVT MemVT = StoreNode->getMemoryVT(); 1342341825Sdim unsigned NewOpc = 0; 1343341825Sdim bool NegateOperand = false; 1344341825Sdim switch (Opc) { 1345341825Sdim default: 1346341825Sdim return false; 1347341825Sdim case SystemZISD::SSUBO: 1348341825Sdim NegateOperand = true; 1349344779Sdim LLVM_FALLTHROUGH; 1350341825Sdim case SystemZISD::SADDO: 1351341825Sdim if (MemVT == MVT::i32) 1352341825Sdim NewOpc = SystemZ::ASI; 1353341825Sdim else if (MemVT == MVT::i64) 1354341825Sdim NewOpc = SystemZ::AGSI; 1355341825Sdim else 1356341825Sdim return false; 1357341825Sdim break; 1358341825Sdim case SystemZISD::USUBO: 1359341825Sdim NegateOperand = true; 1360344779Sdim LLVM_FALLTHROUGH; 1361341825Sdim case SystemZISD::UADDO: 1362341825Sdim if (MemVT == MVT::i32) 1363341825Sdim NewOpc = SystemZ::ALSI; 1364341825Sdim else if (MemVT == MVT::i64) 1365341825Sdim NewOpc = SystemZ::ALGSI; 1366341825Sdim else 1367341825Sdim return false; 1368341825Sdim break; 1369341825Sdim } 1370341825Sdim 1371341825Sdim LoadSDNode *LoadNode = nullptr; 1372341825Sdim SDValue InputChain; 1373341825Sdim if (!isFusableLoadOpStorePattern(StoreNode, StoredVal, CurDAG, LoadNode, 1374341825Sdim InputChain)) 1375341825Sdim return false; 1376341825Sdim 1377341825Sdim SDValue Operand = StoredVal.getOperand(1); 1378341825Sdim auto *OperandC = dyn_cast<ConstantSDNode>(Operand); 1379341825Sdim if (!OperandC) 1380341825Sdim return false; 1381341825Sdim auto OperandV = OperandC->getAPIntValue(); 1382341825Sdim if (NegateOperand) 1383341825Sdim OperandV = -OperandV; 1384341825Sdim if (OperandV.getMinSignedBits() > 8) 1385341825Sdim return false; 1386341825Sdim Operand = CurDAG->getTargetConstant(OperandV, DL, MemVT); 1387341825Sdim 1388341825Sdim SDValue Base, Disp; 1389341825Sdim if (!selectBDAddr20Only(StoreNode->getBasePtr(), Base, Disp)) 1390341825Sdim return false; 1391341825Sdim 1392341825Sdim SDValue Ops[] = { Base, Disp, Operand, InputChain }; 1393341825Sdim MachineSDNode *Result = 1394341825Sdim CurDAG->getMachineNode(NewOpc, DL, MVT::i32, MVT::Other, Ops); 1395344779Sdim CurDAG->setNodeMemRefs( 1396344779Sdim Result, {StoreNode->getMemOperand(), LoadNode->getMemOperand()}); 1397341825Sdim 1398341825Sdim ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1)); 1399341825Sdim ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0)); 1400341825Sdim CurDAG->RemoveDeadNode(Node); 1401341825Sdim return true; 1402341825Sdim} 1403341825Sdim 1404261991Sdimbool SystemZDAGToDAGISel::canUseBlockOperation(StoreSDNode *Store, 1405261991Sdim LoadSDNode *Load) const { 1406261991Sdim // Check that the two memory operands have the same size. 1407261991Sdim if (Load->getMemoryVT() != Store->getMemoryVT()) 1408261991Sdim return false; 1409261991Sdim 1410261991Sdim // Volatility stops an access from being decomposed. 1411261991Sdim if (Load->isVolatile() || Store->isVolatile()) 1412261991Sdim return false; 1413261991Sdim 1414261991Sdim // There's no chance of overlap if the load is invariant. 1415314564Sdim if (Load->isInvariant() && Load->isDereferenceable()) 1416261991Sdim return true; 1417261991Sdim 1418261991Sdim // Otherwise we need to check whether there's an alias. 1419276479Sdim const Value *V1 = Load->getMemOperand()->getValue(); 1420276479Sdim const Value *V2 = Store->getMemOperand()->getValue(); 1421261991Sdim if (!V1 || !V2) 1422261991Sdim return false; 1423261991Sdim 1424261991Sdim // Reject equality. 1425261991Sdim uint64_t Size = Load->getMemoryVT().getStoreSize(); 1426261991Sdim int64_t End1 = Load->getSrcValueOffset() + Size; 1427261991Sdim int64_t End2 = Store->getSrcValueOffset() + Size; 1428261991Sdim if (V1 == V2 && End1 == End2) 1429261991Sdim return false; 1430261991Sdim 1431288943Sdim return !AA->alias(MemoryLocation(V1, End1, Load->getAAInfo()), 1432288943Sdim MemoryLocation(V2, End2, Store->getAAInfo())); 1433261991Sdim} 1434261991Sdim 1435261991Sdimbool SystemZDAGToDAGISel::storeLoadCanUseMVC(SDNode *N) const { 1436276479Sdim auto *Store = cast<StoreSDNode>(N); 1437276479Sdim auto *Load = cast<LoadSDNode>(Store->getValue()); 1438261991Sdim 1439261991Sdim // Prefer not to use MVC if either address can use ... RELATIVE LONG 1440261991Sdim // instructions. 1441261991Sdim uint64_t Size = Load->getMemoryVT().getStoreSize(); 1442261991Sdim if (Size > 1 && Size <= 8) { 1443261991Sdim // Prefer LHRL, LRL and LGRL. 1444261991Sdim if (SystemZISD::isPCREL(Load->getBasePtr().getOpcode())) 1445261991Sdim return false; 1446261991Sdim // Prefer STHRL, STRL and STGRL. 1447261991Sdim if (SystemZISD::isPCREL(Store->getBasePtr().getOpcode())) 1448261991Sdim return false; 1449261991Sdim } 1450261991Sdim 1451261991Sdim return canUseBlockOperation(Store, Load); 1452261991Sdim} 1453261991Sdim 1454261991Sdimbool SystemZDAGToDAGISel::storeLoadCanUseBlockBinary(SDNode *N, 1455261991Sdim unsigned I) const { 1456276479Sdim auto *StoreA = cast<StoreSDNode>(N); 1457276479Sdim auto *LoadA = cast<LoadSDNode>(StoreA->getValue().getOperand(1 - I)); 1458276479Sdim auto *LoadB = cast<LoadSDNode>(StoreA->getValue().getOperand(I)); 1459261991Sdim return !LoadA->isVolatile() && canUseBlockOperation(StoreA, LoadB); 1460261991Sdim} 1461261991Sdim 1462309124Sdimvoid SystemZDAGToDAGISel::Select(SDNode *Node) { 1463251607Sdim // If we have a custom node, we already have selected! 1464251607Sdim if (Node->isMachineOpcode()) { 1465341825Sdim LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); 1466255804Sdim Node->setNodeId(-1); 1467309124Sdim return; 1468251607Sdim } 1469251607Sdim 1470251607Sdim unsigned Opcode = Node->getOpcode(); 1471251607Sdim switch (Opcode) { 1472251607Sdim case ISD::OR: 1473261991Sdim if (Node->getOperand(1).getOpcode() != ISD::Constant) 1474309124Sdim if (tryRxSBG(Node, SystemZ::ROSBG)) 1475309124Sdim return; 1476261991Sdim goto or_xor; 1477261991Sdim 1478251607Sdim case ISD::XOR: 1479261991Sdim if (Node->getOperand(1).getOpcode() != ISD::Constant) 1480309124Sdim if (tryRxSBG(Node, SystemZ::RXSBG)) 1481309124Sdim return; 1482261991Sdim // Fall through. 1483261991Sdim or_xor: 1484251607Sdim // If this is a 64-bit operation in which both 32-bit halves are nonzero, 1485327952Sdim // split the operation into two. If both operands here happen to be 1486327952Sdim // constant, leave this to common code to optimize. 1487327952Sdim if (Node->getValueType(0) == MVT::i64 && 1488327952Sdim Node->getOperand(0).getOpcode() != ISD::Constant) 1489276479Sdim if (auto *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) { 1490251607Sdim uint64_t Val = Op1->getZExtValue(); 1491353358Sdim // Don't split the operation if we can match one of the combined 1492353358Sdim // logical operations provided by miscellaneous-extensions-3. 1493353358Sdim if (Subtarget->hasMiscellaneousExtensions3()) { 1494353358Sdim unsigned ChildOpcode = Node->getOperand(0).getOpcode(); 1495353358Sdim // Check whether this expression matches NAND/NOR/NXOR. 1496353358Sdim if (Val == (uint64_t)-1 && Opcode == ISD::XOR) 1497353358Sdim if (ChildOpcode == ISD::AND || ChildOpcode == ISD::OR || 1498353358Sdim ChildOpcode == ISD::XOR) 1499353358Sdim break; 1500360784Sdim // Check whether this expression matches OR-with-complement 1501360784Sdim // (or matches an alternate pattern for NXOR). 1502360784Sdim if (ChildOpcode == ISD::XOR) { 1503353358Sdim auto Op0 = Node->getOperand(0); 1504353358Sdim if (auto *Op0Op1 = dyn_cast<ConstantSDNode>(Op0->getOperand(1))) 1505353358Sdim if (Op0Op1->getZExtValue() == (uint64_t)-1) 1506353358Sdim break; 1507353358Sdim } 1508353358Sdim } 1509309124Sdim if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val)) { 1510309124Sdim splitLargeImmediate(Opcode, Node, Node->getOperand(0), 1511309124Sdim Val - uint32_t(Val), uint32_t(Val)); 1512309124Sdim return; 1513309124Sdim } 1514251607Sdim } 1515251607Sdim break; 1516251607Sdim 1517261991Sdim case ISD::AND: 1518261991Sdim if (Node->getOperand(1).getOpcode() != ISD::Constant) 1519309124Sdim if (tryRxSBG(Node, SystemZ::RNSBG)) 1520309124Sdim return; 1521314564Sdim LLVM_FALLTHROUGH; 1522261991Sdim case ISD::ROTL: 1523261991Sdim case ISD::SHL: 1524261991Sdim case ISD::SRL: 1525276479Sdim case ISD::ZERO_EXTEND: 1526309124Sdim if (tryRISBGZero(Node)) 1527309124Sdim return; 1528261991Sdim break; 1529261991Sdim 1530251607Sdim case ISD::Constant: 1531251607Sdim // If this is a 64-bit constant that is out of the range of LLILF, 1532251607Sdim // LLIHF and LGFI, split it into two 32-bit pieces. 1533251607Sdim if (Node->getValueType(0) == MVT::i64) { 1534251607Sdim uint64_t Val = cast<ConstantSDNode>(Node)->getZExtValue(); 1535309124Sdim if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val) && !isInt<32>(Val)) { 1536309124Sdim splitLargeImmediate(ISD::OR, Node, SDValue(), Val - uint32_t(Val), 1537309124Sdim uint32_t(Val)); 1538309124Sdim return; 1539309124Sdim } 1540251607Sdim } 1541251607Sdim break; 1542251607Sdim 1543261991Sdim case SystemZISD::SELECT_CCMASK: { 1544261991Sdim SDValue Op0 = Node->getOperand(0); 1545261991Sdim SDValue Op1 = Node->getOperand(1); 1546261991Sdim // Prefer to put any load first, so that it can be matched as a 1547314564Sdim // conditional load. Likewise for constants in range for LOCHI. 1548314564Sdim if ((Op1.getOpcode() == ISD::LOAD && Op0.getOpcode() != ISD::LOAD) || 1549314564Sdim (Subtarget->hasLoadStoreOnCond2() && 1550314564Sdim Node->getValueType(0).isInteger() && 1551314564Sdim Op1.getOpcode() == ISD::Constant && 1552314564Sdim isInt<16>(cast<ConstantSDNode>(Op1)->getSExtValue()) && 1553314564Sdim !(Op0.getOpcode() == ISD::Constant && 1554314564Sdim isInt<16>(cast<ConstantSDNode>(Op0)->getSExtValue())))) { 1555261991Sdim SDValue CCValid = Node->getOperand(2); 1556261991Sdim SDValue CCMask = Node->getOperand(3); 1557261991Sdim uint64_t ConstCCValid = 1558261991Sdim cast<ConstantSDNode>(CCValid.getNode())->getZExtValue(); 1559261991Sdim uint64_t ConstCCMask = 1560261991Sdim cast<ConstantSDNode>(CCMask.getNode())->getZExtValue(); 1561261991Sdim // Invert the condition. 1562360784Sdim CCMask = CurDAG->getTargetConstant(ConstCCValid ^ ConstCCMask, 1563360784Sdim SDLoc(Node), CCMask.getValueType()); 1564261991Sdim SDValue Op4 = Node->getOperand(4); 1565341825Sdim SDNode *UpdatedNode = 1566341825Sdim CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); 1567341825Sdim if (UpdatedNode != Node) { 1568341825Sdim // In case this node already exists then replace Node with it. 1569341825Sdim ReplaceNode(Node, UpdatedNode); 1570341825Sdim Node = UpdatedNode; 1571341825Sdim } 1572261991Sdim } 1573261991Sdim break; 1574251607Sdim } 1575288943Sdim 1576288943Sdim case ISD::INSERT_VECTOR_ELT: { 1577288943Sdim EVT VT = Node->getValueType(0); 1578314564Sdim unsigned ElemBitSize = VT.getScalarSizeInBits(); 1579309124Sdim if (ElemBitSize == 32) { 1580309124Sdim if (tryGather(Node, SystemZ::VGEF)) 1581309124Sdim return; 1582309124Sdim } else if (ElemBitSize == 64) { 1583309124Sdim if (tryGather(Node, SystemZ::VGEG)) 1584309124Sdim return; 1585309124Sdim } 1586288943Sdim break; 1587261991Sdim } 1588251607Sdim 1589353358Sdim case ISD::BUILD_VECTOR: { 1590353358Sdim auto *BVN = cast<BuildVectorSDNode>(Node); 1591353358Sdim SystemZVectorConstantInfo VCI(BVN); 1592353358Sdim if (VCI.isVectorConstantLegal(*Subtarget)) { 1593353358Sdim loadVectorConstant(VCI, Node); 1594353358Sdim return; 1595353358Sdim } 1596353358Sdim break; 1597353358Sdim } 1598353358Sdim 1599353358Sdim case ISD::ConstantFP: { 1600353358Sdim APFloat Imm = cast<ConstantFPSDNode>(Node)->getValueAPF(); 1601353358Sdim if (Imm.isZero() || Imm.isNegZero()) 1602353358Sdim break; 1603353358Sdim SystemZVectorConstantInfo VCI(Imm); 1604353358Sdim bool Success = VCI.isVectorConstantLegal(*Subtarget); (void)Success; 1605353358Sdim assert(Success && "Expected legal FP immediate"); 1606353358Sdim loadVectorConstant(VCI, Node); 1607353358Sdim return; 1608353358Sdim } 1609353358Sdim 1610288943Sdim case ISD::STORE: { 1611341825Sdim if (tryFoldLoadStoreIntoMemOperand(Node)) 1612341825Sdim return; 1613288943Sdim auto *Store = cast<StoreSDNode>(Node); 1614314564Sdim unsigned ElemBitSize = Store->getValue().getValueSizeInBits(); 1615309124Sdim if (ElemBitSize == 32) { 1616309124Sdim if (tryScatter(Store, SystemZ::VSCEF)) 1617309124Sdim return; 1618309124Sdim } else if (ElemBitSize == 64) { 1619309124Sdim if (tryScatter(Store, SystemZ::VSCEG)) 1620309124Sdim return; 1621309124Sdim } 1622288943Sdim break; 1623288943Sdim } 1624288943Sdim } 1625288943Sdim 1626309124Sdim SelectCode(Node); 1627251607Sdim} 1628251607Sdim 1629251607Sdimbool SystemZDAGToDAGISel:: 1630251607SdimSelectInlineAsmMemoryOperand(const SDValue &Op, 1631288943Sdim unsigned ConstraintID, 1632251607Sdim std::vector<SDValue> &OutOps) { 1633309124Sdim SystemZAddressingMode::AddrForm Form; 1634309124Sdim SystemZAddressingMode::DispRange DispRange; 1635309124Sdim SDValue Base, Disp, Index; 1636309124Sdim 1637288943Sdim switch(ConstraintID) { 1638288943Sdim default: 1639288943Sdim llvm_unreachable("Unexpected asm memory constraint"); 1640288943Sdim case InlineAsm::Constraint_i: 1641288943Sdim case InlineAsm::Constraint_Q: 1642309124Sdim // Accept an address with a short displacement, but no index. 1643309124Sdim Form = SystemZAddressingMode::FormBD; 1644309124Sdim DispRange = SystemZAddressingMode::Disp12Only; 1645309124Sdim break; 1646288943Sdim case InlineAsm::Constraint_R: 1647309124Sdim // Accept an address with a short displacement and an index. 1648309124Sdim Form = SystemZAddressingMode::FormBDXNormal; 1649309124Sdim DispRange = SystemZAddressingMode::Disp12Only; 1650309124Sdim break; 1651288943Sdim case InlineAsm::Constraint_S: 1652309124Sdim // Accept an address with a long displacement, but no index. 1653309124Sdim Form = SystemZAddressingMode::FormBD; 1654309124Sdim DispRange = SystemZAddressingMode::Disp20Only; 1655309124Sdim break; 1656288943Sdim case InlineAsm::Constraint_T: 1657309124Sdim case InlineAsm::Constraint_m: 1658327952Sdim case InlineAsm::Constraint_o: 1659309124Sdim // Accept an address with a long displacement and an index. 1660309124Sdim // m works the same as T, as this is the most general case. 1661327952Sdim // We don't really have any special handling of "offsettable" 1662327952Sdim // memory addresses, so just treat o the same as m. 1663309124Sdim Form = SystemZAddressingMode::FormBDXNormal; 1664309124Sdim DispRange = SystemZAddressingMode::Disp20Only; 1665288943Sdim break; 1666288943Sdim } 1667309124Sdim 1668309124Sdim if (selectBDXAddr(Form, DispRange, Op, Base, Disp, Index)) { 1669314564Sdim const TargetRegisterClass *TRC = 1670314564Sdim Subtarget->getRegisterInfo()->getPointerRegClass(*MF); 1671314564Sdim SDLoc DL(Base); 1672314564Sdim SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32); 1673314564Sdim 1674314564Sdim // Make sure that the base address doesn't go into %r0. 1675314564Sdim // If it's a TargetFrameIndex or a fixed register, we shouldn't do anything. 1676314564Sdim if (Base.getOpcode() != ISD::TargetFrameIndex && 1677314564Sdim Base.getOpcode() != ISD::Register) { 1678314564Sdim Base = 1679314564Sdim SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, 1680314564Sdim DL, Base.getValueType(), 1681314564Sdim Base, RC), 0); 1682314564Sdim } 1683314564Sdim 1684314564Sdim // Make sure that the index register isn't assigned to %r0 either. 1685314564Sdim if (Index.getOpcode() != ISD::Register) { 1686314564Sdim Index = 1687314564Sdim SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, 1688314564Sdim DL, Index.getValueType(), 1689314564Sdim Index, RC), 0); 1690314564Sdim } 1691314564Sdim 1692309124Sdim OutOps.push_back(Base); 1693309124Sdim OutOps.push_back(Disp); 1694309124Sdim OutOps.push_back(Index); 1695309124Sdim return false; 1696309124Sdim } 1697309124Sdim 1698288943Sdim return true; 1699251607Sdim} 1700341825Sdim 1701341825Sdim// IsProfitableToFold - Returns true if is profitable to fold the specific 1702341825Sdim// operand node N of U during instruction selection that starts at Root. 1703341825Sdimbool 1704341825SdimSystemZDAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1705341825Sdim SDNode *Root) const { 1706341825Sdim // We want to avoid folding a LOAD into an ICMP node if as a result 1707341825Sdim // we would be forced to spill the condition code into a GPR. 1708341825Sdim if (N.getOpcode() == ISD::LOAD && U->getOpcode() == SystemZISD::ICMP) { 1709341825Sdim if (!N.hasOneUse() || !U->hasOneUse()) 1710341825Sdim return false; 1711341825Sdim 1712341825Sdim // The user of the CC value will usually be a CopyToReg into the 1713341825Sdim // physical CC register, which in turn is glued and chained to the 1714341825Sdim // actual instruction that uses the CC value. Bail out if we have 1715341825Sdim // anything else than that. 1716341825Sdim SDNode *CCUser = *U->use_begin(); 1717341825Sdim SDNode *CCRegUser = nullptr; 1718341825Sdim if (CCUser->getOpcode() == ISD::CopyToReg || 1719341825Sdim cast<RegisterSDNode>(CCUser->getOperand(1))->getReg() == SystemZ::CC) { 1720341825Sdim for (auto *U : CCUser->uses()) { 1721341825Sdim if (CCRegUser == nullptr) 1722341825Sdim CCRegUser = U; 1723341825Sdim else if (CCRegUser != U) 1724341825Sdim return false; 1725341825Sdim } 1726341825Sdim } 1727341825Sdim if (CCRegUser == nullptr) 1728341825Sdim return false; 1729341825Sdim 1730341825Sdim // If the actual instruction is a branch, the only thing that remains to be 1731341825Sdim // checked is whether the CCUser chain is a predecessor of the load. 1732341825Sdim if (CCRegUser->isMachineOpcode() && 1733341825Sdim CCRegUser->getMachineOpcode() == SystemZ::BRC) 1734341825Sdim return !N->isPredecessorOf(CCUser->getOperand(0).getNode()); 1735341825Sdim 1736341825Sdim // Otherwise, the instruction may have multiple operands, and we need to 1737341825Sdim // verify that none of them are a predecessor of the load. This is exactly 1738341825Sdim // the same check that would be done by common code if the CC setter were 1739341825Sdim // glued to the CC user, so simply invoke that check here. 1740341825Sdim if (!IsLegalToFold(N, U, CCRegUser, OptLevel, false)) 1741341825Sdim return false; 1742341825Sdim } 1743341825Sdim 1744341825Sdim return true; 1745341825Sdim} 1746341825Sdim 1747341825Sdimnamespace { 1748341825Sdim// Represents a sequence for extracting a 0/1 value from an IPM result: 1749341825Sdim// (((X ^ XORValue) + AddValue) >> Bit) 1750341825Sdimstruct IPMConversion { 1751341825Sdim IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit) 1752341825Sdim : XORValue(xorValue), AddValue(addValue), Bit(bit) {} 1753341825Sdim 1754341825Sdim int64_t XORValue; 1755341825Sdim int64_t AddValue; 1756341825Sdim unsigned Bit; 1757341825Sdim}; 1758341825Sdim} // end anonymous namespace 1759341825Sdim 1760341825Sdim// Return a sequence for getting a 1 from an IPM result when CC has a 1761341825Sdim// value in CCMask and a 0 when CC has a value in CCValid & ~CCMask. 1762341825Sdim// The handling of CC values outside CCValid doesn't matter. 1763341825Sdimstatic IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) { 1764341825Sdim // Deal with cases where the result can be taken directly from a bit 1765341825Sdim // of the IPM result. 1766341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3))) 1767341825Sdim return IPMConversion(0, 0, SystemZ::IPM_CC); 1768341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3))) 1769341825Sdim return IPMConversion(0, 0, SystemZ::IPM_CC + 1); 1770341825Sdim 1771341825Sdim // Deal with cases where we can add a value to force the sign bit 1772341825Sdim // to contain the right value. Putting the bit in 31 means we can 1773341825Sdim // use SRL rather than RISBG(L), and also makes it easier to get a 1774341825Sdim // 0/-1 value, so it has priority over the other tests below. 1775341825Sdim // 1776341825Sdim // These sequences rely on the fact that the upper two bits of the 1777341825Sdim // IPM result are zero. 1778341825Sdim uint64_t TopBit = uint64_t(1) << 31; 1779341825Sdim if (CCMask == (CCValid & SystemZ::CCMASK_0)) 1780341825Sdim return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31); 1781341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1))) 1782341825Sdim return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31); 1783341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_0 1784341825Sdim | SystemZ::CCMASK_1 1785341825Sdim | SystemZ::CCMASK_2))) 1786341825Sdim return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31); 1787341825Sdim if (CCMask == (CCValid & SystemZ::CCMASK_3)) 1788341825Sdim return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31); 1789341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_1 1790341825Sdim | SystemZ::CCMASK_2 1791341825Sdim | SystemZ::CCMASK_3))) 1792341825Sdim return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31); 1793341825Sdim 1794341825Sdim // Next try inverting the value and testing a bit. 0/1 could be 1795341825Sdim // handled this way too, but we dealt with that case above. 1796341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2))) 1797341825Sdim return IPMConversion(-1, 0, SystemZ::IPM_CC); 1798341825Sdim 1799341825Sdim // Handle cases where adding a value forces a non-sign bit to contain 1800341825Sdim // the right value. 1801341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2))) 1802341825Sdim return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1); 1803341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3))) 1804341825Sdim return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1); 1805341825Sdim 1806341825Sdim // The remaining cases are 1, 2, 0/1/3 and 0/2/3. All these are 1807341825Sdim // can be done by inverting the low CC bit and applying one of the 1808341825Sdim // sign-based extractions above. 1809341825Sdim if (CCMask == (CCValid & SystemZ::CCMASK_1)) 1810341825Sdim return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31); 1811341825Sdim if (CCMask == (CCValid & SystemZ::CCMASK_2)) 1812341825Sdim return IPMConversion(1 << SystemZ::IPM_CC, 1813341825Sdim TopBit - (3 << SystemZ::IPM_CC), 31); 1814341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_0 1815341825Sdim | SystemZ::CCMASK_1 1816341825Sdim | SystemZ::CCMASK_3))) 1817341825Sdim return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31); 1818341825Sdim if (CCMask == (CCValid & (SystemZ::CCMASK_0 1819341825Sdim | SystemZ::CCMASK_2 1820341825Sdim | SystemZ::CCMASK_3))) 1821341825Sdim return IPMConversion(1 << SystemZ::IPM_CC, 1822341825Sdim TopBit - (1 << SystemZ::IPM_CC), 31); 1823341825Sdim 1824341825Sdim llvm_unreachable("Unexpected CC combination"); 1825341825Sdim} 1826341825Sdim 1827341825SdimSDValue SystemZDAGToDAGISel::expandSelectBoolean(SDNode *Node) { 1828341825Sdim auto *TrueOp = dyn_cast<ConstantSDNode>(Node->getOperand(0)); 1829341825Sdim auto *FalseOp = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1830341825Sdim if (!TrueOp || !FalseOp) 1831341825Sdim return SDValue(); 1832341825Sdim if (FalseOp->getZExtValue() != 0) 1833341825Sdim return SDValue(); 1834341825Sdim if (TrueOp->getSExtValue() != 1 && TrueOp->getSExtValue() != -1) 1835341825Sdim return SDValue(); 1836341825Sdim 1837341825Sdim auto *CCValidOp = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1838341825Sdim auto *CCMaskOp = dyn_cast<ConstantSDNode>(Node->getOperand(3)); 1839341825Sdim if (!CCValidOp || !CCMaskOp) 1840341825Sdim return SDValue(); 1841341825Sdim int CCValid = CCValidOp->getZExtValue(); 1842341825Sdim int CCMask = CCMaskOp->getZExtValue(); 1843341825Sdim 1844341825Sdim SDLoc DL(Node); 1845341825Sdim SDValue CCReg = Node->getOperand(4); 1846341825Sdim IPMConversion IPM = getIPMConversion(CCValid, CCMask); 1847341825Sdim SDValue Result = CurDAG->getNode(SystemZISD::IPM, DL, MVT::i32, CCReg); 1848341825Sdim 1849341825Sdim if (IPM.XORValue) 1850341825Sdim Result = CurDAG->getNode(ISD::XOR, DL, MVT::i32, Result, 1851341825Sdim CurDAG->getConstant(IPM.XORValue, DL, MVT::i32)); 1852341825Sdim 1853341825Sdim if (IPM.AddValue) 1854341825Sdim Result = CurDAG->getNode(ISD::ADD, DL, MVT::i32, Result, 1855341825Sdim CurDAG->getConstant(IPM.AddValue, DL, MVT::i32)); 1856341825Sdim 1857341825Sdim EVT VT = Node->getValueType(0); 1858341825Sdim if (VT == MVT::i32 && IPM.Bit == 31) { 1859341825Sdim unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; 1860341825Sdim Result = CurDAG->getNode(ShiftOp, DL, MVT::i32, Result, 1861341825Sdim CurDAG->getConstant(IPM.Bit, DL, MVT::i32)); 1862341825Sdim } else { 1863341825Sdim if (VT != MVT::i32) 1864341825Sdim Result = CurDAG->getNode(ISD::ANY_EXTEND, DL, VT, Result); 1865341825Sdim 1866341825Sdim if (TrueOp->getSExtValue() == 1) { 1867341825Sdim // The SHR/AND sequence should get optimized to an RISBG. 1868341825Sdim Result = CurDAG->getNode(ISD::SRL, DL, VT, Result, 1869341825Sdim CurDAG->getConstant(IPM.Bit, DL, MVT::i32)); 1870341825Sdim Result = CurDAG->getNode(ISD::AND, DL, VT, Result, 1871341825Sdim CurDAG->getConstant(1, DL, VT)); 1872341825Sdim } else { 1873341825Sdim // Sign-extend from IPM.Bit using a pair of shifts. 1874341825Sdim int ShlAmt = VT.getSizeInBits() - 1 - IPM.Bit; 1875341825Sdim int SraAmt = VT.getSizeInBits() - 1; 1876341825Sdim Result = CurDAG->getNode(ISD::SHL, DL, VT, Result, 1877341825Sdim CurDAG->getConstant(ShlAmt, DL, MVT::i32)); 1878341825Sdim Result = CurDAG->getNode(ISD::SRA, DL, VT, Result, 1879341825Sdim CurDAG->getConstant(SraAmt, DL, MVT::i32)); 1880341825Sdim } 1881341825Sdim } 1882341825Sdim 1883341825Sdim return Result; 1884341825Sdim} 1885341825Sdim 1886341825Sdimvoid SystemZDAGToDAGISel::PreprocessISelDAG() { 1887341825Sdim // If we have conditional immediate loads, we always prefer 1888341825Sdim // using those over an IPM sequence. 1889341825Sdim if (Subtarget->hasLoadStoreOnCond2()) 1890341825Sdim return; 1891341825Sdim 1892341825Sdim bool MadeChange = false; 1893341825Sdim 1894341825Sdim for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 1895341825Sdim E = CurDAG->allnodes_end(); 1896341825Sdim I != E;) { 1897341825Sdim SDNode *N = &*I++; 1898341825Sdim if (N->use_empty()) 1899341825Sdim continue; 1900341825Sdim 1901341825Sdim SDValue Res; 1902341825Sdim switch (N->getOpcode()) { 1903341825Sdim default: break; 1904341825Sdim case SystemZISD::SELECT_CCMASK: 1905341825Sdim Res = expandSelectBoolean(N); 1906341825Sdim break; 1907341825Sdim } 1908341825Sdim 1909341825Sdim if (Res) { 1910341825Sdim LLVM_DEBUG(dbgs() << "SystemZ DAG preprocessing replacing:\nOld: "); 1911341825Sdim LLVM_DEBUG(N->dump(CurDAG)); 1912341825Sdim LLVM_DEBUG(dbgs() << "\nNew: "); 1913341825Sdim LLVM_DEBUG(Res.getNode()->dump(CurDAG)); 1914341825Sdim LLVM_DEBUG(dbgs() << "\n"); 1915341825Sdim 1916341825Sdim CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res); 1917341825Sdim MadeChange = true; 1918341825Sdim } 1919341825Sdim } 1920341825Sdim 1921341825Sdim if (MadeChange) 1922341825Sdim CurDAG->RemoveDeadNodes(); 1923341825Sdim} 1924