1193323Sed//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===// 2193323Sed// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6193323Sed// 7193323Sed//===----------------------------------------------------------------------===// 8193323Sed// 9193323Sed// This file implements the MSP430TargetLowering class. 10193323Sed// 11193323Sed//===----------------------------------------------------------------------===// 12193323Sed 13193323Sed#include "MSP430ISelLowering.h" 14193323Sed#include "MSP430.h" 15200581Srdivacky#include "MSP430MachineFunctionInfo.h" 16249423Sdim#include "MSP430Subtarget.h" 17193323Sed#include "MSP430TargetMachine.h" 18193323Sed#include "llvm/CodeGen/CallingConvLower.h" 19193323Sed#include "llvm/CodeGen/MachineFrameInfo.h" 20193323Sed#include "llvm/CodeGen/MachineFunction.h" 21193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 22193323Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 23193323Sed#include "llvm/CodeGen/SelectionDAGISel.h" 24203954Srdivacky#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 25193323Sed#include "llvm/CodeGen/ValueTypes.h" 26249423Sdim#include "llvm/IR/CallingConv.h" 27249423Sdim#include "llvm/IR/DerivedTypes.h" 28249423Sdim#include "llvm/IR/Function.h" 29249423Sdim#include "llvm/IR/GlobalAlias.h" 30249423Sdim#include "llvm/IR/GlobalVariable.h" 31249423Sdim#include "llvm/IR/Intrinsics.h" 32200581Srdivacky#include "llvm/Support/CommandLine.h" 33193323Sed#include "llvm/Support/Debug.h" 34198090Srdivacky#include "llvm/Support/ErrorHandling.h" 35198090Srdivacky#include "llvm/Support/raw_ostream.h" 36193323Sedusing namespace llvm; 37193323Sed 38276479Sdim#define DEBUG_TYPE "msp430-lower" 39276479Sdim 40360784Sdimstatic cl::opt<bool>MSP430NoLegalImmediate( 41360784Sdim "msp430-no-legal-immediate", cl::Hidden, 42360784Sdim cl::desc("Enable non legal immediates (for testing purposes only)"), 43360784Sdim cl::init(false)); 44360784Sdim 45288943SdimMSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM, 46288943Sdim const MSP430Subtarget &STI) 47280031Sdim : TargetLowering(TM) { 48193323Sed 49193323Sed // Set up the register classes. 50239462Sdim addRegisterClass(MVT::i8, &MSP430::GR8RegClass); 51239462Sdim addRegisterClass(MVT::i16, &MSP430::GR16RegClass); 52193323Sed 53193323Sed // Compute derived properties from the register classes 54288943Sdim computeRegisterProperties(STI.getRegisterInfo()); 55193323Sed 56193323Sed // Provide all sorts of operation actions 57280031Sdim setStackPointerRegisterToSaveRestore(MSP430::SP); 58193323Sed setBooleanContents(ZeroOrOneBooleanContent); 59226633Sdim setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 60193323Sed 61199481Srdivacky // We have post-incremented loads / stores. 62199481Srdivacky setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 63199481Srdivacky setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 64199481Srdivacky 65280031Sdim for (MVT VT : MVT::integer_valuetypes()) { 66280031Sdim setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 67280031Sdim setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 68280031Sdim setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 69280031Sdim setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 70280031Sdim setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); 71280031Sdim } 72193323Sed 73193323Sed // We don't have any truncstores 74193323Sed setTruncStoreAction(MVT::i16, MVT::i8, Expand); 75193323Sed 76193323Sed setOperationAction(ISD::SRA, MVT::i8, Custom); 77193323Sed setOperationAction(ISD::SHL, MVT::i8, Custom); 78193323Sed setOperationAction(ISD::SRL, MVT::i8, Custom); 79193323Sed setOperationAction(ISD::SRA, MVT::i16, Custom); 80193323Sed setOperationAction(ISD::SHL, MVT::i16, Custom); 81193323Sed setOperationAction(ISD::SRL, MVT::i16, Custom); 82193323Sed setOperationAction(ISD::ROTL, MVT::i8, Expand); 83193323Sed setOperationAction(ISD::ROTR, MVT::i8, Expand); 84193323Sed setOperationAction(ISD::ROTL, MVT::i16, Expand); 85193323Sed setOperationAction(ISD::ROTR, MVT::i16, Expand); 86193323Sed setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); 87193323Sed setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom); 88207618Srdivacky setOperationAction(ISD::BlockAddress, MVT::i16, Custom); 89193323Sed setOperationAction(ISD::BR_JT, MVT::Other, Expand); 90193323Sed setOperationAction(ISD::BR_CC, MVT::i8, Custom); 91193323Sed setOperationAction(ISD::BR_CC, MVT::i16, Custom); 92193323Sed setOperationAction(ISD::BRCOND, MVT::Other, Expand); 93200581Srdivacky setOperationAction(ISD::SETCC, MVT::i8, Custom); 94200581Srdivacky setOperationAction(ISD::SETCC, MVT::i16, Custom); 95193323Sed setOperationAction(ISD::SELECT, MVT::i8, Expand); 96193323Sed setOperationAction(ISD::SELECT, MVT::i16, Expand); 97193323Sed setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); 98193323Sed setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 99193323Sed setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); 100198090Srdivacky setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); 101198090Srdivacky setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); 102344779Sdim setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 103344779Sdim setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 104193323Sed 105198090Srdivacky setOperationAction(ISD::CTTZ, MVT::i8, Expand); 106198090Srdivacky setOperationAction(ISD::CTTZ, MVT::i16, Expand); 107198090Srdivacky setOperationAction(ISD::CTLZ, MVT::i8, Expand); 108198090Srdivacky setOperationAction(ISD::CTLZ, MVT::i16, Expand); 109198090Srdivacky setOperationAction(ISD::CTPOP, MVT::i8, Expand); 110198090Srdivacky setOperationAction(ISD::CTPOP, MVT::i16, Expand); 111198090Srdivacky 112198090Srdivacky setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand); 113198090Srdivacky setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); 114198090Srdivacky setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand); 115198090Srdivacky setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); 116198090Srdivacky setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand); 117198090Srdivacky setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); 118198090Srdivacky 119198090Srdivacky setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 120198090Srdivacky 121193323Sed // FIXME: Implement efficiently multiplication by a constant 122321369Sdim setOperationAction(ISD::MUL, MVT::i8, Promote); 123321369Sdim setOperationAction(ISD::MULHS, MVT::i8, Promote); 124321369Sdim setOperationAction(ISD::MULHU, MVT::i8, Promote); 125321369Sdim setOperationAction(ISD::SMUL_LOHI, MVT::i8, Promote); 126321369Sdim setOperationAction(ISD::UMUL_LOHI, MVT::i8, Promote); 127321369Sdim setOperationAction(ISD::MUL, MVT::i16, LibCall); 128193323Sed setOperationAction(ISD::MULHS, MVT::i16, Expand); 129193323Sed setOperationAction(ISD::MULHU, MVT::i16, Expand); 130193323Sed setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); 131193323Sed setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); 132193323Sed 133321369Sdim setOperationAction(ISD::UDIV, MVT::i8, Promote); 134321369Sdim setOperationAction(ISD::UDIVREM, MVT::i8, Promote); 135321369Sdim setOperationAction(ISD::UREM, MVT::i8, Promote); 136321369Sdim setOperationAction(ISD::SDIV, MVT::i8, Promote); 137321369Sdim setOperationAction(ISD::SDIVREM, MVT::i8, Promote); 138321369Sdim setOperationAction(ISD::SREM, MVT::i8, Promote); 139321369Sdim setOperationAction(ISD::UDIV, MVT::i16, LibCall); 140193323Sed setOperationAction(ISD::UDIVREM, MVT::i16, Expand); 141321369Sdim setOperationAction(ISD::UREM, MVT::i16, LibCall); 142321369Sdim setOperationAction(ISD::SDIV, MVT::i16, LibCall); 143193323Sed setOperationAction(ISD::SDIVREM, MVT::i16, Expand); 144321369Sdim setOperationAction(ISD::SREM, MVT::i16, LibCall); 145200581Srdivacky 146249423Sdim // varargs support 147249423Sdim setOperationAction(ISD::VASTART, MVT::Other, Custom); 148249423Sdim setOperationAction(ISD::VAARG, MVT::Other, Expand); 149249423Sdim setOperationAction(ISD::VAEND, MVT::Other, Expand); 150249423Sdim setOperationAction(ISD::VACOPY, MVT::Other, Expand); 151261991Sdim setOperationAction(ISD::JumpTable, MVT::i16, Custom); 152249423Sdim 153321369Sdim // EABI Libcalls - EABI Section 6.2 154321369Sdim const struct { 155321369Sdim const RTLIB::Libcall Op; 156321369Sdim const char * const Name; 157321369Sdim const ISD::CondCode Cond; 158321369Sdim } LibraryCalls[] = { 159321369Sdim // Floating point conversions - EABI Table 6 160321369Sdim { RTLIB::FPROUND_F64_F32, "__mspabi_cvtdf", ISD::SETCC_INVALID }, 161321369Sdim { RTLIB::FPEXT_F32_F64, "__mspabi_cvtfd", ISD::SETCC_INVALID }, 162321369Sdim // The following is NOT implemented in libgcc 163321369Sdim //{ RTLIB::FPTOSINT_F64_I16, "__mspabi_fixdi", ISD::SETCC_INVALID }, 164321369Sdim { RTLIB::FPTOSINT_F64_I32, "__mspabi_fixdli", ISD::SETCC_INVALID }, 165321369Sdim { RTLIB::FPTOSINT_F64_I64, "__mspabi_fixdlli", ISD::SETCC_INVALID }, 166321369Sdim // The following is NOT implemented in libgcc 167321369Sdim //{ RTLIB::FPTOUINT_F64_I16, "__mspabi_fixdu", ISD::SETCC_INVALID }, 168321369Sdim { RTLIB::FPTOUINT_F64_I32, "__mspabi_fixdul", ISD::SETCC_INVALID }, 169321369Sdim { RTLIB::FPTOUINT_F64_I64, "__mspabi_fixdull", ISD::SETCC_INVALID }, 170321369Sdim // The following is NOT implemented in libgcc 171321369Sdim //{ RTLIB::FPTOSINT_F32_I16, "__mspabi_fixfi", ISD::SETCC_INVALID }, 172321369Sdim { RTLIB::FPTOSINT_F32_I32, "__mspabi_fixfli", ISD::SETCC_INVALID }, 173321369Sdim { RTLIB::FPTOSINT_F32_I64, "__mspabi_fixflli", ISD::SETCC_INVALID }, 174321369Sdim // The following is NOT implemented in libgcc 175321369Sdim //{ RTLIB::FPTOUINT_F32_I16, "__mspabi_fixfu", ISD::SETCC_INVALID }, 176321369Sdim { RTLIB::FPTOUINT_F32_I32, "__mspabi_fixful", ISD::SETCC_INVALID }, 177321369Sdim { RTLIB::FPTOUINT_F32_I64, "__mspabi_fixfull", ISD::SETCC_INVALID }, 178321369Sdim // TODO The following IS implemented in libgcc 179321369Sdim //{ RTLIB::SINTTOFP_I16_F64, "__mspabi_fltid", ISD::SETCC_INVALID }, 180321369Sdim { RTLIB::SINTTOFP_I32_F64, "__mspabi_fltlid", ISD::SETCC_INVALID }, 181321369Sdim // TODO The following IS implemented in libgcc but is not in the EABI 182321369Sdim { RTLIB::SINTTOFP_I64_F64, "__mspabi_fltllid", ISD::SETCC_INVALID }, 183321369Sdim // TODO The following IS implemented in libgcc 184321369Sdim //{ RTLIB::UINTTOFP_I16_F64, "__mspabi_fltud", ISD::SETCC_INVALID }, 185321369Sdim { RTLIB::UINTTOFP_I32_F64, "__mspabi_fltuld", ISD::SETCC_INVALID }, 186321369Sdim // The following IS implemented in libgcc but is not in the EABI 187321369Sdim { RTLIB::UINTTOFP_I64_F64, "__mspabi_fltulld", ISD::SETCC_INVALID }, 188321369Sdim // TODO The following IS implemented in libgcc 189321369Sdim //{ RTLIB::SINTTOFP_I16_F32, "__mspabi_fltif", ISD::SETCC_INVALID }, 190321369Sdim { RTLIB::SINTTOFP_I32_F32, "__mspabi_fltlif", ISD::SETCC_INVALID }, 191321369Sdim // TODO The following IS implemented in libgcc but is not in the EABI 192321369Sdim { RTLIB::SINTTOFP_I64_F32, "__mspabi_fltllif", ISD::SETCC_INVALID }, 193321369Sdim // TODO The following IS implemented in libgcc 194321369Sdim //{ RTLIB::UINTTOFP_I16_F32, "__mspabi_fltuf", ISD::SETCC_INVALID }, 195321369Sdim { RTLIB::UINTTOFP_I32_F32, "__mspabi_fltulf", ISD::SETCC_INVALID }, 196321369Sdim // The following IS implemented in libgcc but is not in the EABI 197321369Sdim { RTLIB::UINTTOFP_I64_F32, "__mspabi_fltullf", ISD::SETCC_INVALID }, 198321369Sdim 199321369Sdim // Floating point comparisons - EABI Table 7 200321369Sdim { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ }, 201321369Sdim { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE }, 202321369Sdim { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE }, 203321369Sdim { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT }, 204321369Sdim { RTLIB::OLE_F64, "__mspabi_cmpd", ISD::SETLE }, 205321369Sdim { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT }, 206321369Sdim { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ }, 207321369Sdim { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE }, 208321369Sdim { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE }, 209321369Sdim { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT }, 210321369Sdim { RTLIB::OLE_F32, "__mspabi_cmpf", ISD::SETLE }, 211321369Sdim { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT }, 212321369Sdim 213321369Sdim // Floating point arithmetic - EABI Table 8 214321369Sdim { RTLIB::ADD_F64, "__mspabi_addd", ISD::SETCC_INVALID }, 215321369Sdim { RTLIB::ADD_F32, "__mspabi_addf", ISD::SETCC_INVALID }, 216321369Sdim { RTLIB::DIV_F64, "__mspabi_divd", ISD::SETCC_INVALID }, 217321369Sdim { RTLIB::DIV_F32, "__mspabi_divf", ISD::SETCC_INVALID }, 218321369Sdim { RTLIB::MUL_F64, "__mspabi_mpyd", ISD::SETCC_INVALID }, 219321369Sdim { RTLIB::MUL_F32, "__mspabi_mpyf", ISD::SETCC_INVALID }, 220321369Sdim { RTLIB::SUB_F64, "__mspabi_subd", ISD::SETCC_INVALID }, 221321369Sdim { RTLIB::SUB_F32, "__mspabi_subf", ISD::SETCC_INVALID }, 222321369Sdim // The following are NOT implemented in libgcc 223321369Sdim // { RTLIB::NEG_F64, "__mspabi_negd", ISD::SETCC_INVALID }, 224321369Sdim // { RTLIB::NEG_F32, "__mspabi_negf", ISD::SETCC_INVALID }, 225321369Sdim 226321369Sdim // Universal Integer Operations - EABI Table 9 227321369Sdim { RTLIB::SDIV_I16, "__mspabi_divi", ISD::SETCC_INVALID }, 228321369Sdim { RTLIB::SDIV_I32, "__mspabi_divli", ISD::SETCC_INVALID }, 229321369Sdim { RTLIB::SDIV_I64, "__mspabi_divlli", ISD::SETCC_INVALID }, 230321369Sdim { RTLIB::UDIV_I16, "__mspabi_divu", ISD::SETCC_INVALID }, 231321369Sdim { RTLIB::UDIV_I32, "__mspabi_divul", ISD::SETCC_INVALID }, 232321369Sdim { RTLIB::UDIV_I64, "__mspabi_divull", ISD::SETCC_INVALID }, 233321369Sdim { RTLIB::SREM_I16, "__mspabi_remi", ISD::SETCC_INVALID }, 234321369Sdim { RTLIB::SREM_I32, "__mspabi_remli", ISD::SETCC_INVALID }, 235321369Sdim { RTLIB::SREM_I64, "__mspabi_remlli", ISD::SETCC_INVALID }, 236321369Sdim { RTLIB::UREM_I16, "__mspabi_remu", ISD::SETCC_INVALID }, 237321369Sdim { RTLIB::UREM_I32, "__mspabi_remul", ISD::SETCC_INVALID }, 238321369Sdim { RTLIB::UREM_I64, "__mspabi_remull", ISD::SETCC_INVALID }, 239321369Sdim 240344779Sdim // Bitwise Operations - EABI Table 10 241344779Sdim // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc 242344779Sdim { RTLIB::SRL_I32, "__mspabi_srll", ISD::SETCC_INVALID }, 243344779Sdim { RTLIB::SRA_I32, "__mspabi_sral", ISD::SETCC_INVALID }, 244344779Sdim { RTLIB::SHL_I32, "__mspabi_slll", ISD::SETCC_INVALID }, 245344779Sdim // __mspabi_[srlll/srall/sllll/rlli/rlll] are NOT implemented in libgcc 246344779Sdim 247321369Sdim }; 248321369Sdim 249321369Sdim for (const auto &LC : LibraryCalls) { 250321369Sdim setLibcallName(LC.Op, LC.Name); 251321369Sdim if (LC.Cond != ISD::SETCC_INVALID) 252321369Sdim setCmpLibcallCC(LC.Op, LC.Cond); 253200581Srdivacky } 254223017Sdim 255321369Sdim if (STI.hasHWMult16()) { 256321369Sdim const struct { 257321369Sdim const RTLIB::Libcall Op; 258321369Sdim const char * const Name; 259321369Sdim } LibraryCalls[] = { 260321369Sdim // Integer Multiply - EABI Table 9 261321369Sdim { RTLIB::MUL_I16, "__mspabi_mpyi_hw" }, 262321369Sdim { RTLIB::MUL_I32, "__mspabi_mpyl_hw" }, 263321369Sdim { RTLIB::MUL_I64, "__mspabi_mpyll_hw" }, 264321369Sdim // TODO The __mspabi_mpysl*_hw functions ARE implemented in libgcc 265321369Sdim // TODO The __mspabi_mpyul*_hw functions ARE implemented in libgcc 266321369Sdim }; 267321369Sdim for (const auto &LC : LibraryCalls) { 268321369Sdim setLibcallName(LC.Op, LC.Name); 269321369Sdim } 270321369Sdim } else if (STI.hasHWMult32()) { 271321369Sdim const struct { 272321369Sdim const RTLIB::Libcall Op; 273321369Sdim const char * const Name; 274321369Sdim } LibraryCalls[] = { 275321369Sdim // Integer Multiply - EABI Table 9 276321369Sdim { RTLIB::MUL_I16, "__mspabi_mpyi_hw" }, 277321369Sdim { RTLIB::MUL_I32, "__mspabi_mpyl_hw32" }, 278321369Sdim { RTLIB::MUL_I64, "__mspabi_mpyll_hw32" }, 279321369Sdim // TODO The __mspabi_mpysl*_hw32 functions ARE implemented in libgcc 280321369Sdim // TODO The __mspabi_mpyul*_hw32 functions ARE implemented in libgcc 281321369Sdim }; 282321369Sdim for (const auto &LC : LibraryCalls) { 283321369Sdim setLibcallName(LC.Op, LC.Name); 284321369Sdim } 285321369Sdim } else if (STI.hasHWMultF5()) { 286321369Sdim const struct { 287321369Sdim const RTLIB::Libcall Op; 288321369Sdim const char * const Name; 289321369Sdim } LibraryCalls[] = { 290321369Sdim // Integer Multiply - EABI Table 9 291321369Sdim { RTLIB::MUL_I16, "__mspabi_mpyi_f5hw" }, 292321369Sdim { RTLIB::MUL_I32, "__mspabi_mpyl_f5hw" }, 293321369Sdim { RTLIB::MUL_I64, "__mspabi_mpyll_f5hw" }, 294321369Sdim // TODO The __mspabi_mpysl*_f5hw functions ARE implemented in libgcc 295321369Sdim // TODO The __mspabi_mpyul*_f5hw functions ARE implemented in libgcc 296321369Sdim }; 297321369Sdim for (const auto &LC : LibraryCalls) { 298321369Sdim setLibcallName(LC.Op, LC.Name); 299321369Sdim } 300321369Sdim } else { // NoHWMult 301321369Sdim const struct { 302321369Sdim const RTLIB::Libcall Op; 303321369Sdim const char * const Name; 304321369Sdim } LibraryCalls[] = { 305321369Sdim // Integer Multiply - EABI Table 9 306321369Sdim { RTLIB::MUL_I16, "__mspabi_mpyi" }, 307321369Sdim { RTLIB::MUL_I32, "__mspabi_mpyl" }, 308321369Sdim { RTLIB::MUL_I64, "__mspabi_mpyll" }, 309321369Sdim // The __mspabi_mpysl* functions are NOT implemented in libgcc 310321369Sdim // The __mspabi_mpyul* functions are NOT implemented in libgcc 311321369Sdim }; 312321369Sdim for (const auto &LC : LibraryCalls) { 313321369Sdim setLibcallName(LC.Op, LC.Name); 314321369Sdim } 315321369Sdim setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::MSP430_BUILTIN); 316321369Sdim } 317321369Sdim 318321369Sdim // Several of the runtime library functions use a special calling conv 319321369Sdim setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::MSP430_BUILTIN); 320321369Sdim setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::MSP430_BUILTIN); 321321369Sdim setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::MSP430_BUILTIN); 322321369Sdim setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::MSP430_BUILTIN); 323321369Sdim setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::MSP430_BUILTIN); 324321369Sdim setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::MSP430_BUILTIN); 325321369Sdim setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::MSP430_BUILTIN); 326321369Sdim setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::MSP430_BUILTIN); 327321369Sdim setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::MSP430_BUILTIN); 328321369Sdim setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::MSP430_BUILTIN); 329321369Sdim setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::MSP430_BUILTIN); 330321369Sdim setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::MSP430_BUILTIN); 331321369Sdim setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::MSP430_BUILTIN); 332321369Sdim setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::MSP430_BUILTIN); 333321369Sdim // TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll 334321369Sdim 335360784Sdim setMinFunctionAlignment(Align(2)); 336360784Sdim setPrefFunctionAlignment(Align(2)); 337193323Sed} 338193323Sed 339207618SrdivackySDValue MSP430TargetLowering::LowerOperation(SDValue Op, 340207618Srdivacky SelectionDAG &DAG) const { 341193323Sed switch (Op.getOpcode()) { 342193323Sed case ISD::SHL: // FALLTHROUGH 343193323Sed case ISD::SRL: 344193323Sed case ISD::SRA: return LowerShifts(Op, DAG); 345193323Sed case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 346207618Srdivacky case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 347193323Sed case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 348200581Srdivacky case ISD::SETCC: return LowerSETCC(Op, DAG); 349193323Sed case ISD::BR_CC: return LowerBR_CC(Op, DAG); 350193323Sed case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 351193323Sed case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); 352200581Srdivacky case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 353200581Srdivacky case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 354249423Sdim case ISD::VASTART: return LowerVASTART(Op, DAG); 355261991Sdim case ISD::JumpTable: return LowerJumpTable(Op, DAG); 356193323Sed default: 357198090Srdivacky llvm_unreachable("unimplemented operand"); 358193323Sed } 359193323Sed} 360193323Sed 361360784Sdim// Define non profitable transforms into shifts 362360784Sdimbool MSP430TargetLowering::shouldAvoidTransformToShift(EVT VT, 363360784Sdim unsigned Amount) const { 364360784Sdim return !(Amount == 8 || Amount == 9 || Amount<=2); 365360784Sdim} 366360784Sdim 367360784Sdim// Implemented to verify test case assertions in 368360784Sdim// tests/codegen/msp430/shift-amount-threshold-b.ll 369360784Sdimbool MSP430TargetLowering::isLegalICmpImmediate(int64_t Immed) const { 370360784Sdim if (MSP430NoLegalImmediate) 371360784Sdim return Immed >= -32 && Immed < 32; 372360784Sdim return TargetLowering::isLegalICmpImmediate(Immed); 373360784Sdim} 374360784Sdim 375193323Sed//===----------------------------------------------------------------------===// 376198090Srdivacky// MSP430 Inline Assembly Support 377198090Srdivacky//===----------------------------------------------------------------------===// 378198090Srdivacky 379198090Srdivacky/// getConstraintType - Given a constraint letter, return the type of 380198090Srdivacky/// constraint it is for this target. 381198090SrdivackyTargetLowering::ConstraintType 382288943SdimMSP430TargetLowering::getConstraintType(StringRef Constraint) const { 383198090Srdivacky if (Constraint.size() == 1) { 384198090Srdivacky switch (Constraint[0]) { 385198090Srdivacky case 'r': 386198090Srdivacky return C_RegisterClass; 387198090Srdivacky default: 388198090Srdivacky break; 389198090Srdivacky } 390198090Srdivacky } 391198090Srdivacky return TargetLowering::getConstraintType(Constraint); 392198090Srdivacky} 393198090Srdivacky 394288943Sdimstd::pair<unsigned, const TargetRegisterClass *> 395288943SdimMSP430TargetLowering::getRegForInlineAsmConstraint( 396288943Sdim const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { 397198090Srdivacky if (Constraint.size() == 1) { 398198090Srdivacky // GCC Constraint Letters 399198090Srdivacky switch (Constraint[0]) { 400198090Srdivacky default: break; 401198090Srdivacky case 'r': // GENERAL_REGS 402198090Srdivacky if (VT == MVT::i8) 403239462Sdim return std::make_pair(0U, &MSP430::GR8RegClass); 404198090Srdivacky 405239462Sdim return std::make_pair(0U, &MSP430::GR16RegClass); 406198090Srdivacky } 407198090Srdivacky } 408198090Srdivacky 409288943Sdim return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 410198090Srdivacky} 411198090Srdivacky 412198090Srdivacky//===----------------------------------------------------------------------===// 413193323Sed// Calling Convention Implementation 414193323Sed//===----------------------------------------------------------------------===// 415193323Sed 416193323Sed#include "MSP430GenCallingConv.inc" 417193323Sed 418261991Sdim/// For each argument in a function store the number of pieces it is composed 419261991Sdim/// of. 420261991Sdimtemplate<typename ArgT> 421261991Sdimstatic void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args, 422261991Sdim SmallVectorImpl<unsigned> &Out) { 423321369Sdim unsigned CurrentArgIndex; 424321369Sdim 425321369Sdim if (Args.empty()) 426321369Sdim return; 427321369Sdim 428321369Sdim CurrentArgIndex = Args[0].OrigArgIndex; 429321369Sdim Out.push_back(0); 430321369Sdim 431321369Sdim for (auto &Arg : Args) { 432321369Sdim if (CurrentArgIndex == Arg.OrigArgIndex) { 433321369Sdim Out.back() += 1; 434261991Sdim } else { 435261991Sdim Out.push_back(1); 436321369Sdim CurrentArgIndex = Arg.OrigArgIndex; 437261991Sdim } 438261991Sdim } 439261991Sdim} 440261991Sdim 441261991Sdimstatic void AnalyzeVarArgs(CCState &State, 442261991Sdim const SmallVectorImpl<ISD::OutputArg> &Outs) { 443261991Sdim State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack); 444261991Sdim} 445261991Sdim 446261991Sdimstatic void AnalyzeVarArgs(CCState &State, 447261991Sdim const SmallVectorImpl<ISD::InputArg> &Ins) { 448261991Sdim State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack); 449261991Sdim} 450261991Sdim 451261991Sdim/// Analyze incoming and outgoing function arguments. We need custom C++ code 452261991Sdim/// to handle special constraints in the ABI like reversing the order of the 453261991Sdim/// pieces of splitted arguments. In addition, all pieces of a certain argument 454261991Sdim/// have to be passed either using registers or the stack but never mixing both. 455261991Sdimtemplate<typename ArgT> 456261991Sdimstatic void AnalyzeArguments(CCState &State, 457261991Sdim SmallVectorImpl<CCValAssign> &ArgLocs, 458261991Sdim const SmallVectorImpl<ArgT> &Args) { 459321369Sdim static const MCPhysReg CRegList[] = { 460321369Sdim MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 461261991Sdim }; 462321369Sdim static const unsigned CNbRegs = array_lengthof(CRegList); 463321369Sdim static const MCPhysReg BuiltinRegList[] = { 464321369Sdim MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, 465321369Sdim MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 466321369Sdim }; 467321369Sdim static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList); 468261991Sdim 469321369Sdim ArrayRef<MCPhysReg> RegList; 470321369Sdim unsigned NbRegs; 471321369Sdim 472321369Sdim bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN); 473321369Sdim if (Builtin) { 474321369Sdim RegList = BuiltinRegList; 475321369Sdim NbRegs = BuiltinNbRegs; 476321369Sdim } else { 477321369Sdim RegList = CRegList; 478321369Sdim NbRegs = CNbRegs; 479321369Sdim } 480321369Sdim 481261991Sdim if (State.isVarArg()) { 482261991Sdim AnalyzeVarArgs(State, Args); 483261991Sdim return; 484261991Sdim } 485261991Sdim 486261991Sdim SmallVector<unsigned, 4> ArgsParts; 487261991Sdim ParseFunctionArgs(Args, ArgsParts); 488261991Sdim 489321369Sdim if (Builtin) { 490321369Sdim assert(ArgsParts.size() == 2 && 491321369Sdim "Builtin calling convention requires two arguments"); 492321369Sdim } 493321369Sdim 494261991Sdim unsigned RegsLeft = NbRegs; 495321369Sdim bool UsedStack = false; 496261991Sdim unsigned ValNo = 0; 497261991Sdim 498261991Sdim for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) { 499261991Sdim MVT ArgVT = Args[ValNo].VT; 500261991Sdim ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags; 501261991Sdim MVT LocVT = ArgVT; 502261991Sdim CCValAssign::LocInfo LocInfo = CCValAssign::Full; 503261991Sdim 504261991Sdim // Promote i8 to i16 505261991Sdim if (LocVT == MVT::i8) { 506261991Sdim LocVT = MVT::i16; 507261991Sdim if (ArgFlags.isSExt()) 508261991Sdim LocInfo = CCValAssign::SExt; 509261991Sdim else if (ArgFlags.isZExt()) 510261991Sdim LocInfo = CCValAssign::ZExt; 511261991Sdim else 512261991Sdim LocInfo = CCValAssign::AExt; 513261991Sdim } 514261991Sdim 515261991Sdim // Handle byval arguments 516261991Sdim if (ArgFlags.isByVal()) { 517261991Sdim State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags); 518261991Sdim continue; 519261991Sdim } 520261991Sdim 521261991Sdim unsigned Parts = ArgsParts[i]; 522261991Sdim 523321369Sdim if (Builtin) { 524321369Sdim assert(Parts == 4 && 525321369Sdim "Builtin calling convention requires 64-bit arguments"); 526321369Sdim } 527321369Sdim 528321369Sdim if (!UsedStack && Parts == 2 && RegsLeft == 1) { 529321369Sdim // Special case for 32-bit register split, see EABI section 3.3.3 530321369Sdim unsigned Reg = State.AllocateReg(RegList); 531321369Sdim State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo)); 532321369Sdim RegsLeft -= 1; 533321369Sdim 534321369Sdim UsedStack = true; 535321369Sdim CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State); 536321369Sdim } else if (Parts <= RegsLeft) { 537261991Sdim for (unsigned j = 0; j < Parts; j++) { 538288943Sdim unsigned Reg = State.AllocateReg(RegList); 539261991Sdim State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo)); 540261991Sdim RegsLeft--; 541261991Sdim } 542261991Sdim } else { 543321369Sdim UsedStack = true; 544261991Sdim for (unsigned j = 0; j < Parts; j++) 545261991Sdim CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State); 546261991Sdim } 547261991Sdim } 548261991Sdim} 549261991Sdim 550261991Sdimstatic void AnalyzeRetResult(CCState &State, 551261991Sdim const SmallVectorImpl<ISD::InputArg> &Ins) { 552261991Sdim State.AnalyzeCallResult(Ins, RetCC_MSP430); 553261991Sdim} 554261991Sdim 555261991Sdimstatic void AnalyzeRetResult(CCState &State, 556261991Sdim const SmallVectorImpl<ISD::OutputArg> &Outs) { 557261991Sdim State.AnalyzeReturn(Outs, RetCC_MSP430); 558261991Sdim} 559261991Sdim 560261991Sdimtemplate<typename ArgT> 561261991Sdimstatic void AnalyzeReturnValues(CCState &State, 562261991Sdim SmallVectorImpl<CCValAssign> &RVLocs, 563261991Sdim const SmallVectorImpl<ArgT> &Args) { 564261991Sdim AnalyzeRetResult(State, Args); 565261991Sdim} 566261991Sdim 567309124SdimSDValue MSP430TargetLowering::LowerFormalArguments( 568309124Sdim SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 569309124Sdim const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 570309124Sdim SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 571198090Srdivacky 572198090Srdivacky switch (CallConv) { 573193323Sed default: 574327952Sdim report_fatal_error("Unsupported calling convention"); 575193323Sed case CallingConv::C: 576193323Sed case CallingConv::Fast: 577198090Srdivacky return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); 578200581Srdivacky case CallingConv::MSP430_INTR: 579234353Sdim if (Ins.empty()) 580234353Sdim return Chain; 581207618Srdivacky report_fatal_error("ISRs cannot have arguments"); 582193323Sed } 583193323Sed} 584193323Sed 585198090SrdivackySDValue 586239462SdimMSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 587207618Srdivacky SmallVectorImpl<SDValue> &InVals) const { 588239462Sdim SelectionDAG &DAG = CLI.DAG; 589261991Sdim SDLoc &dl = CLI.DL; 590261991Sdim SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 591261991Sdim SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 592261991Sdim SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 593239462Sdim SDValue Chain = CLI.Chain; 594239462Sdim SDValue Callee = CLI.Callee; 595239462Sdim bool &isTailCall = CLI.IsTailCall; 596239462Sdim CallingConv::ID CallConv = CLI.CallConv; 597239462Sdim bool isVarArg = CLI.IsVarArg; 598239462Sdim 599203954Srdivacky // MSP430 target does not yet support tail call optimization. 600203954Srdivacky isTailCall = false; 601198090Srdivacky 602198090Srdivacky switch (CallConv) { 603193323Sed default: 604327952Sdim report_fatal_error("Unsupported calling convention"); 605321369Sdim case CallingConv::MSP430_BUILTIN: 606193323Sed case CallingConv::Fast: 607193323Sed case CallingConv::C: 608198090Srdivacky return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 609210299Sed Outs, OutVals, Ins, dl, DAG, InVals); 610200581Srdivacky case CallingConv::MSP430_INTR: 611207618Srdivacky report_fatal_error("ISRs cannot be called directly"); 612193323Sed } 613193323Sed} 614193323Sed 615193323Sed/// LowerCCCArguments - transform physical registers into virtual registers and 616193323Sed/// generate load operations for arguments places on the stack. 617193323Sed// FIXME: struct return stuff 618309124SdimSDValue MSP430TargetLowering::LowerCCCArguments( 619309124Sdim SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 620309124Sdim const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 621309124Sdim SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 622193323Sed MachineFunction &MF = DAG.getMachineFunction(); 623314564Sdim MachineFrameInfo &MFI = MF.getFrameInfo(); 624193323Sed MachineRegisterInfo &RegInfo = MF.getRegInfo(); 625249423Sdim MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 626193323Sed 627193323Sed // Assign locations to all of the incoming arguments. 628193323Sed SmallVector<CCValAssign, 16> ArgLocs; 629280031Sdim CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 630280031Sdim *DAG.getContext()); 631261991Sdim AnalyzeArguments(CCInfo, ArgLocs, Ins); 632193323Sed 633249423Sdim // Create frame index for the start of the first vararg value 634249423Sdim if (isVarArg) { 635249423Sdim unsigned Offset = CCInfo.getNextStackOffset(); 636314564Sdim FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, Offset, true)); 637249423Sdim } 638193323Sed 639193323Sed for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 640193323Sed CCValAssign &VA = ArgLocs[i]; 641193323Sed if (VA.isRegLoc()) { 642193323Sed // Arguments passed in registers 643198090Srdivacky EVT RegVT = VA.getLocVT(); 644198090Srdivacky switch (RegVT.getSimpleVT().SimpleTy) { 645219077Sdim default: 646198090Srdivacky { 647198090Srdivacky#ifndef NDEBUG 648198090Srdivacky errs() << "LowerFormalArguments Unhandled argument type: " 649309124Sdim << RegVT.getEVTString() << "\n"; 650198090Srdivacky#endif 651276479Sdim llvm_unreachable(nullptr); 652198090Srdivacky } 653193323Sed case MVT::i16: 654360784Sdim Register VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); 655193323Sed RegInfo.addLiveIn(VA.getLocReg(), VReg); 656198090Srdivacky SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); 657193323Sed 658193323Sed // If this is an 8-bit value, it is really passed promoted to 16 659193323Sed // bits. Insert an assert[sz]ext to capture this, then truncate to the 660193323Sed // right size. 661193323Sed if (VA.getLocInfo() == CCValAssign::SExt) 662193323Sed ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 663193323Sed DAG.getValueType(VA.getValVT())); 664193323Sed else if (VA.getLocInfo() == CCValAssign::ZExt) 665193323Sed ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 666193323Sed DAG.getValueType(VA.getValVT())); 667193323Sed 668193323Sed if (VA.getLocInfo() != CCValAssign::Full) 669193323Sed ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 670193323Sed 671198090Srdivacky InVals.push_back(ArgValue); 672193323Sed } 673193323Sed } else { 674193323Sed // Sanity check 675193323Sed assert(VA.isMemLoc()); 676249423Sdim 677249423Sdim SDValue InVal; 678249423Sdim ISD::ArgFlagsTy Flags = Ins[i].Flags; 679249423Sdim 680249423Sdim if (Flags.isByVal()) { 681314564Sdim int FI = MFI.CreateFixedObject(Flags.getByValSize(), 682314564Sdim VA.getLocMemOffset(), true); 683288943Sdim InVal = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 684249423Sdim } else { 685249423Sdim // Load the argument to a virtual register 686249423Sdim unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 687249423Sdim if (ObjSize > 2) { 688249423Sdim errs() << "LowerFormalArguments Unhandled argument type: " 689249423Sdim << EVT(VA.getLocVT()).getEVTString() 690249423Sdim << "\n"; 691249423Sdim } 692249423Sdim // Create the frame index object for this incoming parameter... 693314564Sdim int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true); 694249423Sdim 695249423Sdim // Create the SelectionDAG nodes corresponding to a load 696249423Sdim //from this parameter 697249423Sdim SDValue FIN = DAG.getFrameIndex(FI, MVT::i16); 698296417Sdim InVal = DAG.getLoad( 699296417Sdim VA.getLocVT(), dl, Chain, FIN, 700309124Sdim MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 701193323Sed } 702193323Sed 703249423Sdim InVals.push_back(InVal); 704193323Sed } 705193323Sed } 706193323Sed 707321369Sdim for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 708321369Sdim if (Ins[i].Flags.isSRet()) { 709321369Sdim unsigned Reg = FuncInfo->getSRetReturnReg(); 710321369Sdim if (!Reg) { 711321369Sdim Reg = MF.getRegInfo().createVirtualRegister( 712321369Sdim getRegClassFor(MVT::i16)); 713321369Sdim FuncInfo->setSRetReturnReg(Reg); 714321369Sdim } 715321369Sdim SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]); 716321369Sdim Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 717321369Sdim } 718321369Sdim } 719321369Sdim 720198090Srdivacky return Chain; 721193323Sed} 722193323Sed 723321369Sdimbool 724321369SdimMSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 725321369Sdim MachineFunction &MF, 726321369Sdim bool IsVarArg, 727321369Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 728321369Sdim LLVMContext &Context) const { 729321369Sdim SmallVector<CCValAssign, 16> RVLocs; 730321369Sdim CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 731321369Sdim return CCInfo.CheckReturn(Outs, RetCC_MSP430); 732321369Sdim} 733321369Sdim 734198090SrdivackySDValue 735309124SdimMSP430TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 736309124Sdim bool isVarArg, 737198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 738210299Sed const SmallVectorImpl<SDValue> &OutVals, 739309124Sdim const SDLoc &dl, SelectionDAG &DAG) const { 740198090Srdivacky 741321369Sdim MachineFunction &MF = DAG.getMachineFunction(); 742321369Sdim 743193323Sed // CCValAssign - represent the assignment of the return value to a location 744193323Sed SmallVector<CCValAssign, 16> RVLocs; 745193323Sed 746200581Srdivacky // ISRs cannot return any value. 747234353Sdim if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) 748207618Srdivacky report_fatal_error("ISRs cannot return any value"); 749200581Srdivacky 750193323Sed // CCState - Info about the registers and stack slot. 751280031Sdim CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 752280031Sdim *DAG.getContext()); 753193323Sed 754198090Srdivacky // Analize return values. 755261991Sdim AnalyzeReturnValues(CCInfo, RVLocs, Outs); 756193323Sed 757193323Sed SDValue Flag; 758249423Sdim SmallVector<SDValue, 4> RetOps(1, Chain); 759193323Sed 760193323Sed // Copy the result values into the output registers. 761193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) { 762193323Sed CCValAssign &VA = RVLocs[i]; 763193323Sed assert(VA.isRegLoc() && "Can only return in registers!"); 764193323Sed 765193323Sed Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 766210299Sed OutVals[i], Flag); 767193323Sed 768193323Sed // Guarantee that all emitted copies are stuck together, 769193323Sed // avoiding something bad. 770193323Sed Flag = Chain.getValue(1); 771249423Sdim RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 772193323Sed } 773193323Sed 774327952Sdim if (MF.getFunction().hasStructRetAttr()) { 775321369Sdim MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 776321369Sdim unsigned Reg = FuncInfo->getSRetReturnReg(); 777321369Sdim 778321369Sdim if (!Reg) 779321369Sdim llvm_unreachable("sret virtual register not created in entry block"); 780321369Sdim 781321369Sdim SDValue Val = 782321369Sdim DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout())); 783321369Sdim unsigned R12 = MSP430::R12; 784321369Sdim 785321369Sdim Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag); 786321369Sdim Flag = Chain.getValue(1); 787321369Sdim RetOps.push_back(DAG.getRegister(R12, getPointerTy(DAG.getDataLayout()))); 788321369Sdim } 789321369Sdim 790200581Srdivacky unsigned Opc = (CallConv == CallingConv::MSP430_INTR ? 791200581Srdivacky MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG); 792200581Srdivacky 793249423Sdim RetOps[0] = Chain; // Update chain. 794249423Sdim 795249423Sdim // Add the flag if we have it. 796193323Sed if (Flag.getNode()) 797249423Sdim RetOps.push_back(Flag); 798193323Sed 799276479Sdim return DAG.getNode(Opc, dl, MVT::Other, RetOps); 800193323Sed} 801193323Sed 802193323Sed/// LowerCCCCallTo - functions arguments are copied from virtual regs to 803193323Sed/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 804309124SdimSDValue MSP430TargetLowering::LowerCCCCallTo( 805309124Sdim SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, 806309124Sdim bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, 807309124Sdim const SmallVectorImpl<SDValue> &OutVals, 808309124Sdim const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 809309124Sdim SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 810193323Sed // Analyze operands of the call, assigning locations to each operand. 811193323Sed SmallVector<CCValAssign, 16> ArgLocs; 812280031Sdim CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 813280031Sdim *DAG.getContext()); 814261991Sdim AnalyzeArguments(CCInfo, ArgLocs, Outs); 815193323Sed 816193323Sed // Get a count of how many bytes are to be pushed on the stack. 817193323Sed unsigned NumBytes = CCInfo.getNextStackOffset(); 818288943Sdim auto PtrVT = getPointerTy(DAG.getDataLayout()); 819193323Sed 820321369Sdim Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl); 821193323Sed 822193323Sed SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 823193323Sed SmallVector<SDValue, 12> MemOpChains; 824193323Sed SDValue StackPtr; 825193323Sed 826193323Sed // Walk the register/memloc assignments, inserting copies/loads. 827193323Sed for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 828193323Sed CCValAssign &VA = ArgLocs[i]; 829193323Sed 830210299Sed SDValue Arg = OutVals[i]; 831193323Sed 832193323Sed // Promote the value if needed. 833193323Sed switch (VA.getLocInfo()) { 834198090Srdivacky default: llvm_unreachable("Unknown loc info!"); 835193323Sed case CCValAssign::Full: break; 836193323Sed case CCValAssign::SExt: 837193323Sed Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 838193323Sed break; 839193323Sed case CCValAssign::ZExt: 840193323Sed Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 841193323Sed break; 842193323Sed case CCValAssign::AExt: 843193323Sed Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 844193323Sed break; 845193323Sed } 846193323Sed 847193323Sed // Arguments that can be passed on register must be kept at RegsToPass 848193323Sed // vector 849193323Sed if (VA.isRegLoc()) { 850193323Sed RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 851193323Sed } else { 852193323Sed assert(VA.isMemLoc()); 853193323Sed 854276479Sdim if (!StackPtr.getNode()) 855288943Sdim StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT); 856193323Sed 857288943Sdim SDValue PtrOff = 858288943Sdim DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 859288943Sdim DAG.getIntPtrConstant(VA.getLocMemOffset(), dl)); 860193323Sed 861249423Sdim SDValue MemOp; 862249423Sdim ISD::ArgFlagsTy Flags = Outs[i].Flags; 863193323Sed 864249423Sdim if (Flags.isByVal()) { 865288943Sdim SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16); 866249423Sdim MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode, 867249423Sdim Flags.getByValAlign(), 868249423Sdim /*isVolatile*/false, 869249423Sdim /*AlwaysInline=*/true, 870288943Sdim /*isTailCall=*/false, 871249423Sdim MachinePointerInfo(), 872249423Sdim MachinePointerInfo()); 873249423Sdim } else { 874309124Sdim MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()); 875249423Sdim } 876249423Sdim 877249423Sdim MemOpChains.push_back(MemOp); 878193323Sed } 879193323Sed } 880193323Sed 881193323Sed // Transform all store nodes into one single node because all store nodes are 882193323Sed // independent of each other. 883193323Sed if (!MemOpChains.empty()) 884276479Sdim Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); 885193323Sed 886193323Sed // Build a sequence of copy-to-reg nodes chained together with token chain and 887193323Sed // flag operands which copy the outgoing args into registers. The InFlag in 888221345Sdim // necessary since all emitted instructions must be stuck together. 889193323Sed SDValue InFlag; 890193323Sed for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 891193323Sed Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 892193323Sed RegsToPass[i].second, InFlag); 893193323Sed InFlag = Chain.getValue(1); 894193323Sed } 895193323Sed 896193323Sed // If the callee is a GlobalAddress node (quite common, every direct call is) 897193323Sed // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 898193323Sed // Likewise ExternalSymbol -> TargetExternalSymbol. 899193323Sed if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 900210299Sed Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16); 901193323Sed else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 902193323Sed Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16); 903193323Sed 904193323Sed // Returns a chain & a flag for retval copy to use. 905218893Sdim SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 906193323Sed SmallVector<SDValue, 8> Ops; 907193323Sed Ops.push_back(Chain); 908193323Sed Ops.push_back(Callee); 909193323Sed 910193323Sed // Add argument registers to the end of the list so that they are 911193323Sed // known live into the call. 912193323Sed for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 913193323Sed Ops.push_back(DAG.getRegister(RegsToPass[i].first, 914193323Sed RegsToPass[i].second.getValueType())); 915193323Sed 916193323Sed if (InFlag.getNode()) 917193323Sed Ops.push_back(InFlag); 918193323Sed 919276479Sdim Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops); 920193323Sed InFlag = Chain.getValue(1); 921193323Sed 922193323Sed // Create the CALLSEQ_END node. 923288943Sdim Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true), 924288943Sdim DAG.getConstant(0, dl, PtrVT, true), InFlag, dl); 925193323Sed InFlag = Chain.getValue(1); 926193323Sed 927193323Sed // Handle result values, copying them out of physregs into vregs that we 928193323Sed // return. 929198090Srdivacky return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, 930198090Srdivacky DAG, InVals); 931193323Sed} 932193323Sed 933198090Srdivacky/// LowerCallResult - Lower the result values of a call into the 934198090Srdivacky/// appropriate copies out of appropriate physical registers. 935198090Srdivacky/// 936309124SdimSDValue MSP430TargetLowering::LowerCallResult( 937309124Sdim SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, 938309124Sdim const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 939309124Sdim SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 940193323Sed 941193323Sed // Assign locations to each value returned by this call. 942193323Sed SmallVector<CCValAssign, 16> RVLocs; 943280031Sdim CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 944280031Sdim *DAG.getContext()); 945193323Sed 946261991Sdim AnalyzeReturnValues(CCInfo, RVLocs, Ins); 947193323Sed 948193323Sed // Copy all of the result registers out of their specified physreg. 949193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) { 950193323Sed Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 951193323Sed RVLocs[i].getValVT(), InFlag).getValue(1); 952193323Sed InFlag = Chain.getValue(2); 953198090Srdivacky InVals.push_back(Chain.getValue(0)); 954193323Sed } 955193323Sed 956198090Srdivacky return Chain; 957193323Sed} 958193323Sed 959193323SedSDValue MSP430TargetLowering::LowerShifts(SDValue Op, 960207618Srdivacky SelectionDAG &DAG) const { 961193323Sed unsigned Opc = Op.getOpcode(); 962193323Sed SDNode* N = Op.getNode(); 963198090Srdivacky EVT VT = Op.getValueType(); 964261991Sdim SDLoc dl(N); 965193323Sed 966200581Srdivacky // Expand non-constant shifts to loops: 967193323Sed if (!isa<ConstantSDNode>(N->getOperand(1))) 968344779Sdim return Op; 969193323Sed 970193323Sed uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 971193323Sed 972193323Sed // Expand the stuff into sequence of shifts. 973193323Sed SDValue Victim = N->getOperand(0); 974193323Sed 975344779Sdim if (ShiftAmount >= 8) { 976344779Sdim assert(VT == MVT::i16 && "Can not shift i8 by 8 and more"); 977344779Sdim switch(Opc) { 978344779Sdim default: 979344779Sdim llvm_unreachable("Unknown shift"); 980344779Sdim case ISD::SHL: 981344779Sdim // foo << (8 + N) => swpb(zext(foo)) << N 982344779Sdim Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8); 983344779Sdim Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim); 984344779Sdim break; 985344779Sdim case ISD::SRA: 986344779Sdim case ISD::SRL: 987344779Sdim // foo >> (8 + N) => sxt(swpb(foo)) >> N 988344779Sdim Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim); 989344779Sdim Victim = (Opc == ISD::SRA) 990344779Sdim ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim, 991344779Sdim DAG.getValueType(MVT::i8)) 992344779Sdim : DAG.getZeroExtendInReg(Victim, dl, MVT::i8); 993344779Sdim break; 994344779Sdim } 995344779Sdim ShiftAmount -= 8; 996344779Sdim } 997344779Sdim 998193323Sed if (Opc == ISD::SRL && ShiftAmount) { 999193323Sed // Emit a special goodness here: 1000193323Sed // srl A, 1 => clrc; rrc A 1001344779Sdim Victim = DAG.getNode(MSP430ISD::RRCL, dl, VT, Victim); 1002193323Sed ShiftAmount -= 1; 1003193323Sed } 1004193323Sed 1005193323Sed while (ShiftAmount--) 1006193323Sed Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), 1007193323Sed dl, VT, Victim); 1008193323Sed 1009193323Sed return Victim; 1010193323Sed} 1011193323Sed 1012207618SrdivackySDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, 1013207618Srdivacky SelectionDAG &DAG) const { 1014193323Sed const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1015193323Sed int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 1016288943Sdim auto PtrVT = getPointerTy(DAG.getDataLayout()); 1017193323Sed 1018193323Sed // Create the TargetGlobalAddress node, folding in the constant offset. 1019288943Sdim SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset); 1020288943Sdim return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result); 1021193323Sed} 1022193323Sed 1023193323SedSDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op, 1024207618Srdivacky SelectionDAG &DAG) const { 1025261991Sdim SDLoc dl(Op); 1026193323Sed const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 1027288943Sdim auto PtrVT = getPointerTy(DAG.getDataLayout()); 1028288943Sdim SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT); 1029193323Sed 1030288943Sdim return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result); 1031193323Sed} 1032193323Sed 1033207618SrdivackySDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op, 1034207618Srdivacky SelectionDAG &DAG) const { 1035261991Sdim SDLoc dl(Op); 1036288943Sdim auto PtrVT = getPointerTy(DAG.getDataLayout()); 1037207618Srdivacky const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1038288943Sdim SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT); 1039207618Srdivacky 1040288943Sdim return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result); 1041207618Srdivacky} 1042207618Srdivacky 1043198396Srdivackystatic SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, 1044309124Sdim ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) { 1045193323Sed // FIXME: Handle bittests someday 1046193323Sed assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet"); 1047193323Sed 1048193323Sed // FIXME: Handle jump negative someday 1049198396Srdivacky MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID; 1050193323Sed switch (CC) { 1051198090Srdivacky default: llvm_unreachable("Invalid integer condition!"); 1052193323Sed case ISD::SETEQ: 1053198396Srdivacky TCC = MSP430CC::COND_E; // aka COND_Z 1054202375Srdivacky // Minor optimization: if LHS is a constant, swap operands, then the 1055199989Srdivacky // constant can be folded into comparison. 1056202375Srdivacky if (LHS.getOpcode() == ISD::Constant) 1057199989Srdivacky std::swap(LHS, RHS); 1058193323Sed break; 1059193323Sed case ISD::SETNE: 1060198396Srdivacky TCC = MSP430CC::COND_NE; // aka COND_NZ 1061202375Srdivacky // Minor optimization: if LHS is a constant, swap operands, then the 1062199989Srdivacky // constant can be folded into comparison. 1063202375Srdivacky if (LHS.getOpcode() == ISD::Constant) 1064199989Srdivacky std::swap(LHS, RHS); 1065193323Sed break; 1066193323Sed case ISD::SETULE: 1067314564Sdim std::swap(LHS, RHS); 1068314564Sdim LLVM_FALLTHROUGH; 1069193323Sed case ISD::SETUGE: 1070202878Srdivacky // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to 1071202878Srdivacky // fold constant into instruction. 1072202878Srdivacky if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 1073202878Srdivacky LHS = RHS; 1074288943Sdim RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); 1075202878Srdivacky TCC = MSP430CC::COND_LO; 1076202878Srdivacky break; 1077202878Srdivacky } 1078198396Srdivacky TCC = MSP430CC::COND_HS; // aka COND_C 1079193323Sed break; 1080193323Sed case ISD::SETUGT: 1081314564Sdim std::swap(LHS, RHS); 1082314564Sdim LLVM_FALLTHROUGH; 1083193323Sed case ISD::SETULT: 1084202878Srdivacky // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to 1085202878Srdivacky // fold constant into instruction. 1086202878Srdivacky if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 1087202878Srdivacky LHS = RHS; 1088288943Sdim RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); 1089202878Srdivacky TCC = MSP430CC::COND_HS; 1090202878Srdivacky break; 1091202878Srdivacky } 1092198396Srdivacky TCC = MSP430CC::COND_LO; // aka COND_NC 1093193323Sed break; 1094193323Sed case ISD::SETLE: 1095314564Sdim std::swap(LHS, RHS); 1096314564Sdim LLVM_FALLTHROUGH; 1097193323Sed case ISD::SETGE: 1098202878Srdivacky // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to 1099202878Srdivacky // fold constant into instruction. 1100202878Srdivacky if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 1101202878Srdivacky LHS = RHS; 1102288943Sdim RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); 1103202878Srdivacky TCC = MSP430CC::COND_L; 1104202878Srdivacky break; 1105202878Srdivacky } 1106198396Srdivacky TCC = MSP430CC::COND_GE; 1107193323Sed break; 1108193323Sed case ISD::SETGT: 1109314564Sdim std::swap(LHS, RHS); 1110314564Sdim LLVM_FALLTHROUGH; 1111193323Sed case ISD::SETLT: 1112202878Srdivacky // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to 1113202878Srdivacky // fold constant into instruction. 1114202878Srdivacky if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 1115202878Srdivacky LHS = RHS; 1116288943Sdim RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); 1117202878Srdivacky TCC = MSP430CC::COND_GE; 1118202878Srdivacky break; 1119202878Srdivacky } 1120198396Srdivacky TCC = MSP430CC::COND_L; 1121193323Sed break; 1122193323Sed } 1123193323Sed 1124288943Sdim TargetCC = DAG.getConstant(TCC, dl, MVT::i8); 1125218893Sdim return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS); 1126193323Sed} 1127193323Sed 1128193323Sed 1129207618SrdivackySDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 1130193323Sed SDValue Chain = Op.getOperand(0); 1131193323Sed ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1132193323Sed SDValue LHS = Op.getOperand(2); 1133193323Sed SDValue RHS = Op.getOperand(3); 1134193323Sed SDValue Dest = Op.getOperand(4); 1135261991Sdim SDLoc dl (Op); 1136193323Sed 1137198396Srdivacky SDValue TargetCC; 1138193323Sed SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 1139193323Sed 1140193323Sed return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(), 1141198396Srdivacky Chain, Dest, TargetCC, Flag); 1142193323Sed} 1143193323Sed 1144207618SrdivackySDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1145200581Srdivacky SDValue LHS = Op.getOperand(0); 1146200581Srdivacky SDValue RHS = Op.getOperand(1); 1147261991Sdim SDLoc dl (Op); 1148200581Srdivacky 1149200581Srdivacky // If we are doing an AND and testing against zero, then the CMP 1150200581Srdivacky // will not be generated. The AND (or BIT) will generate the condition codes, 1151200581Srdivacky // but they are different from CMP. 1152202878Srdivacky // FIXME: since we're doing a post-processing, use a pseudoinstr here, so 1153202878Srdivacky // lowering & isel wouldn't diverge. 1154200581Srdivacky bool andCC = false; 1155200581Srdivacky if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 1156200581Srdivacky if (RHSC->isNullValue() && LHS.hasOneUse() && 1157200581Srdivacky (LHS.getOpcode() == ISD::AND || 1158200581Srdivacky (LHS.getOpcode() == ISD::TRUNCATE && 1159200581Srdivacky LHS.getOperand(0).getOpcode() == ISD::AND))) { 1160200581Srdivacky andCC = true; 1161200581Srdivacky } 1162200581Srdivacky } 1163200581Srdivacky ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1164200581Srdivacky SDValue TargetCC; 1165200581Srdivacky SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 1166200581Srdivacky 1167200581Srdivacky // Get the condition codes directly from the status register, if its easy. 1168200581Srdivacky // Otherwise a branch will be generated. Note that the AND and BIT 1169200581Srdivacky // instructions generate different flags than CMP, the carry bit can be used 1170200581Srdivacky // for NE/EQ. 1171200581Srdivacky bool Invert = false; 1172200581Srdivacky bool Shift = false; 1173200581Srdivacky bool Convert = true; 1174200581Srdivacky switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) { 1175200581Srdivacky default: 1176200581Srdivacky Convert = false; 1177200581Srdivacky break; 1178200581Srdivacky case MSP430CC::COND_HS: 1179280031Sdim // Res = SR & 1, no processing is required 1180200581Srdivacky break; 1181202878Srdivacky case MSP430CC::COND_LO: 1182280031Sdim // Res = ~(SR & 1) 1183200581Srdivacky Invert = true; 1184200581Srdivacky break; 1185202878Srdivacky case MSP430CC::COND_NE: 1186200581Srdivacky if (andCC) { 1187280031Sdim // C = ~Z, thus Res = SR & 1, no processing is required 1188200581Srdivacky } else { 1189280031Sdim // Res = ~((SR >> 1) & 1) 1190200581Srdivacky Shift = true; 1191204642Srdivacky Invert = true; 1192200581Srdivacky } 1193200581Srdivacky break; 1194202878Srdivacky case MSP430CC::COND_E: 1195204642Srdivacky Shift = true; 1196280031Sdim // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however, 1197280031Sdim // Res = (SR >> 1) & 1 is 1 word shorter. 1198200581Srdivacky break; 1199200581Srdivacky } 1200200581Srdivacky EVT VT = Op.getValueType(); 1201288943Sdim SDValue One = DAG.getConstant(1, dl, VT); 1202200581Srdivacky if (Convert) { 1203280031Sdim SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR, 1204202878Srdivacky MVT::i16, Flag); 1205200581Srdivacky if (Shift) 1206200581Srdivacky // FIXME: somewhere this is turned into a SRL, lower it MSP specific? 1207200581Srdivacky SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); 1208200581Srdivacky SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One); 1209200581Srdivacky if (Invert) 1210200581Srdivacky SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One); 1211200581Srdivacky return SR; 1212200581Srdivacky } else { 1213288943Sdim SDValue Zero = DAG.getConstant(0, dl, VT); 1214218893Sdim SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 1215288943Sdim SDValue Ops[] = {One, Zero, TargetCC, Flag}; 1216276479Sdim return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); 1217200581Srdivacky } 1218200581Srdivacky} 1219200581Srdivacky 1220207618SrdivackySDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, 1221207618Srdivacky SelectionDAG &DAG) const { 1222193323Sed SDValue LHS = Op.getOperand(0); 1223193323Sed SDValue RHS = Op.getOperand(1); 1224193323Sed SDValue TrueV = Op.getOperand(2); 1225193323Sed SDValue FalseV = Op.getOperand(3); 1226193323Sed ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1227261991Sdim SDLoc dl (Op); 1228193323Sed 1229198396Srdivacky SDValue TargetCC; 1230193323Sed SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 1231193323Sed 1232218893Sdim SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 1233288943Sdim SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag}; 1234193323Sed 1235276479Sdim return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); 1236193323Sed} 1237193323Sed 1238193323SedSDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op, 1239207618Srdivacky SelectionDAG &DAG) const { 1240193323Sed SDValue Val = Op.getOperand(0); 1241198090Srdivacky EVT VT = Op.getValueType(); 1242261991Sdim SDLoc dl(Op); 1243193323Sed 1244193323Sed assert(VT == MVT::i16 && "Only support i16 for now!"); 1245193323Sed 1246193323Sed return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, 1247193323Sed DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), 1248193323Sed DAG.getValueType(Val.getValueType())); 1249193323Sed} 1250193323Sed 1251207618SrdivackySDValue 1252207618SrdivackyMSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 1253200581Srdivacky MachineFunction &MF = DAG.getMachineFunction(); 1254200581Srdivacky MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 1255200581Srdivacky int ReturnAddrIndex = FuncInfo->getRAIndex(); 1256288943Sdim auto PtrVT = getPointerTy(MF.getDataLayout()); 1257200581Srdivacky 1258200581Srdivacky if (ReturnAddrIndex == 0) { 1259200581Srdivacky // Set up a frame object for the return address. 1260288943Sdim uint64_t SlotSize = MF.getDataLayout().getPointerSize(); 1261314564Sdim ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize, -SlotSize, 1262210299Sed true); 1263200581Srdivacky FuncInfo->setRAIndex(ReturnAddrIndex); 1264200581Srdivacky } 1265200581Srdivacky 1266288943Sdim return DAG.getFrameIndex(ReturnAddrIndex, PtrVT); 1267200581Srdivacky} 1268200581Srdivacky 1269207618SrdivackySDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op, 1270207618Srdivacky SelectionDAG &DAG) const { 1271314564Sdim MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 1272314564Sdim MFI.setReturnAddressIsTaken(true); 1273208599Srdivacky 1274276479Sdim if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 1275276479Sdim return SDValue(); 1276276479Sdim 1277200581Srdivacky unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1278261991Sdim SDLoc dl(Op); 1279288943Sdim auto PtrVT = getPointerTy(DAG.getDataLayout()); 1280200581Srdivacky 1281200581Srdivacky if (Depth > 0) { 1282200581Srdivacky SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 1283200581Srdivacky SDValue Offset = 1284288943Sdim DAG.getConstant(DAG.getDataLayout().getPointerSize(), dl, MVT::i16); 1285288943Sdim return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 1286288943Sdim DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset), 1287309124Sdim MachinePointerInfo()); 1288200581Srdivacky } 1289200581Srdivacky 1290200581Srdivacky // Just load the return address. 1291200581Srdivacky SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 1292288943Sdim return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI, 1293309124Sdim MachinePointerInfo()); 1294200581Srdivacky} 1295200581Srdivacky 1296207618SrdivackySDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, 1297207618Srdivacky SelectionDAG &DAG) const { 1298314564Sdim MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 1299314564Sdim MFI.setFrameAddressIsTaken(true); 1300208599Srdivacky 1301200581Srdivacky EVT VT = Op.getValueType(); 1302261991Sdim SDLoc dl(Op); // FIXME probably not meaningful 1303200581Srdivacky unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1304200581Srdivacky SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 1305280031Sdim MSP430::FP, VT); 1306200581Srdivacky while (Depth--) 1307218893Sdim FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 1308309124Sdim MachinePointerInfo()); 1309200581Srdivacky return FrameAddr; 1310200581Srdivacky} 1311200581Srdivacky 1312249423SdimSDValue MSP430TargetLowering::LowerVASTART(SDValue Op, 1313249423Sdim SelectionDAG &DAG) const { 1314249423Sdim MachineFunction &MF = DAG.getMachineFunction(); 1315249423Sdim MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 1316288943Sdim auto PtrVT = getPointerTy(DAG.getDataLayout()); 1317249423Sdim 1318249423Sdim // Frame index of first vararg argument 1319288943Sdim SDValue FrameIndex = 1320288943Sdim DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1321249423Sdim const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1322249423Sdim 1323249423Sdim // Create a store of the frame index to the location operand 1324309124Sdim return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Op.getOperand(1), 1325309124Sdim MachinePointerInfo(SV)); 1326249423Sdim} 1327249423Sdim 1328261991SdimSDValue MSP430TargetLowering::LowerJumpTable(SDValue Op, 1329261991Sdim SelectionDAG &DAG) const { 1330261991Sdim JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1331288943Sdim auto PtrVT = getPointerTy(DAG.getDataLayout()); 1332288943Sdim SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1333288943Sdim return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result); 1334261991Sdim} 1335261991Sdim 1336199481Srdivacky/// getPostIndexedAddressParts - returns true by value, base pointer and 1337199481Srdivacky/// offset pointer and addressing mode by reference if this node can be 1338199481Srdivacky/// combined with a load / store to form a post-indexed load / store. 1339199481Srdivackybool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 1340199481Srdivacky SDValue &Base, 1341199481Srdivacky SDValue &Offset, 1342199481Srdivacky ISD::MemIndexedMode &AM, 1343199481Srdivacky SelectionDAG &DAG) const { 1344199481Srdivacky 1345199481Srdivacky LoadSDNode *LD = cast<LoadSDNode>(N); 1346199481Srdivacky if (LD->getExtensionType() != ISD::NON_EXTLOAD) 1347199481Srdivacky return false; 1348199481Srdivacky 1349199481Srdivacky EVT VT = LD->getMemoryVT(); 1350199481Srdivacky if (VT != MVT::i8 && VT != MVT::i16) 1351199481Srdivacky return false; 1352199481Srdivacky 1353199481Srdivacky if (Op->getOpcode() != ISD::ADD) 1354199481Srdivacky return false; 1355199481Srdivacky 1356199481Srdivacky if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 1357199481Srdivacky uint64_t RHSC = RHS->getZExtValue(); 1358199481Srdivacky if ((VT == MVT::i16 && RHSC != 2) || 1359199481Srdivacky (VT == MVT::i8 && RHSC != 1)) 1360199481Srdivacky return false; 1361199481Srdivacky 1362199481Srdivacky Base = Op->getOperand(0); 1363288943Sdim Offset = DAG.getConstant(RHSC, SDLoc(N), VT); 1364199481Srdivacky AM = ISD::POST_INC; 1365199481Srdivacky return true; 1366199481Srdivacky } 1367199481Srdivacky 1368199481Srdivacky return false; 1369199481Srdivacky} 1370199481Srdivacky 1371199481Srdivacky 1372193323Sedconst char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const { 1373288943Sdim switch ((MSP430ISD::NodeType)Opcode) { 1374288943Sdim case MSP430ISD::FIRST_NUMBER: break; 1375193323Sed case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG"; 1376200581Srdivacky case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG"; 1377193323Sed case MSP430ISD::RRA: return "MSP430ISD::RRA"; 1378193323Sed case MSP430ISD::RLA: return "MSP430ISD::RLA"; 1379193323Sed case MSP430ISD::RRC: return "MSP430ISD::RRC"; 1380344779Sdim case MSP430ISD::RRCL: return "MSP430ISD::RRCL"; 1381193323Sed case MSP430ISD::CALL: return "MSP430ISD::CALL"; 1382193323Sed case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper"; 1383193323Sed case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC"; 1384193323Sed case MSP430ISD::CMP: return "MSP430ISD::CMP"; 1385288943Sdim case MSP430ISD::SETCC: return "MSP430ISD::SETCC"; 1386193323Sed case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; 1387344779Sdim case MSP430ISD::DADD: return "MSP430ISD::DADD"; 1388193323Sed } 1389288943Sdim return nullptr; 1390193323Sed} 1391193323Sed 1392226633Sdimbool MSP430TargetLowering::isTruncateFree(Type *Ty1, 1393226633Sdim Type *Ty2) const { 1394203954Srdivacky if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 1395202878Srdivacky return false; 1396202878Srdivacky 1397202878Srdivacky return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits()); 1398202878Srdivacky} 1399202878Srdivacky 1400202878Srdivackybool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 1401202878Srdivacky if (!VT1.isInteger() || !VT2.isInteger()) 1402202878Srdivacky return false; 1403202878Srdivacky 1404202878Srdivacky return (VT1.getSizeInBits() > VT2.getSizeInBits()); 1405202878Srdivacky} 1406202878Srdivacky 1407226633Sdimbool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 1408202878Srdivacky // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. 1409203954Srdivacky return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16); 1410202878Srdivacky} 1411202878Srdivacky 1412202878Srdivackybool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 1413202878Srdivacky // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. 1414202878Srdivacky return 0 && VT1 == MVT::i8 && VT2 == MVT::i16; 1415202878Srdivacky} 1416202878Srdivacky 1417249423Sdimbool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 1418249423Sdim return isZExtFree(Val.getValueType(), VT2); 1419249423Sdim} 1420249423Sdim 1421193323Sed//===----------------------------------------------------------------------===// 1422193323Sed// Other Lowering Code 1423193323Sed//===----------------------------------------------------------------------===// 1424193323Sed 1425309124SdimMachineBasicBlock * 1426309124SdimMSP430TargetLowering::EmitShiftInstr(MachineInstr &MI, 1427207618Srdivacky MachineBasicBlock *BB) const { 1428200581Srdivacky MachineFunction *F = BB->getParent(); 1429200581Srdivacky MachineRegisterInfo &RI = F->getRegInfo(); 1430309124Sdim DebugLoc dl = MI.getDebugLoc(); 1431288943Sdim const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo(); 1432200581Srdivacky 1433200581Srdivacky unsigned Opc; 1434344779Sdim bool ClearCarry = false; 1435200581Srdivacky const TargetRegisterClass * RC; 1436309124Sdim switch (MI.getOpcode()) { 1437234353Sdim default: llvm_unreachable("Invalid shift opcode!"); 1438200581Srdivacky case MSP430::Shl8: 1439344779Sdim Opc = MSP430::ADD8rr; 1440344779Sdim RC = &MSP430::GR8RegClass; 1441344779Sdim break; 1442200581Srdivacky case MSP430::Shl16: 1443344779Sdim Opc = MSP430::ADD16rr; 1444344779Sdim RC = &MSP430::GR16RegClass; 1445344779Sdim break; 1446200581Srdivacky case MSP430::Sra8: 1447344779Sdim Opc = MSP430::RRA8r; 1448344779Sdim RC = &MSP430::GR8RegClass; 1449344779Sdim break; 1450200581Srdivacky case MSP430::Sra16: 1451344779Sdim Opc = MSP430::RRA16r; 1452344779Sdim RC = &MSP430::GR16RegClass; 1453344779Sdim break; 1454200581Srdivacky case MSP430::Srl8: 1455344779Sdim ClearCarry = true; 1456344779Sdim Opc = MSP430::RRC8r; 1457344779Sdim RC = &MSP430::GR8RegClass; 1458344779Sdim break; 1459200581Srdivacky case MSP430::Srl16: 1460344779Sdim ClearCarry = true; 1461344779Sdim Opc = MSP430::RRC16r; 1462344779Sdim RC = &MSP430::GR16RegClass; 1463344779Sdim break; 1464344779Sdim case MSP430::Rrcl8: 1465344779Sdim case MSP430::Rrcl16: { 1466344779Sdim BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR) 1467344779Sdim .addReg(MSP430::SR).addImm(1); 1468360784Sdim Register SrcReg = MI.getOperand(1).getReg(); 1469360784Sdim Register DstReg = MI.getOperand(0).getReg(); 1470344779Sdim unsigned RrcOpc = MI.getOpcode() == MSP430::Rrcl16 1471344779Sdim ? MSP430::RRC16r : MSP430::RRC8r; 1472344779Sdim BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg) 1473344779Sdim .addReg(SrcReg); 1474344779Sdim MI.eraseFromParent(); // The pseudo instruction is gone now. 1475344779Sdim return BB; 1476200581Srdivacky } 1477344779Sdim } 1478200581Srdivacky 1479200581Srdivacky const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1480296417Sdim MachineFunction::iterator I = ++BB->getIterator(); 1481200581Srdivacky 1482200581Srdivacky // Create loop block 1483200581Srdivacky MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); 1484200581Srdivacky MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); 1485200581Srdivacky 1486200581Srdivacky F->insert(I, LoopBB); 1487200581Srdivacky F->insert(I, RemBB); 1488200581Srdivacky 1489200581Srdivacky // Update machine-CFG edges by transferring all successors of the current 1490200581Srdivacky // block to the block containing instructions after shift. 1491276479Sdim RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), 1492210299Sed BB->end()); 1493210299Sed RemBB->transferSuccessorsAndUpdatePHIs(BB); 1494200581Srdivacky 1495321369Sdim // Add edges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB 1496200581Srdivacky BB->addSuccessor(LoopBB); 1497200581Srdivacky BB->addSuccessor(RemBB); 1498200581Srdivacky LoopBB->addSuccessor(RemBB); 1499200581Srdivacky LoopBB->addSuccessor(LoopBB); 1500200581Srdivacky 1501360784Sdim Register ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass); 1502360784Sdim Register ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass); 1503360784Sdim Register ShiftReg = RI.createVirtualRegister(RC); 1504360784Sdim Register ShiftReg2 = RI.createVirtualRegister(RC); 1505360784Sdim Register ShiftAmtSrcReg = MI.getOperand(2).getReg(); 1506360784Sdim Register SrcReg = MI.getOperand(1).getReg(); 1507360784Sdim Register DstReg = MI.getOperand(0).getReg(); 1508200581Srdivacky 1509200581Srdivacky // BB: 1510200581Srdivacky // cmp 0, N 1511200581Srdivacky // je RemBB 1512202375Srdivacky BuildMI(BB, dl, TII.get(MSP430::CMP8ri)) 1513202375Srdivacky .addReg(ShiftAmtSrcReg).addImm(0); 1514200581Srdivacky BuildMI(BB, dl, TII.get(MSP430::JCC)) 1515200581Srdivacky .addMBB(RemBB) 1516200581Srdivacky .addImm(MSP430CC::COND_E); 1517200581Srdivacky 1518200581Srdivacky // LoopBB: 1519200581Srdivacky // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB] 1520200581Srdivacky // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB] 1521200581Srdivacky // ShiftReg2 = shift ShiftReg 1522200581Srdivacky // ShiftAmt2 = ShiftAmt - 1; 1523200581Srdivacky BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) 1524200581Srdivacky .addReg(SrcReg).addMBB(BB) 1525200581Srdivacky .addReg(ShiftReg2).addMBB(LoopBB); 1526200581Srdivacky BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg) 1527200581Srdivacky .addReg(ShiftAmtSrcReg).addMBB(BB) 1528200581Srdivacky .addReg(ShiftAmtReg2).addMBB(LoopBB); 1529344779Sdim if (ClearCarry) 1530344779Sdim BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR) 1531344779Sdim .addReg(MSP430::SR).addImm(1); 1532344779Sdim if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr) 1533344779Sdim BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2) 1534344779Sdim .addReg(ShiftReg) 1535344779Sdim .addReg(ShiftReg); 1536344779Sdim else 1537344779Sdim BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2) 1538344779Sdim .addReg(ShiftReg); 1539200581Srdivacky BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2) 1540200581Srdivacky .addReg(ShiftAmtReg).addImm(1); 1541200581Srdivacky BuildMI(LoopBB, dl, TII.get(MSP430::JCC)) 1542200581Srdivacky .addMBB(LoopBB) 1543200581Srdivacky .addImm(MSP430CC::COND_NE); 1544200581Srdivacky 1545200581Srdivacky // RemBB: 1546200581Srdivacky // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB] 1547210299Sed BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg) 1548200581Srdivacky .addReg(SrcReg).addMBB(BB) 1549200581Srdivacky .addReg(ShiftReg2).addMBB(LoopBB); 1550200581Srdivacky 1551309124Sdim MI.eraseFromParent(); // The pseudo instruction is gone now. 1552200581Srdivacky return RemBB; 1553200581Srdivacky} 1554200581Srdivacky 1555309124SdimMachineBasicBlock * 1556309124SdimMSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1557207618Srdivacky MachineBasicBlock *BB) const { 1558309124Sdim unsigned Opc = MI.getOpcode(); 1559200581Srdivacky 1560344779Sdim if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 || 1561344779Sdim Opc == MSP430::Sra8 || Opc == MSP430::Sra16 || 1562344779Sdim Opc == MSP430::Srl8 || Opc == MSP430::Srl16 || 1563344779Sdim Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16) 1564207618Srdivacky return EmitShiftInstr(MI, BB); 1565200581Srdivacky 1566288943Sdim const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); 1567309124Sdim DebugLoc dl = MI.getDebugLoc(); 1568200581Srdivacky 1569200581Srdivacky assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) && 1570193323Sed "Unexpected instr type to insert"); 1571193323Sed 1572193323Sed // To "insert" a SELECT instruction, we actually have to insert the diamond 1573193323Sed // control-flow pattern. The incoming instruction knows the destination vreg 1574193323Sed // to set, the condition code register to branch on, the true/false values to 1575193323Sed // select between, and a branch opcode to use. 1576193323Sed const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1577296417Sdim MachineFunction::iterator I = ++BB->getIterator(); 1578193323Sed 1579193323Sed // thisMBB: 1580193323Sed // ... 1581193323Sed // TrueVal = ... 1582193323Sed // cmpTY ccX, r1, r2 1583193323Sed // jCC copy1MBB 1584193323Sed // fallthrough --> copy0MBB 1585193323Sed MachineBasicBlock *thisMBB = BB; 1586193323Sed MachineFunction *F = BB->getParent(); 1587193323Sed MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1588193323Sed MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 1589193323Sed F->insert(I, copy0MBB); 1590193323Sed F->insert(I, copy1MBB); 1591193323Sed // Update machine-CFG edges by transferring all successors of the current 1592193323Sed // block to the new block which will contain the Phi node for the select. 1593210299Sed copy1MBB->splice(copy1MBB->begin(), BB, 1594276479Sdim std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1595210299Sed copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 1596193323Sed // Next, add the true and fallthrough blocks as its successors. 1597193323Sed BB->addSuccessor(copy0MBB); 1598193323Sed BB->addSuccessor(copy1MBB); 1599193323Sed 1600210299Sed BuildMI(BB, dl, TII.get(MSP430::JCC)) 1601309124Sdim .addMBB(copy1MBB) 1602309124Sdim .addImm(MI.getOperand(3).getImm()); 1603210299Sed 1604193323Sed // copy0MBB: 1605193323Sed // %FalseValue = ... 1606193323Sed // # fallthrough to copy1MBB 1607193323Sed BB = copy0MBB; 1608193323Sed 1609193323Sed // Update machine-CFG edges 1610193323Sed BB->addSuccessor(copy1MBB); 1611193323Sed 1612193323Sed // copy1MBB: 1613193323Sed // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1614193323Sed // ... 1615193323Sed BB = copy1MBB; 1616309124Sdim BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg()) 1617309124Sdim .addReg(MI.getOperand(2).getReg()) 1618309124Sdim .addMBB(copy0MBB) 1619309124Sdim .addReg(MI.getOperand(1).getReg()) 1620309124Sdim .addMBB(thisMBB); 1621193323Sed 1622309124Sdim MI.eraseFromParent(); // The pseudo instruction is gone now. 1623193323Sed return BB; 1624193323Sed} 1625