Searched refs:CSR_WRITE_2 (Results 1 - 25 of 68) sorted by relevance

123

/freebsd-11-stable/sys/dev/ep/
H A Dif_ep.c143 CSR_WRITE_2(sc, EP_W0_EEPROM_COMMAND,
407 CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
409 CSR_WRITE_2(sc, EP_W4_MEDIA_TYPE, DISABLE_UTP);
413 CSR_WRITE_2(sc, EP_W0_CONFIG_CTRL, 0);
416 CSR_WRITE_2(sc, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
422 CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
423 CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
432 CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | 0xff);
434 CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK | S_5_INTS);
435 CSR_WRITE_2(s
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H A Dif_ep_pccard.c166 CSR_WRITE_2(sc, EP_W0_ADDRESS_CFG, result & 0xc000);
175 CSR_WRITE_2(sc, EP_W0_PRODUCT_ID, sc->epb.prod_id);
182 CSR_WRITE_2(sc, EP_W3_OPTIONS, 0x8040);
184 CSR_WRITE_2(sc, EP_W3_OPTIONS, 0xc040);
185 CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
186 CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
189 CSR_WRITE_2(sc, EP_W3_OPTIONS, 0x8040);
/freebsd-11-stable/sys/dev/bm/
H A Dif_bm.c172 CSR_WRITE_2(sc, BM_MII_CSR, val);
228 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
242 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
918 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
925 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
931 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
958 CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]);
959 CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]);
960 CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]);
961 CSR_WRITE_2(s
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H A Dif_bmreg.h157 #define CSR_WRITE_2(sc, reg, val) \ macro
/freebsd-11-stable/sys/dev/sn/
H A Dif_sn.c280 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
282 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
286 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
294 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
300 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
306 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
329 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
446 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
496 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
502 CSR_WRITE_2(s
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H A Dif_snvar.h62 #define CSR_WRITE_2(sc, off, val) \ macro
/freebsd-11-stable/sys/dev/vx/
H A Dif_vx.c163 CSR_WRITE_2(sc, VX_COMMAND, GLOBAL_RESET);
180 CSR_WRITE_2(sc, VX_W0_EEPROM_COMMAND, EEPROM_CMD_RD
241 CSR_WRITE_2(sc, VX_COMMAND, RX_RESET);
243 CSR_WRITE_2(sc, VX_COMMAND, TX_RESET);
250 CSR_WRITE_2(sc, VX_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE |
252 CSR_WRITE_2(sc, VX_COMMAND, SET_INTR_MASK | S_CARD_FAILURE |
261 CSR_WRITE_2(sc, VX_COMMAND, ACK_INTR | 0xff);
266 CSR_WRITE_2(sc, VX_COMMAND, RX_ENABLE);
267 CSR_WRITE_2(sc, VX_COMMAND, TX_ENABLE);
287 CSR_WRITE_2(s
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H A Dif_vxvar.h62 #define CSR_WRITE_2(sc, reg, val) \ macro
/freebsd-11-stable/sys/dev/ex/
H A Dif_ex.c382 CSR_WRITE_2(sc, RCV_BAR, sc->rx_lower_limit);
384 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit | 0xfe);
385 CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);
501 CSR_WRITE_2(sc, HOST_ADDR_REG, dest);
502 CSR_WRITE_2(sc, IO_PORT_REG, Transmit_CMD);
503 CSR_WRITE_2(sc, IO_PORT_REG, 0);
504 CSR_WRITE_2(sc, IO_PORT_REG, next);
505 CSR_WRITE_2(sc, IO_PORT_REG, data_len);
536 CSR_WRITE_2(sc, HOST_ADDR_REG,
538 CSR_WRITE_2(s
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H A Dif_exvar.h99 #define CSR_WRITE_2(sc, off, val) \ macro
/freebsd-11-stable/sys/dev/xl/
H A Dif_xl.c407 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val);
572 CSR_WRITE_2(sc, XL_W0_EE_CMD,
575 CSR_WRITE_2(sc, XL_W0_EE_CMD,
644 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
685 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
707 CSR_WRITE_2(sc, XL_COMMAND,
716 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
737 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
822 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
824 CSR_WRITE_2(s
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/freebsd-11-stable/sys/dev/vte/
H A Dif_vte.c178 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
202 CSR_WRITE_2(sc, VTE_MMWD, val);
203 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
259 CSR_WRITE_2(sc, VTE_MRICR, val);
267 CSR_WRITE_2(sc, VTE_MTICR, val);
1159 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
1255 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1356 CSR_WRITE_2(sc, VTE_MIER, 0);
1377 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1576 CSR_WRITE_2(s
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H A Dif_vtevar.h149 #define CSR_WRITE_2(_sc, reg, val) \ macro
/freebsd-11-stable/sys/dev/wi/
H A Dif_wi_pci.c155 CSR_WRITE_2(sc, WI_INT_EN, 0);
156 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
203 CSR_WRITE_2(sc, WI_PCICOR_OFF, WI_PCICOR_RESET);
206 CSR_WRITE_2(sc, WI_PCICOR_OFF, 0x0000);
221 CSR_WRITE_2(sc, WI_HFA384X_SWSUPPORT0_OFF, WI_PRISM2STA_MAGIC);
H A Dif_wi_macio.c137 CSR_WRITE_2(sc, WI_INT_EN, 0);
138 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
H A Dif_wi.c567 CSR_WRITE_2(sc, WI_INT_EN, 0);
568 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
574 CSR_WRITE_2(sc, WI_INT_EN, 0);
589 CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS);
600 CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS);
675 CSR_WRITE_2(sc, WI_INT_EN, 0);
1120 CSR_WRITE_2(sc, WI_INT_EN, 0);
1121 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
1271 CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX);
1282 CSR_WRITE_2(s
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/freebsd-11-stable/sys/dev/bwi/
H A Dbwimac.c217 CSR_WRITE_2(sc, data_reg, v);
230 CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16);
234 CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff);
278 CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
349 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
366 CSR_WRITE_2(sc, 0x60e, 0);
367 CSR_WRITE_2(sc, 0x610, 0x8000);
368 CSR_WRITE_2(sc, 0x604, 0);
369 CSR_WRITE_2(sc, 0x606, 0x200);
393 CSR_WRITE_2(s
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H A Dbwirf.c201 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
202 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
220 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
251 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
255 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
354 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
580 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
582 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
584 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
786 CSR_WRITE_2(s
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H A Dbwiphy.c140 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
141 CSR_WRITE_2(sc, BWI_PHY_DATA, data);
149 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
442 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
452 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
489 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100);
536 CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0);
560 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
568 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
722 CSR_WRITE_2(s
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/freebsd-11-stable/sys/dev/an/
H A Dif_an.c339 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
340 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), 0xFFFF);
1204 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
1207 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), ~AN_INTRS(sc->mpi350));
1210 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_MIC);
1219 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_LINKSTAT);
1224 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_RX);
1229 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX_CPY);
1234 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX);
1239 CSR_WRITE_2(s
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/freebsd-11-stable/sys/dev/vge/
H A Dif_vgevar.h219 #define CSR_WRITE_2(sc, reg, val) \ macro
234 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
241 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/freebsd-11-stable/sys/dev/ste/
H A Dif_ste.c191 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
194 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
298 CSR_WRITE_2(sc, STE_MACCTL0, cfg);
395 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
448 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
449 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
450 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
451 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
552 CSR_WRITE_2(sc, STE_COUNTDOWN,
579 CSR_WRITE_2(s
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/freebsd-11-stable/sys/dev/tx/
H A Dif_txvar.h132 #define CSR_WRITE_2(sc, reg, val) \ macro
/freebsd-11-stable/sys/dev/tl/
H A Dif_tl.c378 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
391 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
404 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
418 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
432 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
435 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
446 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
462 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
482 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
501 CSR_WRITE_2(s
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/freebsd-11-stable/sys/dev/stge/
H A Dif_stge.c401 CSR_WRITE_2(sc, STGE_EepromCtrl,
1314 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1322 CSR_WRITE_2(sc, STGE_IntEnable,
1511 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2018 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2019 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2020 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2062 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2069 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2094 CSR_WRITE_2(s
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