1179645Smarcel/*- 2179645Smarcel * Copyright 2008 Nathan Whitehorn. All rights reserved. 3179645Smarcel * Copyright 2003 by Peter Grehan. All rights reserved. 4179645Smarcel * Copyright (C) 1998, 1999, 2000 Tsubai Masanari. All rights reserved. 5179645Smarcel * 6179645Smarcel * Redistribution and use in source and binary forms, with or without 7179645Smarcel * modification, are permitted provided that the following conditions 8179645Smarcel * are met: 9179645Smarcel * 1. Redistributions of source code must retain the above copyright 10179645Smarcel * notice, this list of conditions and the following disclaimer. 11179645Smarcel * 2. Redistributions in binary form must reproduce the above copyright 12179645Smarcel * notice, this list of conditions and the following disclaimer in the 13179645Smarcel * documentation and/or other materials provided with the distribution. 14179645Smarcel * 3. The name of the author may not be used to endorse or promote products 15179645Smarcel * derived from this software without specific prior written permission. 16179645Smarcel * 17179645Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18179645Smarcel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19179645Smarcel * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20179645Smarcel * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21179645Smarcel * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22179645Smarcel * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23179645Smarcel * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24179645Smarcel * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25179645Smarcel * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26179645Smarcel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27179645Smarcel * SUCH DAMAGE. 28179645Smarcel * 29179645Smarcel * From: 30179645Smarcel * NetBSD: if_bm.c,v 1.9.2.1 2000/11/01 15:02:49 tv Exp 31179645Smarcel */ 32179645Smarcel 33179645Smarcel/* 34179645Smarcel * BMAC/BMAC+ Macio cell 10/100 ethernet driver 35179645Smarcel * The low-cost, low-feature Apple variant of the Sun HME 36179645Smarcel */ 37179645Smarcel 38179645Smarcel#include <sys/cdefs.h> 39179645Smarcel__FBSDID("$FreeBSD: stable/11/sys/dev/bm/if_bm.c 347962 2019-05-18 20:43:13Z brooks $"); 40179645Smarcel 41179645Smarcel#include <sys/param.h> 42179645Smarcel#include <sys/systm.h> 43179645Smarcel#include <sys/sockio.h> 44179645Smarcel#include <sys/endian.h> 45179645Smarcel#include <sys/mbuf.h> 46179645Smarcel#include <sys/module.h> 47179645Smarcel#include <sys/malloc.h> 48179645Smarcel#include <sys/kernel.h> 49179645Smarcel#include <sys/socket.h> 50179645Smarcel 51179645Smarcel#include <net/bpf.h> 52179645Smarcel#include <net/if.h> 53257176Sglebius#include <net/if_var.h> 54179645Smarcel#include <net/if_arp.h> 55179645Smarcel#include <net/ethernet.h> 56179645Smarcel#include <net/if_dl.h> 57179645Smarcel#include <net/if_media.h> 58179645Smarcel#include <net/if_types.h> 59179645Smarcel 60179645Smarcel#include <machine/pio.h> 61179645Smarcel#include <machine/bus.h> 62179645Smarcel#include <machine/resource.h> 63179645Smarcel#include <sys/bus.h> 64179645Smarcel#include <sys/rman.h> 65179645Smarcel 66179645Smarcel#include <dev/mii/mii.h> 67226995Smarius#include <dev/mii/mii_bitbang.h> 68179645Smarcel#include <dev/mii/miivar.h> 69179645Smarcel 70179645Smarcel#include <dev/ofw/ofw_bus.h> 71179645Smarcel#include <dev/ofw/openfirm.h> 72179645Smarcel#include <machine/dbdma.h> 73179645Smarcel 74179645SmarcelMODULE_DEPEND(bm, ether, 1, 1, 1); 75179645SmarcelMODULE_DEPEND(bm, miibus, 1, 1, 1); 76179645Smarcel 77179645Smarcel/* "controller miibus0" required. See GENERIC if you get errors here. */ 78179645Smarcel#include "miibus_if.h" 79179645Smarcel 80179645Smarcel#include "if_bmreg.h" 81179645Smarcel#include "if_bmvar.h" 82179645Smarcel 83179645Smarcelstatic int bm_probe (device_t); 84179645Smarcelstatic int bm_attach (device_t); 85179645Smarcelstatic int bm_detach (device_t); 86188131Snwhitehornstatic int bm_shutdown (device_t); 87179645Smarcel 88179645Smarcelstatic void bm_start (struct ifnet *); 89179645Smarcelstatic void bm_start_locked (struct ifnet *); 90179645Smarcelstatic int bm_encap (struct bm_softc *sc, struct mbuf **m_head); 91179645Smarcelstatic int bm_ioctl (struct ifnet *, u_long, caddr_t); 92179645Smarcelstatic void bm_init (void *); 93179645Smarcelstatic void bm_init_locked (struct bm_softc *sc); 94179645Smarcelstatic void bm_chip_setup (struct bm_softc *sc); 95179645Smarcelstatic void bm_stop (struct bm_softc *sc); 96179645Smarcelstatic void bm_setladrf (struct bm_softc *sc); 97179645Smarcelstatic void bm_dummypacket (struct bm_softc *sc); 98179645Smarcelstatic void bm_txintr (void *xsc); 99179645Smarcelstatic void bm_rxintr (void *xsc); 100179645Smarcel 101179645Smarcelstatic int bm_add_rxbuf (struct bm_softc *sc, int i); 102179645Smarcelstatic int bm_add_rxbuf_dma (struct bm_softc *sc, int i); 103179645Smarcelstatic void bm_enable_interrupts (struct bm_softc *sc); 104179645Smarcelstatic void bm_disable_interrupts (struct bm_softc *sc); 105179645Smarcelstatic void bm_tick (void *xsc); 106179645Smarcel 107179645Smarcelstatic int bm_ifmedia_upd (struct ifnet *); 108179645Smarcelstatic void bm_ifmedia_sts (struct ifnet *, struct ifmediareq *); 109179645Smarcel 110179645Smarcelstatic int bm_miibus_readreg (device_t, int, int); 111179645Smarcelstatic int bm_miibus_writereg (device_t, int, int, int); 112179645Smarcelstatic void bm_miibus_statchg (device_t); 113179645Smarcel 114226995Smarius/* 115226995Smarius * MII bit-bang glue 116226995Smarius */ 117226995Smariusstatic uint32_t bm_mii_bitbang_read(device_t); 118226995Smariusstatic void bm_mii_bitbang_write(device_t, uint32_t); 119226995Smarius 120226995Smariusstatic const struct mii_bitbang_ops bm_mii_bitbang_ops = { 121226995Smarius bm_mii_bitbang_read, 122226995Smarius bm_mii_bitbang_write, 123226995Smarius { 124226995Smarius BM_MII_DATAOUT, /* MII_BIT_MDO */ 125226995Smarius BM_MII_DATAIN, /* MII_BIT_MDI */ 126226995Smarius BM_MII_CLK, /* MII_BIT_MDC */ 127226995Smarius BM_MII_OENABLE, /* MII_BIT_DIR_HOST_PHY */ 128226995Smarius 0, /* MII_BIT_DIR_PHY_HOST */ 129226995Smarius } 130226995Smarius}; 131226995Smarius 132179645Smarcelstatic device_method_t bm_methods[] = { 133179645Smarcel /* Device interface */ 134179645Smarcel DEVMETHOD(device_probe, bm_probe), 135179645Smarcel DEVMETHOD(device_attach, bm_attach), 136179645Smarcel DEVMETHOD(device_detach, bm_detach), 137179645Smarcel DEVMETHOD(device_shutdown, bm_shutdown), 138179645Smarcel 139179645Smarcel /* MII interface */ 140179645Smarcel DEVMETHOD(miibus_readreg, bm_miibus_readreg), 141179645Smarcel DEVMETHOD(miibus_writereg, bm_miibus_writereg), 142179645Smarcel DEVMETHOD(miibus_statchg, bm_miibus_statchg), 143227843Smarius 144227843Smarius DEVMETHOD_END 145179645Smarcel}; 146179645Smarcel 147179645Smarcelstatic driver_t bm_macio_driver = { 148179645Smarcel "bm", 149179645Smarcel bm_methods, 150179645Smarcel sizeof(struct bm_softc) 151179645Smarcel}; 152179645Smarcel 153179645Smarcelstatic devclass_t bm_devclass; 154179645Smarcel 155179645SmarcelDRIVER_MODULE(bm, macio, bm_macio_driver, bm_devclass, 0, 0); 156179645SmarcelDRIVER_MODULE(miibus, bm, miibus_driver, miibus_devclass, 0, 0); 157179645Smarcel 158179645Smarcel/* 159179645Smarcel * MII internal routines 160179645Smarcel */ 161179645Smarcel 162179645Smarcel/* 163226995Smarius * Write the MII serial port for the MII bit-bang module. 164179645Smarcel */ 165179645Smarcelstatic void 166226995Smariusbm_mii_bitbang_write(device_t dev, uint32_t val) 167179645Smarcel{ 168226995Smarius struct bm_softc *sc; 169179645Smarcel 170226995Smarius sc = device_get_softc(dev); 171179645Smarcel 172226995Smarius CSR_WRITE_2(sc, BM_MII_CSR, val); 173226995Smarius CSR_BARRIER(sc, BM_MII_CSR, 2, 174226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 175179645Smarcel} 176179645Smarcel 177179645Smarcel/* 178226995Smarius * Read the MII serial port for the MII bit-bang module. 179179645Smarcel */ 180226995Smariusstatic uint32_t 181226995Smariusbm_mii_bitbang_read(device_t dev) 182179645Smarcel{ 183226995Smarius struct bm_softc *sc; 184226995Smarius uint32_t reg; 185179645Smarcel 186226995Smarius sc = device_get_softc(dev); 187179645Smarcel 188226995Smarius reg = CSR_READ_2(sc, BM_MII_CSR); 189226995Smarius CSR_BARRIER(sc, BM_MII_CSR, 2, 190226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 191179645Smarcel 192226995Smarius return (reg); 193179645Smarcel} 194179645Smarcel 195179645Smarcel/* 196179645Smarcel * MII bus i/f 197179645Smarcel */ 198179645Smarcelstatic int 199179645Smarcelbm_miibus_readreg(device_t dev, int phy, int reg) 200179645Smarcel{ 201179645Smarcel 202226995Smarius return (mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg)); 203179645Smarcel} 204179645Smarcel 205179645Smarcelstatic int 206179645Smarcelbm_miibus_writereg(device_t dev, int phy, int reg, int data) 207179645Smarcel{ 208179645Smarcel 209226995Smarius mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg); 210179645Smarcel 211179645Smarcel return (0); 212179645Smarcel} 213179645Smarcel 214179645Smarcelstatic void 215179645Smarcelbm_miibus_statchg(device_t dev) 216179645Smarcel{ 217179645Smarcel struct bm_softc *sc = device_get_softc(dev); 218179645Smarcel uint16_t reg; 219179645Smarcel int new_duplex; 220179645Smarcel 221179645Smarcel reg = CSR_READ_2(sc, BM_TX_CONFIG); 222179645Smarcel new_duplex = IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX; 223179645Smarcel 224179645Smarcel if (new_duplex != sc->sc_duplex) { 225179645Smarcel /* Turn off TX MAC while we fiddle its settings */ 226179645Smarcel reg &= ~BM_ENABLE; 227179645Smarcel 228179645Smarcel CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 229179645Smarcel while (CSR_READ_2(sc, BM_TX_CONFIG) & BM_ENABLE) 230179645Smarcel DELAY(10); 231179645Smarcel } 232179645Smarcel 233179645Smarcel if (new_duplex && !sc->sc_duplex) 234179645Smarcel reg |= BM_TX_IGNORECOLL | BM_TX_FULLDPX; 235179645Smarcel else if (!new_duplex && sc->sc_duplex) 236179645Smarcel reg &= ~(BM_TX_IGNORECOLL | BM_TX_FULLDPX); 237179645Smarcel 238179645Smarcel if (new_duplex != sc->sc_duplex) { 239179645Smarcel /* Turn TX MAC back on */ 240179645Smarcel reg |= BM_ENABLE; 241179645Smarcel 242179645Smarcel CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 243179645Smarcel sc->sc_duplex = new_duplex; 244179645Smarcel } 245179645Smarcel} 246179645Smarcel 247179645Smarcel/* 248179645Smarcel * ifmedia/mii callbacks 249179645Smarcel */ 250179645Smarcelstatic int 251179645Smarcelbm_ifmedia_upd(struct ifnet *ifp) 252179645Smarcel{ 253179645Smarcel struct bm_softc *sc = ifp->if_softc; 254179645Smarcel int error; 255179645Smarcel 256179645Smarcel BM_LOCK(sc); 257179645Smarcel error = mii_mediachg(sc->sc_mii); 258179645Smarcel BM_UNLOCK(sc); 259179645Smarcel return (error); 260179645Smarcel} 261179645Smarcel 262179645Smarcelstatic void 263179645Smarcelbm_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifm) 264179645Smarcel{ 265179645Smarcel struct bm_softc *sc = ifp->if_softc; 266179645Smarcel 267179645Smarcel BM_LOCK(sc); 268179645Smarcel mii_pollstat(sc->sc_mii); 269179645Smarcel ifm->ifm_active = sc->sc_mii->mii_media_active; 270179645Smarcel ifm->ifm_status = sc->sc_mii->mii_media_status; 271179645Smarcel BM_UNLOCK(sc); 272179645Smarcel} 273179645Smarcel 274179645Smarcel/* 275179645Smarcel * Macio probe/attach 276179645Smarcel */ 277179645Smarcelstatic int 278179645Smarcelbm_probe(device_t dev) 279179645Smarcel{ 280179645Smarcel const char *dname = ofw_bus_get_name(dev); 281179645Smarcel const char *dcompat = ofw_bus_get_compat(dev); 282179645Smarcel 283179645Smarcel /* 284179645Smarcel * BMAC+ cells have a name of "ethernet" and 285179645Smarcel * a compatible property of "bmac+" 286179645Smarcel */ 287179645Smarcel if (strcmp(dname, "bmac") == 0) { 288179645Smarcel device_set_desc(dev, "Apple BMAC Ethernet Adaptor"); 289179645Smarcel } else if (strcmp(dcompat, "bmac+") == 0) { 290179645Smarcel device_set_desc(dev, "Apple BMAC+ Ethernet Adaptor"); 291179645Smarcel } else 292179645Smarcel return (ENXIO); 293179645Smarcel 294179645Smarcel return (0); 295179645Smarcel} 296179645Smarcel 297179645Smarcelstatic int 298179645Smarcelbm_attach(device_t dev) 299179645Smarcel{ 300179645Smarcel phandle_t node; 301179645Smarcel u_char *eaddr; 302179645Smarcel struct ifnet *ifp; 303179645Smarcel int error, cellid, i; 304179645Smarcel struct bm_txsoft *txs; 305179645Smarcel struct bm_softc *sc = device_get_softc(dev); 306179645Smarcel 307179645Smarcel ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 308179645Smarcel ifp->if_softc = sc; 309179645Smarcel sc->sc_dev = dev; 310179645Smarcel sc->sc_duplex = ~IFM_FDX; 311179645Smarcel 312179645Smarcel error = 0; 313179645Smarcel mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 314180233Snwhitehorn MTX_DEF); 315179645Smarcel callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 316179645Smarcel 317179645Smarcel /* Check for an improved version of Paddington */ 318179645Smarcel sc->sc_streaming = 0; 319179645Smarcel cellid = -1; 320179645Smarcel node = ofw_bus_get_node(dev); 321179645Smarcel 322179645Smarcel OF_getprop(node, "cell-id", &cellid, sizeof(cellid)); 323179645Smarcel if (cellid >= 0xc4) 324179645Smarcel sc->sc_streaming = 1; 325179645Smarcel 326179645Smarcel sc->sc_memrid = 0; 327179645Smarcel sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 328179645Smarcel &sc->sc_memrid, RF_ACTIVE); 329179645Smarcel if (sc->sc_memr == NULL) { 330179645Smarcel device_printf(dev, "Could not alloc chip registers!\n"); 331179645Smarcel return (ENXIO); 332179645Smarcel } 333179645Smarcel 334179645Smarcel sc->sc_txdmarid = BM_TXDMA_REGISTERS; 335179645Smarcel sc->sc_rxdmarid = BM_RXDMA_REGISTERS; 336179645Smarcel 337179645Smarcel sc->sc_txdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 338179645Smarcel &sc->sc_txdmarid, RF_ACTIVE); 339179645Smarcel sc->sc_rxdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 340179645Smarcel &sc->sc_rxdmarid, RF_ACTIVE); 341179645Smarcel 342179645Smarcel if (sc->sc_txdmar == NULL || sc->sc_rxdmar == NULL) { 343179645Smarcel device_printf(dev, "Could not map DBDMA registers!\n"); 344179645Smarcel return (ENXIO); 345179645Smarcel } 346179645Smarcel 347183288Snwhitehorn error = dbdma_allocate_channel(sc->sc_txdmar, 0, bus_get_dma_tag(dev), 348179645Smarcel BM_MAX_DMA_COMMANDS, &sc->sc_txdma); 349183288Snwhitehorn error += dbdma_allocate_channel(sc->sc_rxdmar, 0, bus_get_dma_tag(dev), 350179645Smarcel BM_MAX_DMA_COMMANDS, &sc->sc_rxdma); 351179645Smarcel 352179645Smarcel if (error) { 353179645Smarcel device_printf(dev,"Could not allocate DBDMA channel!\n"); 354179645Smarcel return (ENXIO); 355179645Smarcel } 356179645Smarcel 357179645Smarcel /* alloc DMA tags and buffers */ 358179645Smarcel error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 359179645Smarcel BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 360179645Smarcel BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 361179645Smarcel NULL, &sc->sc_pdma_tag); 362179645Smarcel 363179645Smarcel if (error) { 364179645Smarcel device_printf(dev,"Could not allocate DMA tag!\n"); 365179645Smarcel return (ENXIO); 366179645Smarcel } 367179645Smarcel 368179645Smarcel error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR, 369179645Smarcel BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 370179645Smarcel BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdma_tag); 371179645Smarcel 372179645Smarcel if (error) { 373179645Smarcel device_printf(dev,"Could not allocate RX DMA channel!\n"); 374179645Smarcel return (ENXIO); 375179645Smarcel } 376179645Smarcel 377179645Smarcel error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR, 378179645Smarcel BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * BM_NTXSEGS, BM_NTXSEGS, 379179645Smarcel MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdma_tag); 380179645Smarcel 381179645Smarcel if (error) { 382179645Smarcel device_printf(dev,"Could not allocate TX DMA tag!\n"); 383179645Smarcel return (ENXIO); 384179645Smarcel } 385179645Smarcel 386179645Smarcel /* init transmit descriptors */ 387179645Smarcel STAILQ_INIT(&sc->sc_txfreeq); 388179645Smarcel STAILQ_INIT(&sc->sc_txdirtyq); 389179645Smarcel 390179645Smarcel /* create TX DMA maps */ 391179645Smarcel error = ENOMEM; 392179645Smarcel for (i = 0; i < BM_MAX_TX_PACKETS; i++) { 393179645Smarcel txs = &sc->sc_txsoft[i]; 394179645Smarcel txs->txs_mbuf = NULL; 395179645Smarcel error = bus_dmamap_create(sc->sc_tdma_tag, 0, &txs->txs_dmamap); 396179645Smarcel if (error) { 397179645Smarcel device_printf(sc->sc_dev, 398179645Smarcel "unable to create TX DMA map %d, error = %d\n", 399179645Smarcel i, error); 400179645Smarcel } 401179645Smarcel STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 402179645Smarcel } 403179645Smarcel 404179645Smarcel /* Create the receive buffer DMA maps. */ 405179645Smarcel for (i = 0; i < BM_MAX_RX_PACKETS; i++) { 406179645Smarcel error = bus_dmamap_create(sc->sc_rdma_tag, 0, 407179645Smarcel &sc->sc_rxsoft[i].rxs_dmamap); 408179645Smarcel if (error) { 409179645Smarcel device_printf(sc->sc_dev, 410179645Smarcel "unable to create RX DMA map %d, error = %d\n", 411179645Smarcel i, error); 412179645Smarcel } 413179645Smarcel sc->sc_rxsoft[i].rxs_mbuf = NULL; 414179645Smarcel } 415179645Smarcel 416179645Smarcel /* alloc interrupt */ 417221519Snwhitehorn bm_disable_interrupts(sc); 418179645Smarcel 419179645Smarcel sc->sc_txdmairqid = BM_TXDMA_INTERRUPT; 420179645Smarcel sc->sc_txdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 421179645Smarcel &sc->sc_txdmairqid, RF_ACTIVE); 422179645Smarcel 423179645Smarcel if (error) { 424179645Smarcel device_printf(dev,"Could not allocate TX interrupt!\n"); 425179645Smarcel return (ENXIO); 426179645Smarcel } 427179645Smarcel 428179645Smarcel bus_setup_intr(dev,sc->sc_txdmairq, 429179645Smarcel INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_txintr, sc, 430179645Smarcel &sc->sc_txihtx); 431179645Smarcel 432179645Smarcel sc->sc_rxdmairqid = BM_RXDMA_INTERRUPT; 433179645Smarcel sc->sc_rxdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 434179645Smarcel &sc->sc_rxdmairqid, RF_ACTIVE); 435179645Smarcel 436179645Smarcel if (error) { 437179645Smarcel device_printf(dev,"Could not allocate RX interrupt!\n"); 438179645Smarcel return (ENXIO); 439179645Smarcel } 440179645Smarcel 441179645Smarcel bus_setup_intr(dev,sc->sc_rxdmairq, 442179645Smarcel INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_rxintr, sc, 443179645Smarcel &sc->sc_rxih); 444179645Smarcel 445179645Smarcel /* 446179645Smarcel * Get the ethernet address from OpenFirmware 447179645Smarcel */ 448179645Smarcel eaddr = sc->sc_enaddr; 449179645Smarcel OF_getprop(node, "local-mac-address", eaddr, ETHER_ADDR_LEN); 450179645Smarcel 451213893Smarius /* 452213893Smarius * Setup MII 453213893Smarius * On Apple BMAC controllers, we end up in a weird state of 454213893Smarius * partially-completed autonegotiation on boot. So we force 455213893Smarius * autonegotation to try again. 456213893Smarius */ 457213893Smarius error = mii_attach(dev, &sc->sc_miibus, ifp, bm_ifmedia_upd, 458213893Smarius bm_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 459213893Smarius MIIF_FORCEANEG); 460213893Smarius if (error != 0) { 461213893Smarius device_printf(dev, "attaching PHYs failed\n"); 462213893Smarius return (error); 463213893Smarius } 464179645Smarcel 465221519Snwhitehorn /* reset the adapter */ 466221519Snwhitehorn bm_chip_setup(sc); 467221519Snwhitehorn 468179645Smarcel sc->sc_mii = device_get_softc(sc->sc_miibus); 469179645Smarcel 470179645Smarcel if_initname(ifp, device_get_name(sc->sc_dev), 471179645Smarcel device_get_unit(sc->sc_dev)); 472179645Smarcel ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 473179645Smarcel ifp->if_start = bm_start; 474179645Smarcel ifp->if_ioctl = bm_ioctl; 475179645Smarcel ifp->if_init = bm_init; 476179645Smarcel IFQ_SET_MAXLEN(&ifp->if_snd, BM_MAX_TX_PACKETS); 477179645Smarcel ifp->if_snd.ifq_drv_maxlen = BM_MAX_TX_PACKETS; 478179645Smarcel IFQ_SET_READY(&ifp->if_snd); 479179645Smarcel 480179645Smarcel /* Attach the interface. */ 481179645Smarcel ether_ifattach(ifp, sc->sc_enaddr); 482179645Smarcel ifp->if_hwassist = 0; 483179645Smarcel 484347962Sbrooks gone_by_fcp101_dev(dev); 485347962Sbrooks 486179645Smarcel return (0); 487179645Smarcel} 488179645Smarcel 489179645Smarcelstatic int 490179645Smarcelbm_detach(device_t dev) 491179645Smarcel{ 492179645Smarcel struct bm_softc *sc = device_get_softc(dev); 493179645Smarcel 494179645Smarcel BM_LOCK(sc); 495179645Smarcel bm_stop(sc); 496180233Snwhitehorn BM_UNLOCK(sc); 497179645Smarcel 498180233Snwhitehorn callout_drain(&sc->sc_tick_ch); 499180233Snwhitehorn ether_ifdetach(sc->sc_ifp); 500180233Snwhitehorn bus_teardown_intr(dev, sc->sc_txdmairq, sc->sc_txihtx); 501180233Snwhitehorn bus_teardown_intr(dev, sc->sc_rxdmairq, sc->sc_rxih); 502180233Snwhitehorn 503179645Smarcel dbdma_free_channel(sc->sc_txdma); 504179645Smarcel dbdma_free_channel(sc->sc_rxdma); 505179645Smarcel 506179645Smarcel bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr); 507179645Smarcel bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_txdmarid, 508179645Smarcel sc->sc_txdmar); 509179645Smarcel bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rxdmarid, 510179645Smarcel sc->sc_rxdmar); 511179645Smarcel 512179645Smarcel bus_release_resource(dev, SYS_RES_IRQ, sc->sc_txdmairqid, 513179645Smarcel sc->sc_txdmairq); 514179645Smarcel bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rxdmairqid, 515179645Smarcel sc->sc_rxdmairq); 516179645Smarcel 517179645Smarcel mtx_destroy(&sc->sc_mtx); 518180233Snwhitehorn if_free(sc->sc_ifp); 519179645Smarcel 520179645Smarcel return (0); 521179645Smarcel} 522179645Smarcel 523188131Snwhitehornstatic int 524179645Smarcelbm_shutdown(device_t dev) 525179645Smarcel{ 526180233Snwhitehorn struct bm_softc *sc; 527180233Snwhitehorn 528180233Snwhitehorn sc = device_get_softc(dev); 529180233Snwhitehorn 530180233Snwhitehorn BM_LOCK(sc); 531180233Snwhitehorn bm_stop(sc); 532180233Snwhitehorn BM_UNLOCK(sc); 533188131Snwhitehorn 534188131Snwhitehorn return (0); 535179645Smarcel} 536179645Smarcel 537179645Smarcelstatic void 538179645Smarcelbm_dummypacket(struct bm_softc *sc) 539179645Smarcel{ 540179645Smarcel struct mbuf *m; 541179645Smarcel struct ifnet *ifp; 542179645Smarcel 543179645Smarcel ifp = sc->sc_ifp; 544179645Smarcel 545243857Sglebius MGETHDR(m, M_NOWAIT, MT_DATA); 546179645Smarcel 547179645Smarcel if (m == NULL) 548179645Smarcel return; 549179645Smarcel 550179645Smarcel bcopy(sc->sc_enaddr, 551179645Smarcel mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 552179645Smarcel bcopy(sc->sc_enaddr, 553179645Smarcel mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 554179645Smarcel mtod(m, struct ether_header *)->ether_type = htons(3); 555179645Smarcel mtod(m, unsigned char *)[14] = 0; 556179645Smarcel mtod(m, unsigned char *)[15] = 0; 557179645Smarcel mtod(m, unsigned char *)[16] = 0xE3; 558179645Smarcel m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 559179645Smarcel IF_ENQUEUE(&ifp->if_snd, m); 560182670Snwhitehorn bm_start_locked(ifp); 561179645Smarcel} 562179645Smarcel 563179645Smarcelstatic void 564179645Smarcelbm_rxintr(void *xsc) 565179645Smarcel{ 566179645Smarcel struct bm_softc *sc = xsc; 567179645Smarcel struct ifnet *ifp = sc->sc_ifp; 568179645Smarcel struct mbuf *m; 569179645Smarcel int i, prev_stop, new_stop; 570179645Smarcel uint16_t status; 571179645Smarcel 572179645Smarcel BM_LOCK(sc); 573179645Smarcel 574179645Smarcel status = dbdma_get_chan_status(sc->sc_rxdma); 575179645Smarcel if (status & DBDMA_STATUS_DEAD) { 576179645Smarcel dbdma_reset(sc->sc_rxdma); 577179645Smarcel BM_UNLOCK(sc); 578179645Smarcel return; 579179645Smarcel } 580179645Smarcel if (!(status & DBDMA_STATUS_RUN)) { 581179645Smarcel device_printf(sc->sc_dev,"Bad RX Interrupt!\n"); 582179645Smarcel BM_UNLOCK(sc); 583179645Smarcel return; 584179645Smarcel } 585179645Smarcel 586179645Smarcel prev_stop = sc->next_rxdma_slot - 1; 587179645Smarcel if (prev_stop < 0) 588179645Smarcel prev_stop = sc->rxdma_loop_slot - 1; 589179645Smarcel 590179645Smarcel if (prev_stop < 0) { 591179645Smarcel BM_UNLOCK(sc); 592179645Smarcel return; 593179645Smarcel } 594179645Smarcel 595179645Smarcel new_stop = -1; 596179645Smarcel dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_POSTREAD); 597179645Smarcel 598179645Smarcel for (i = sc->next_rxdma_slot; i < BM_MAX_RX_PACKETS; i++) { 599179645Smarcel if (i == sc->rxdma_loop_slot) 600179645Smarcel i = 0; 601179645Smarcel 602179645Smarcel if (i == prev_stop) 603179645Smarcel break; 604179645Smarcel 605179645Smarcel status = dbdma_get_cmd_status(sc->sc_rxdma, i); 606179645Smarcel 607179645Smarcel if (status == 0) 608179645Smarcel break; 609179645Smarcel 610179645Smarcel m = sc->sc_rxsoft[i].rxs_mbuf; 611179645Smarcel 612179645Smarcel if (bm_add_rxbuf(sc, i)) { 613271830Sglebius if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 614179645Smarcel m = NULL; 615179645Smarcel continue; 616179645Smarcel } 617179645Smarcel 618179645Smarcel if (m == NULL) 619179645Smarcel continue; 620179645Smarcel 621271830Sglebius if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 622179645Smarcel m->m_pkthdr.rcvif = ifp; 623179645Smarcel m->m_len -= (dbdma_get_residuals(sc->sc_rxdma, i) + 2); 624179645Smarcel m->m_pkthdr.len = m->m_len; 625179645Smarcel 626179645Smarcel /* Send up the stack */ 627179645Smarcel BM_UNLOCK(sc); 628179645Smarcel (*ifp->if_input)(ifp, m); 629179645Smarcel BM_LOCK(sc); 630179645Smarcel 631179645Smarcel /* Clear all fields on this command */ 632179645Smarcel bm_add_rxbuf_dma(sc, i); 633179645Smarcel 634179645Smarcel new_stop = i; 635179645Smarcel } 636179645Smarcel 637179645Smarcel /* Change the last packet we processed to the ring buffer terminator, 638179645Smarcel * and restore a receive buffer to the old terminator */ 639179645Smarcel if (new_stop >= 0) { 640179645Smarcel dbdma_insert_stop(sc->sc_rxdma, new_stop); 641179645Smarcel bm_add_rxbuf_dma(sc, prev_stop); 642179645Smarcel if (i < sc->rxdma_loop_slot) 643179645Smarcel sc->next_rxdma_slot = i; 644179645Smarcel else 645179645Smarcel sc->next_rxdma_slot = 0; 646179645Smarcel } 647179645Smarcel dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE); 648179645Smarcel 649179645Smarcel dbdma_wake(sc->sc_rxdma); 650179645Smarcel 651179645Smarcel BM_UNLOCK(sc); 652179645Smarcel} 653179645Smarcel 654179645Smarcelstatic void 655179645Smarcelbm_txintr(void *xsc) 656179645Smarcel{ 657179645Smarcel struct bm_softc *sc = xsc; 658179645Smarcel struct ifnet *ifp = sc->sc_ifp; 659179645Smarcel struct bm_txsoft *txs; 660179645Smarcel int progress = 0; 661179645Smarcel 662179645Smarcel BM_LOCK(sc); 663179645Smarcel 664179645Smarcel while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 665179645Smarcel if (!dbdma_get_cmd_status(sc->sc_txdma, txs->txs_lastdesc)) 666179645Smarcel break; 667179645Smarcel 668179645Smarcel STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 669179645Smarcel bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap); 670179645Smarcel 671179645Smarcel if (txs->txs_mbuf != NULL) { 672179645Smarcel m_freem(txs->txs_mbuf); 673179645Smarcel txs->txs_mbuf = NULL; 674179645Smarcel } 675179645Smarcel 676179645Smarcel /* Set the first used TXDMA slot to the location of the 677179645Smarcel * STOP/NOP command associated with this packet. */ 678179645Smarcel 679179645Smarcel sc->first_used_txdma_slot = txs->txs_stopdesc; 680179645Smarcel 681179645Smarcel STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 682179645Smarcel 683271830Sglebius if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 684179645Smarcel progress = 1; 685179645Smarcel } 686179645Smarcel 687179645Smarcel if (progress) { 688179645Smarcel /* 689179645Smarcel * We freed some descriptors, so reset IFF_DRV_OACTIVE 690179645Smarcel * and restart. 691179645Smarcel */ 692179645Smarcel ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 693179645Smarcel sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 694179645Smarcel 695179645Smarcel if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 696179645Smarcel !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 697179645Smarcel bm_start_locked(ifp); 698179645Smarcel } 699179645Smarcel 700179645Smarcel BM_UNLOCK(sc); 701179645Smarcel} 702179645Smarcel 703179645Smarcelstatic void 704179645Smarcelbm_start(struct ifnet *ifp) 705179645Smarcel{ 706179645Smarcel struct bm_softc *sc = ifp->if_softc; 707179645Smarcel 708179645Smarcel BM_LOCK(sc); 709179645Smarcel bm_start_locked(ifp); 710179645Smarcel BM_UNLOCK(sc); 711179645Smarcel} 712179645Smarcel 713179645Smarcelstatic void 714179645Smarcelbm_start_locked(struct ifnet *ifp) 715179645Smarcel{ 716179645Smarcel struct bm_softc *sc = ifp->if_softc; 717179645Smarcel struct mbuf *mb_head; 718179645Smarcel int prev_stop; 719179645Smarcel int txqueued = 0; 720179645Smarcel 721179645Smarcel /* 722179645Smarcel * We lay out our DBDMA program in the following manner: 723179645Smarcel * OUTPUT_MORE 724179645Smarcel * ... 725179645Smarcel * OUTPUT_LAST (+ Interrupt) 726179645Smarcel * STOP 727179645Smarcel * 728179645Smarcel * To extend the channel, we append a new program, 729179645Smarcel * then replace STOP with NOP and wake the channel. 730179645Smarcel * If we stalled on the STOP already, the program proceeds, 731179645Smarcel * if not it will sail through the NOP. 732179645Smarcel */ 733179645Smarcel 734179645Smarcel while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 735179645Smarcel IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 736179645Smarcel 737179645Smarcel if (mb_head == NULL) 738179645Smarcel break; 739179645Smarcel 740179645Smarcel prev_stop = sc->next_txdma_slot - 1; 741179645Smarcel 742179645Smarcel if (bm_encap(sc, &mb_head)) { 743179645Smarcel /* Put the packet back and stop */ 744179645Smarcel ifp->if_drv_flags |= IFF_DRV_OACTIVE; 745179645Smarcel IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 746179645Smarcel break; 747179645Smarcel } 748179645Smarcel 749179645Smarcel dbdma_insert_nop(sc->sc_txdma, prev_stop); 750179645Smarcel 751179645Smarcel txqueued = 1; 752179645Smarcel 753179645Smarcel BPF_MTAP(ifp, mb_head); 754179645Smarcel } 755179645Smarcel 756179645Smarcel dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE); 757179645Smarcel 758179645Smarcel if (txqueued) { 759179645Smarcel dbdma_wake(sc->sc_txdma); 760179645Smarcel sc->sc_wdog_timer = 5; 761179645Smarcel } 762179645Smarcel} 763179645Smarcel 764179645Smarcelstatic int 765179645Smarcelbm_encap(struct bm_softc *sc, struct mbuf **m_head) 766179645Smarcel{ 767179645Smarcel bus_dma_segment_t segs[BM_NTXSEGS]; 768179645Smarcel struct bm_txsoft *txs; 769179645Smarcel struct mbuf *m; 770179645Smarcel int nsegs = BM_NTXSEGS; 771179645Smarcel int error = 0; 772179645Smarcel uint8_t branch_type; 773179645Smarcel int i; 774179645Smarcel 775179645Smarcel /* Limit the command size to the number of free DBDMA slots */ 776179645Smarcel 777179645Smarcel if (sc->next_txdma_slot >= sc->first_used_txdma_slot) 778179645Smarcel nsegs = BM_MAX_DMA_COMMANDS - 2 - sc->next_txdma_slot + 779179645Smarcel sc->first_used_txdma_slot; /* -2 for branch and indexing */ 780179645Smarcel else 781179645Smarcel nsegs = sc->first_used_txdma_slot - sc->next_txdma_slot; 782179645Smarcel 783179645Smarcel /* Remove one slot for the STOP/NOP terminator */ 784179645Smarcel nsegs--; 785179645Smarcel 786179645Smarcel if (nsegs > BM_NTXSEGS) 787179645Smarcel nsegs = BM_NTXSEGS; 788179645Smarcel 789179645Smarcel /* Get a work queue entry. */ 790179645Smarcel if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 791179645Smarcel /* Ran out of descriptors. */ 792179645Smarcel return (ENOBUFS); 793179645Smarcel } 794179645Smarcel 795179645Smarcel error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, txs->txs_dmamap, 796179645Smarcel *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 797179645Smarcel 798179645Smarcel if (error == EFBIG) { 799243857Sglebius m = m_collapse(*m_head, M_NOWAIT, nsegs); 800179645Smarcel if (m == NULL) { 801179645Smarcel m_freem(*m_head); 802179645Smarcel *m_head = NULL; 803179645Smarcel return (ENOBUFS); 804179645Smarcel } 805179645Smarcel *m_head = m; 806179645Smarcel 807179645Smarcel error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, 808179645Smarcel txs->txs_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 809179645Smarcel if (error != 0) { 810179645Smarcel m_freem(*m_head); 811179645Smarcel *m_head = NULL; 812179645Smarcel return (error); 813179645Smarcel } 814179645Smarcel } else if (error != 0) 815179645Smarcel return (error); 816179645Smarcel 817179645Smarcel if (nsegs == 0) { 818179645Smarcel m_freem(*m_head); 819179645Smarcel *m_head = NULL; 820179645Smarcel return (EIO); 821179645Smarcel } 822179645Smarcel 823179645Smarcel txs->txs_ndescs = nsegs; 824179645Smarcel txs->txs_firstdesc = sc->next_txdma_slot; 825179645Smarcel 826179645Smarcel for (i = 0; i < nsegs; i++) { 827179645Smarcel /* Loop back to the beginning if this is our last slot */ 828179645Smarcel if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) 829179645Smarcel branch_type = DBDMA_ALWAYS; 830179645Smarcel else 831179645Smarcel branch_type = DBDMA_NEVER; 832179645Smarcel 833179645Smarcel if (i+1 == nsegs) 834179645Smarcel txs->txs_lastdesc = sc->next_txdma_slot; 835179645Smarcel 836179645Smarcel dbdma_insert_command(sc->sc_txdma, sc->next_txdma_slot++, 837179645Smarcel (i + 1 < nsegs) ? DBDMA_OUTPUT_MORE : DBDMA_OUTPUT_LAST, 838179645Smarcel 0, segs[i].ds_addr, segs[i].ds_len, 839179645Smarcel (i + 1 < nsegs) ? DBDMA_NEVER : DBDMA_ALWAYS, 840179645Smarcel branch_type, DBDMA_NEVER, 0); 841179645Smarcel 842179645Smarcel if (branch_type == DBDMA_ALWAYS) 843179645Smarcel sc->next_txdma_slot = 0; 844179645Smarcel } 845179645Smarcel 846179645Smarcel /* We have a corner case where the STOP command is the last slot, 847179645Smarcel * but you can't branch in STOP commands. So add a NOP branch here 848179645Smarcel * and the STOP in slot 0. */ 849179645Smarcel 850179645Smarcel if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) { 851179645Smarcel dbdma_insert_branch(sc->sc_txdma, sc->next_txdma_slot, 0); 852179645Smarcel sc->next_txdma_slot = 0; 853179645Smarcel } 854179645Smarcel 855179645Smarcel txs->txs_stopdesc = sc->next_txdma_slot; 856179645Smarcel dbdma_insert_stop(sc->sc_txdma, sc->next_txdma_slot++); 857179645Smarcel 858179645Smarcel STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 859179645Smarcel STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 860179645Smarcel txs->txs_mbuf = *m_head; 861179645Smarcel 862179645Smarcel return (0); 863179645Smarcel} 864179645Smarcel 865179645Smarcelstatic int 866179645Smarcelbm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 867179645Smarcel{ 868179645Smarcel struct bm_softc *sc = ifp->if_softc; 869179645Smarcel struct ifreq *ifr = (struct ifreq *)data; 870179645Smarcel int error; 871179645Smarcel 872179645Smarcel error = 0; 873179645Smarcel 874179645Smarcel switch(cmd) { 875179645Smarcel case SIOCSIFFLAGS: 876179645Smarcel BM_LOCK(sc); 877179645Smarcel if ((ifp->if_flags & IFF_UP) != 0) { 878179645Smarcel if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 879179645Smarcel ((ifp->if_flags ^ sc->sc_ifpflags) & 880179645Smarcel (IFF_ALLMULTI | IFF_PROMISC)) != 0) 881179645Smarcel bm_setladrf(sc); 882179645Smarcel else 883179645Smarcel bm_init_locked(sc); 884179645Smarcel } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 885179645Smarcel bm_stop(sc); 886179645Smarcel sc->sc_ifpflags = ifp->if_flags; 887179645Smarcel BM_UNLOCK(sc); 888179645Smarcel break; 889179645Smarcel case SIOCADDMULTI: 890179645Smarcel case SIOCDELMULTI: 891179645Smarcel BM_LOCK(sc); 892179645Smarcel bm_setladrf(sc); 893179645Smarcel BM_UNLOCK(sc); 894179645Smarcel case SIOCGIFMEDIA: 895179645Smarcel case SIOCSIFMEDIA: 896179645Smarcel error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 897179645Smarcel break; 898179645Smarcel default: 899179645Smarcel error = ether_ioctl(ifp, cmd, data); 900179645Smarcel break; 901179645Smarcel } 902179645Smarcel 903179645Smarcel return (error); 904179645Smarcel} 905179645Smarcel 906179645Smarcelstatic void 907179645Smarcelbm_setladrf(struct bm_softc *sc) 908179645Smarcel{ 909179645Smarcel struct ifnet *ifp = sc->sc_ifp; 910179645Smarcel struct ifmultiaddr *inm; 911179645Smarcel uint16_t hash[4]; 912179645Smarcel uint16_t reg; 913179645Smarcel uint32_t crc; 914179645Smarcel 915179645Smarcel reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS; 916179645Smarcel 917179645Smarcel /* Turn off RX MAC while we fiddle its settings */ 918179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 919179645Smarcel while (CSR_READ_2(sc, BM_RX_CONFIG) & BM_ENABLE) 920179645Smarcel DELAY(10); 921179645Smarcel 922179645Smarcel if ((ifp->if_flags & IFF_PROMISC) != 0) { 923179645Smarcel reg |= BM_PROMISC; 924179645Smarcel 925179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 926179645Smarcel 927179645Smarcel DELAY(15); 928179645Smarcel 929179645Smarcel reg = CSR_READ_2(sc, BM_RX_CONFIG); 930179645Smarcel reg |= BM_ENABLE; 931179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 932179645Smarcel return; 933179645Smarcel } 934179645Smarcel 935179645Smarcel if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 936179645Smarcel hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 937179645Smarcel } else { 938179645Smarcel /* Clear the hash table. */ 939179645Smarcel memset(hash, 0, sizeof(hash)); 940179645Smarcel 941195049Srwatson if_maddr_rlock(ifp); 942179645Smarcel TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 943179645Smarcel if (inm->ifma_addr->sa_family != AF_LINK) 944179645Smarcel continue; 945179645Smarcel crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 946179645Smarcel inm->ifma_addr), ETHER_ADDR_LEN); 947179645Smarcel 948179645Smarcel /* We just want the 6 most significant bits */ 949179645Smarcel crc >>= 26; 950179645Smarcel 951179645Smarcel /* Set the corresponding bit in the filter. */ 952179645Smarcel hash[crc >> 4] |= 1 << (crc & 0xf); 953179645Smarcel } 954195049Srwatson if_maddr_runlock(ifp); 955179645Smarcel } 956179645Smarcel 957179645Smarcel /* Write out new hash table */ 958179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]); 959179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]); 960179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]); 961179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB3, hash[3]); 962179645Smarcel 963179645Smarcel /* And turn the RX MAC back on, this time with the hash bit set */ 964179645Smarcel reg |= BM_HASH_FILTER_ENABLE; 965179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 966179645Smarcel 967179645Smarcel while (!(CSR_READ_2(sc, BM_RX_CONFIG) & BM_HASH_FILTER_ENABLE)) 968179645Smarcel DELAY(10); 969179645Smarcel 970179645Smarcel reg = CSR_READ_2(sc, BM_RX_CONFIG); 971179645Smarcel reg |= BM_ENABLE; 972179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 973179645Smarcel} 974179645Smarcel 975179645Smarcelstatic void 976179645Smarcelbm_init(void *xsc) 977179645Smarcel{ 978179645Smarcel struct bm_softc *sc = xsc; 979179645Smarcel 980179645Smarcel BM_LOCK(sc); 981179645Smarcel bm_init_locked(sc); 982179645Smarcel BM_UNLOCK(sc); 983179645Smarcel} 984179645Smarcel 985179645Smarcelstatic void 986179645Smarcelbm_chip_setup(struct bm_softc *sc) 987179645Smarcel{ 988179645Smarcel uint16_t reg; 989179645Smarcel uint16_t *eaddr_sect; 990179645Smarcel 991179645Smarcel eaddr_sect = (uint16_t *)(sc->sc_enaddr); 992221519Snwhitehorn dbdma_stop(sc->sc_txdma); 993221519Snwhitehorn dbdma_stop(sc->sc_rxdma); 994179645Smarcel 995179645Smarcel /* Reset chip */ 996179645Smarcel CSR_WRITE_2(sc, BM_RX_RESET, 0x0000); 997179645Smarcel CSR_WRITE_2(sc, BM_TX_RESET, 0x0001); 998179645Smarcel do { 999221519Snwhitehorn DELAY(10); 1000179645Smarcel reg = CSR_READ_2(sc, BM_TX_RESET); 1001179645Smarcel } while (reg & 0x0001); 1002179645Smarcel 1003179645Smarcel /* Some random junk. OS X uses the system time. We use 1004179645Smarcel * the low 16 bits of the MAC address. */ 1005179645Smarcel CSR_WRITE_2(sc, BM_TX_RANDSEED, eaddr_sect[2]); 1006179645Smarcel 1007179645Smarcel /* Enable transmit */ 1008179645Smarcel reg = CSR_READ_2(sc, BM_TX_IFC); 1009179645Smarcel reg |= BM_ENABLE; 1010179645Smarcel CSR_WRITE_2(sc, BM_TX_IFC, reg); 1011179645Smarcel 1012179645Smarcel CSR_READ_2(sc, BM_TX_PEAKCNT); 1013179645Smarcel} 1014179645Smarcel 1015179645Smarcelstatic void 1016179645Smarcelbm_stop(struct bm_softc *sc) 1017179645Smarcel{ 1018179645Smarcel struct bm_txsoft *txs; 1019179645Smarcel uint16_t reg; 1020179645Smarcel 1021179645Smarcel /* Disable TX and RX MACs */ 1022179645Smarcel reg = CSR_READ_2(sc, BM_TX_CONFIG); 1023179645Smarcel reg &= ~BM_ENABLE; 1024179645Smarcel CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 1025179645Smarcel 1026179645Smarcel reg = CSR_READ_2(sc, BM_RX_CONFIG); 1027179645Smarcel reg &= ~BM_ENABLE; 1028179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1029179645Smarcel 1030179645Smarcel DELAY(100); 1031179645Smarcel 1032179645Smarcel /* Stop DMA engine */ 1033179645Smarcel dbdma_stop(sc->sc_rxdma); 1034179645Smarcel dbdma_stop(sc->sc_txdma); 1035179645Smarcel sc->next_rxdma_slot = 0; 1036179645Smarcel sc->rxdma_loop_slot = 0; 1037179645Smarcel 1038179645Smarcel /* Disable interrupts */ 1039179645Smarcel bm_disable_interrupts(sc); 1040179645Smarcel 1041179645Smarcel /* Don't worry about pending transmits anymore */ 1042179645Smarcel while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1043179645Smarcel STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1044179645Smarcel if (txs->txs_ndescs != 0) { 1045179645Smarcel bus_dmamap_sync(sc->sc_tdma_tag, txs->txs_dmamap, 1046179645Smarcel BUS_DMASYNC_POSTWRITE); 1047179645Smarcel bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap); 1048179645Smarcel if (txs->txs_mbuf != NULL) { 1049179645Smarcel m_freem(txs->txs_mbuf); 1050179645Smarcel txs->txs_mbuf = NULL; 1051179645Smarcel } 1052179645Smarcel } 1053179645Smarcel STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1054179645Smarcel } 1055179645Smarcel 1056179645Smarcel /* And we're down */ 1057179645Smarcel sc->sc_ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1058179645Smarcel sc->sc_wdog_timer = 0; 1059180233Snwhitehorn callout_stop(&sc->sc_tick_ch); 1060179645Smarcel} 1061179645Smarcel 1062179645Smarcelstatic void 1063179645Smarcelbm_init_locked(struct bm_softc *sc) 1064179645Smarcel{ 1065179645Smarcel uint16_t reg; 1066179645Smarcel uint16_t *eaddr_sect; 1067179645Smarcel struct bm_rxsoft *rxs; 1068179645Smarcel int i; 1069179645Smarcel 1070179645Smarcel eaddr_sect = (uint16_t *)(sc->sc_enaddr); 1071179645Smarcel 1072179645Smarcel /* Zero RX slot info and stop DMA */ 1073179645Smarcel dbdma_stop(sc->sc_rxdma); 1074179645Smarcel dbdma_stop(sc->sc_txdma); 1075179645Smarcel sc->next_rxdma_slot = 0; 1076179645Smarcel sc->rxdma_loop_slot = 0; 1077179645Smarcel 1078179645Smarcel /* Initialize TX/RX DBDMA programs */ 1079179645Smarcel dbdma_insert_stop(sc->sc_rxdma, 0); 1080179645Smarcel dbdma_insert_stop(sc->sc_txdma, 0); 1081179645Smarcel dbdma_set_current_cmd(sc->sc_rxdma, 0); 1082179645Smarcel dbdma_set_current_cmd(sc->sc_txdma, 0); 1083179645Smarcel 1084179645Smarcel sc->next_rxdma_slot = 0; 1085179645Smarcel sc->next_txdma_slot = 1; 1086179645Smarcel sc->first_used_txdma_slot = 0; 1087179645Smarcel 1088179645Smarcel for (i = 0; i < BM_MAX_RX_PACKETS; i++) { 1089179645Smarcel rxs = &sc->sc_rxsoft[i]; 1090179645Smarcel rxs->dbdma_slot = i; 1091179645Smarcel 1092179645Smarcel if (rxs->rxs_mbuf == NULL) { 1093179645Smarcel bm_add_rxbuf(sc, i); 1094179645Smarcel 1095179645Smarcel if (rxs->rxs_mbuf == NULL) { 1096179645Smarcel /* If we can't add anymore, mark the problem */ 1097179645Smarcel rxs->dbdma_slot = -1; 1098179645Smarcel break; 1099179645Smarcel } 1100179645Smarcel } 1101179645Smarcel 1102179645Smarcel if (i > 0) 1103179645Smarcel bm_add_rxbuf_dma(sc, i); 1104179645Smarcel } 1105179645Smarcel 1106179645Smarcel /* 1107179645Smarcel * Now terminate the RX ring buffer, and follow with the loop to 1108179645Smarcel * the beginning. 1109179645Smarcel */ 1110179645Smarcel dbdma_insert_stop(sc->sc_rxdma, i - 1); 1111179645Smarcel dbdma_insert_branch(sc->sc_rxdma, i, 0); 1112179645Smarcel sc->rxdma_loop_slot = i; 1113179645Smarcel 1114179645Smarcel /* Now add in the first element of the RX DMA chain */ 1115179645Smarcel bm_add_rxbuf_dma(sc, 0); 1116179645Smarcel 1117179645Smarcel dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE); 1118179645Smarcel dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE); 1119179645Smarcel 1120179645Smarcel /* Zero collision counters */ 1121179645Smarcel CSR_WRITE_2(sc, BM_TX_NCCNT, 0); 1122179645Smarcel CSR_WRITE_2(sc, BM_TX_FCCNT, 0); 1123179645Smarcel CSR_WRITE_2(sc, BM_TX_EXCNT, 0); 1124179645Smarcel CSR_WRITE_2(sc, BM_TX_LTCNT, 0); 1125179645Smarcel 1126179645Smarcel /* Zero receive counters */ 1127179645Smarcel CSR_WRITE_2(sc, BM_RX_FRCNT, 0); 1128179645Smarcel CSR_WRITE_2(sc, BM_RX_LECNT, 0); 1129179645Smarcel CSR_WRITE_2(sc, BM_RX_AECNT, 0); 1130179645Smarcel CSR_WRITE_2(sc, BM_RX_FECNT, 0); 1131179645Smarcel CSR_WRITE_2(sc, BM_RXCV, 0); 1132179645Smarcel 1133179645Smarcel /* Prime transmit */ 1134179645Smarcel CSR_WRITE_2(sc, BM_TX_THRESH, 0xff); 1135179645Smarcel 1136179645Smarcel CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0); 1137179645Smarcel CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0x0001); 1138179645Smarcel 1139179645Smarcel /* Prime receive */ 1140179645Smarcel CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0); 1141179645Smarcel CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0x0001); 1142179645Smarcel 1143179645Smarcel /* Clear status reg */ 1144179645Smarcel CSR_READ_2(sc, BM_STATUS); 1145179645Smarcel 1146179645Smarcel /* Zero hash filters */ 1147179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB0, 0); 1148179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB1, 0); 1149179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB2, 0); 1150179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB3, 0); 1151179645Smarcel 1152179645Smarcel /* Write MAC address to chip */ 1153179645Smarcel CSR_WRITE_2(sc, BM_MACADDR0, eaddr_sect[0]); 1154179645Smarcel CSR_WRITE_2(sc, BM_MACADDR1, eaddr_sect[1]); 1155179645Smarcel CSR_WRITE_2(sc, BM_MACADDR2, eaddr_sect[2]); 1156179645Smarcel 1157179645Smarcel /* Final receive engine setup */ 1158179645Smarcel reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS | BM_HASH_FILTER_ENABLE; 1159179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1160179645Smarcel 1161179645Smarcel /* Now turn it all on! */ 1162179645Smarcel dbdma_reset(sc->sc_rxdma); 1163179645Smarcel dbdma_reset(sc->sc_txdma); 1164179645Smarcel 1165179645Smarcel /* Enable RX and TX MACs. Setting the address filter has 1166179645Smarcel * the side effect of enabling the RX MAC. */ 1167179645Smarcel bm_setladrf(sc); 1168179645Smarcel 1169179645Smarcel reg = CSR_READ_2(sc, BM_TX_CONFIG); 1170179645Smarcel reg |= BM_ENABLE; 1171179645Smarcel CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 1172179645Smarcel 1173179645Smarcel /* 1174179645Smarcel * Enable interrupts, unwedge the controller with a dummy packet, 1175179645Smarcel * and nudge the DMA queue. 1176179645Smarcel */ 1177179645Smarcel bm_enable_interrupts(sc); 1178179645Smarcel bm_dummypacket(sc); 1179179645Smarcel dbdma_wake(sc->sc_rxdma); /* Nudge RXDMA */ 1180179645Smarcel 1181179645Smarcel sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING; 1182179645Smarcel sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1183179645Smarcel sc->sc_ifpflags = sc->sc_ifp->if_flags; 1184179645Smarcel 1185179645Smarcel /* Resync PHY and MAC states */ 1186179645Smarcel sc->sc_mii = device_get_softc(sc->sc_miibus); 1187179645Smarcel sc->sc_duplex = ~IFM_FDX; 1188179645Smarcel mii_mediachg(sc->sc_mii); 1189179645Smarcel 1190179645Smarcel /* Start the one second timer. */ 1191179645Smarcel sc->sc_wdog_timer = 0; 1192179645Smarcel callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc); 1193179645Smarcel} 1194179645Smarcel 1195179645Smarcelstatic void 1196179645Smarcelbm_tick(void *arg) 1197179645Smarcel{ 1198179645Smarcel struct bm_softc *sc = arg; 1199179645Smarcel 1200179645Smarcel /* Read error counters */ 1201271830Sglebius if_inc_counter(sc->sc_ifp, IFCOUNTER_COLLISIONS, 1202271830Sglebius CSR_READ_2(sc, BM_TX_NCCNT) + CSR_READ_2(sc, BM_TX_FCCNT) + 1203271830Sglebius CSR_READ_2(sc, BM_TX_EXCNT) + CSR_READ_2(sc, BM_TX_LTCNT)); 1204179645Smarcel 1205271830Sglebius if_inc_counter(sc->sc_ifp, IFCOUNTER_IERRORS, 1206271830Sglebius CSR_READ_2(sc, BM_RX_LECNT) + CSR_READ_2(sc, BM_RX_AECNT) + 1207271830Sglebius CSR_READ_2(sc, BM_RX_FECNT)); 1208179645Smarcel 1209179645Smarcel /* Zero collision counters */ 1210179645Smarcel CSR_WRITE_2(sc, BM_TX_NCCNT, 0); 1211179645Smarcel CSR_WRITE_2(sc, BM_TX_FCCNT, 0); 1212179645Smarcel CSR_WRITE_2(sc, BM_TX_EXCNT, 0); 1213179645Smarcel CSR_WRITE_2(sc, BM_TX_LTCNT, 0); 1214179645Smarcel 1215179645Smarcel /* Zero receive counters */ 1216179645Smarcel CSR_WRITE_2(sc, BM_RX_FRCNT, 0); 1217179645Smarcel CSR_WRITE_2(sc, BM_RX_LECNT, 0); 1218179645Smarcel CSR_WRITE_2(sc, BM_RX_AECNT, 0); 1219179645Smarcel CSR_WRITE_2(sc, BM_RX_FECNT, 0); 1220179645Smarcel CSR_WRITE_2(sc, BM_RXCV, 0); 1221179645Smarcel 1222179645Smarcel /* Check for link changes and run watchdog */ 1223179645Smarcel mii_tick(sc->sc_mii); 1224179645Smarcel bm_miibus_statchg(sc->sc_dev); 1225179645Smarcel 1226180233Snwhitehorn if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) { 1227180233Snwhitehorn callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc); 1228179645Smarcel return; 1229180233Snwhitehorn } 1230179645Smarcel 1231180233Snwhitehorn /* Problems */ 1232179645Smarcel device_printf(sc->sc_dev, "device timeout\n"); 1233179645Smarcel 1234179645Smarcel bm_init_locked(sc); 1235179645Smarcel} 1236179645Smarcel 1237179645Smarcelstatic int 1238179645Smarcelbm_add_rxbuf(struct bm_softc *sc, int idx) 1239179645Smarcel{ 1240179645Smarcel struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1241179645Smarcel struct mbuf *m; 1242179645Smarcel bus_dma_segment_t segs[1]; 1243179645Smarcel int error, nsegs; 1244179645Smarcel 1245243857Sglebius m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1246179645Smarcel if (m == NULL) 1247179645Smarcel return (ENOBUFS); 1248179645Smarcel m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1249179645Smarcel 1250179645Smarcel if (rxs->rxs_mbuf != NULL) { 1251179645Smarcel bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, 1252179645Smarcel BUS_DMASYNC_POSTREAD); 1253179645Smarcel bus_dmamap_unload(sc->sc_rdma_tag, rxs->rxs_dmamap); 1254179645Smarcel } 1255179645Smarcel 1256179645Smarcel error = bus_dmamap_load_mbuf_sg(sc->sc_rdma_tag, rxs->rxs_dmamap, m, 1257179645Smarcel segs, &nsegs, BUS_DMA_NOWAIT); 1258179645Smarcel if (error != 0) { 1259179645Smarcel device_printf(sc->sc_dev, 1260179645Smarcel "cannot load RS DMA map %d, error = %d\n", idx, error); 1261179645Smarcel m_freem(m); 1262179645Smarcel return (error); 1263179645Smarcel } 1264179645Smarcel /* If nsegs is wrong then the stack is corrupt. */ 1265179645Smarcel KASSERT(nsegs == 1, 1266179645Smarcel ("%s: too many DMA segments (%d)", __func__, nsegs)); 1267179645Smarcel rxs->rxs_mbuf = m; 1268179645Smarcel rxs->segment = segs[0]; 1269179645Smarcel 1270179645Smarcel bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 1271179645Smarcel 1272179645Smarcel return (0); 1273179645Smarcel} 1274179645Smarcel 1275179645Smarcelstatic int 1276179645Smarcelbm_add_rxbuf_dma(struct bm_softc *sc, int idx) 1277179645Smarcel{ 1278179645Smarcel struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1279179645Smarcel 1280179645Smarcel dbdma_insert_command(sc->sc_rxdma, idx, DBDMA_INPUT_LAST, 0, 1281179645Smarcel rxs->segment.ds_addr, rxs->segment.ds_len, DBDMA_ALWAYS, 1282179645Smarcel DBDMA_NEVER, DBDMA_NEVER, 0); 1283179645Smarcel 1284179645Smarcel return (0); 1285179645Smarcel} 1286179645Smarcel 1287179645Smarcelstatic void 1288179645Smarcelbm_enable_interrupts(struct bm_softc *sc) 1289179645Smarcel{ 1290179645Smarcel CSR_WRITE_2(sc, BM_INTR_DISABLE, 1291179645Smarcel (sc->sc_streaming) ? BM_INTR_NONE : BM_INTR_NORMAL); 1292179645Smarcel} 1293179645Smarcel 1294179645Smarcelstatic void 1295179645Smarcelbm_disable_interrupts(struct bm_softc *sc) 1296179645Smarcel{ 1297179645Smarcel CSR_WRITE_2(sc, BM_INTR_DISABLE, BM_INTR_NONE); 1298179645Smarcel} 1299