Lines Matching refs:CSR_WRITE_2
191 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
194 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
298 CSR_WRITE_2(sc, STE_MACCTL0, cfg);
395 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
448 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
449 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
450 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
451 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
552 CSR_WRITE_2(sc, STE_COUNTDOWN,
579 CSR_WRITE_2(sc, STE_IMR, intrs);
727 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
1523 CSR_WRITE_2(sc, STE_PAR0 + i,
1552 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1558 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1586 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1587 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1596 CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
1597 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1601 CSR_WRITE_2(sc, STE_IMR, 0);
1605 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1633 CSR_WRITE_2(sc, STE_IMR, 0);
1634 CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
1650 CSR_WRITE_2(sc, STE_MACCTL1, val);
1727 CSR_WRITE_2(sc, STE_MACCTL1, mac);
1790 CSR_WRITE_2(sc, STE_IMR, 0);
1794 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);