Searched refs:ANY_EXTEND (Results 1 - 25 of 44) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h531 /// ANY_EXTEND - Used for integer types. The high bits are undefined.
532 ANY_EXTEND, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp117 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
317 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
330 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
345 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
388 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp);
394 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
439 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
595 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
679 // 1. ANY_EXTEND iN to iM
1261 case ISD::ANY_EXTEND
[all...]
H A DLegalizeVectorTypes.cpp72 case ISD::ANY_EXTEND:
393 return DAG.getNode(ISD::ANY_EXTEND, DL, EltVT, Op);
567 case ISD::ANY_EXTEND:
696 : DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Res);
795 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Res);
900 case ISD::ANY_EXTEND:
1438 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec);
1441 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, EltVT, Elt);
1972 case ISD::ANY_EXTEND:
2199 Vec = DAG.getNode(ISD::ANY_EXTEND, d
[all...]
H A DSelectionDAGBuilder.h893 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
H A DFunctionLoweringInfo.cpp67 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
H A DDAGCombiner.cpp1147 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
1149 return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op);
1568 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1675 case ISD::ANY_EXTEND:
4388 if (HandOpcode == ISD::ANY_EXTEND || HandOpcode == ISD::ZERO_EXTEND ||
4404 if (HandOpcode == ISD::ANY_EXTEND && LegalTypes &&
5114 if (Not.getOpcode() == ISD::ANY_EXTEND)
5224 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
5351 (N0.getOpcode() == ISD::ANY_EXTEND &&
5354 LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND
[all...]
H A DSelectionDAGDumper.cpp321 case ISD::ANY_EXTEND: return "any_extend";
H A DLegalizeTypes.cpp972 Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi);
H A DLegalizeTypesGeneric.cpp221 OldVec = DAG.getNode(ISD::ANY_EXTEND, dl, NVecVT, N->getOperand(0));
H A DLegalizeDAG.cpp2843 case ISD::ANY_EXTEND:
3343 SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]);
3385 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3391 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3510 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
4339 ExtOp = ISD::ANY_EXTEND;
4385 ExtOp = ISD::ANY_EXTEND;
H A DTargetLowering.cpp573 SDValue Z = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), X);
1370 if (Op0.getOpcode() == ISD::ANY_EXTEND) {
1383 Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, NarrowShl));
1401 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
1695 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
1728 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
1758 case ISD::ANY_EXTEND:
1767 // TODO: Handle ANY_EXTEND?
3523 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
6704 ISD::ANY_EXTEND, d
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h539 return ISD::ANY_EXTEND;
H A DSystemZISelDAGToDAG.cpp845 case ISD::ANY_EXTEND:
965 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND &&
1071 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND &&
1864 Result = CurDAG->getNode(ISD::ANY_EXTEND, DL, VT, Result);
H A DSystemZISelLowering.cpp1308 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
3071 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
3289 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
3756 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op);
4671 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
4673 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
4675 Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
4676 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
5622 if (N0.hasOneUse() && N0.getOpcode() == ISD::ANY_EXTEND)
5651 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLo
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp425 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
861 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
862 SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
872 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
873 SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
1035 // conversion is unnecessary and can be replaced with an ANY_EXTEND
1039 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0.getOperand(0));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp878 case ISD::ANY_EXTEND:
886 unsigned NewOpc = N->getOpcode() == ISD::ANY_EXTEND
1686 // FIXME: Generalize this to other ANY_EXTEND than i32 to i64?
1688 if (Shift.getOpcode() == ISD::ANY_EXTEND && Shift.hasOneUse() &&
1715 SDValue NewX = DAG.getNode(ISD::ANY_EXTEND, DL, VT, X);
1804 if (X.getOpcode() == ISD::ANY_EXTEND) {
1823 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
2109 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
3438 NBits = CurDAG->getNode(ISD::ANY_EXTEND, DL, NVT, NBits);
3495 Control = CurDAG->getNode(ISD::ANY_EXTEND, D
[all...]
H A DX86ISelLowering.cpp809 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
1237 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1412 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1516 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1517 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1522 setOperationAction(ISD::ANY_EXTEND, MVT::v8i8, Custom);
1761 setOperationAction(ISD::ANY_EXTEND, MVT::v32i8, Custom);
1774 setOperationAction(ISD::ANY_EXTEND, MVT::v64i8, Custom);
1792 setOperationAction(ISD::ANY_EXTEND, MVT::v32i16, Custom);
2012 setTargetDAGCombine(ISD::ANY_EXTEND);
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1529 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
1614 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
2217 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
2218 Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2);
2388 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
2706 RetVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, RetVal);
4480 // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
4481 if (Val.getOpcode() == ISD::ANY_EXTEND) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp101 setOperationAction(ISD::ANY_EXTEND, T, Custom);
134 setOperationAction(ISD::ANY_EXTEND, T, Custom);
1570 case ISD::ANY_EXTEND: return LowerHvxAnyExt(Op, DAG);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp343 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp279 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp644 setTargetDAGCombine(ISD::ANY_EXTEND);
801 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
2729 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
3034 Scalar = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Scalar);
4079 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
4083 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
12100 if (Op->getOpcode() == ISD::ANY_EXTEND &&
12395 Offset = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::nxv2i64, Offset).getValue(0);
12416 SrcNew = DAG.getNode(ISD::ANY_EXTEND, DL, HwSrcVt, Src);
12455 Offset = DAG.getNode(ISD::ANY_EXTEND, D
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp582 setOperationAction(ISD::ANY_EXTEND, MVT::v2i32, Expand);
587 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Expand);
2339 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2809 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
4351 LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS);
4352 RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS);
5009 SDValue ExtLo = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Lo);
7245 SDValue BufferStoreExt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Ops[1]);
7266 return DAG.getNode(ISD::ANY_EXTEND, SL, VT, Op);
9557 Opc == ISD::ANY_EXTEND || Op
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp843 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1247 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1477 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1488 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {

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