Searched refs:divider (Results 76 - 100 of 147) sorted by path

123456

/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_display.c149 int divider; local
152 divider = val & CCK_FREQUENCY_VALUES;
155 (divider << CCK_FREQUENCY_STATUS_SHIFT),
158 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
3742 * The PLL needs to be enabled with a valid divider
H A Dintel_dpll_mgr.c1497 unsigned int p; /* chosen divider */
1507 unsigned int divider)
1521 ctx->p = divider;
1529 ctx->p = divider;
1700 * have found the definitive divider, we can't
1710 * If a solution is found with an even divider, prefer
1764 drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
2596 * Program half of the nominal DCO divider fraction value.
1504 skl_wrpll_try_divider(struct skl_wrpll_context *ctx, u64 central_freq, u64 dco_freq, unsigned int divider) argument
H A Dintel_lvds.c65 int divider; member in struct:intel_lvds_pps
176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
202 "divider %d port %d powerdown_on_reset %d\n",
204 pps->divider, pps->port, pps->powerdown_on_reset);
229 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
H A Dvlv_dsi.c955 * On Broxton the PLL needs to be enabled with a valid divider
1201 /* return txclkesc cycles in terms of divider and duration in us */
1202 static u16 txclkesc(u32 divider, unsigned int us) argument
1204 switch (divider) {
1330 * escape clock divider, 20MHz, shared for A and C.
/linux-master/drivers/gpu/drm/kmb/
H A Dkmb_dsi.c94 u32 divider; member in struct:vco_params
885 .divider = 1,
961 t_freq = target_freq_mhz * vco_p.divider;
/linux-master/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_10nm.c118 u64 divider; local
125 divider = fref * 2;
128 dec_multiple = div_u64(pll_freq * multiplier, divider);
570 * The post dividers and mux clocks are created using the standard divider and
572 * state to follow the master PLL's divider/mux state. Therefore, we don't
H A Ddsi_phy_7nm.c114 u64 divider; local
121 divider = fref * 2;
124 dec_multiple = div_u64(pll_freq * multiplier, divider);
619 * The post dividers and mux clocks are created using the standard divider and
621 * state to follow the master PLL's divider/mux state. Therefore, we don't
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk20a.c92 u32 divider; local
95 divider = pll->m * clk->pl_to_div(pll->pl);
97 return rate / divider / 2;
305 /* split VCO-to-bypass jump in half by setting out divider 1:2 */
308 /* Intentional 2nd write to assure linear divider operation */
322 /* restore out divider 1:1 */
326 /* Intentional 2nd write to assure linear divider operation */
/linux-master/drivers/gpu/drm/radeon/
H A Dr600_dpm.c477 u32 index, u32 divider)
480 STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK);
484 u32 index, u32 divider)
487 STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK);
491 u32 index, u32 divider)
494 STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK);
476 r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
483 r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
490 r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
H A Dr600_dpm.h180 u32 index, u32 divider);
182 u32 index, u32 divider);
184 u32 index, u32 divider);
H A Dradeon_legacy_crtc.c754 int divider; member in struct:__anon1219
822 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
823 if (post_div->divider == post_divider)
827 if (!post_div->divider)
929 This appears to related to the PLL divider registers (fail to lock?).
975 /* R300 uses ref_div_acc field as real ref divider */
H A Dsumo_dpm.c472 u32 index, u32 divider)
479 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
482 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
485 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
488 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
492 u32 index, u32 divider)
500 dpm_ctrl |= (divider << (index * 3));
506 u32 index, u32 divider)
514 dpm_ctrl |= (divider << (index * 3));
471 sumo_set_divider_value(struct radeon_device *rdev, u32 index, u32 divider) argument
491 sumo_set_ds_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument
505 sumo_set_ss_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument
H A Dtrinity_dpm.c565 u32 index, u32 divider)
572 value |= DS_DIV(divider);
577 u32 index, u32 divider)
584 value |= DS_SH_DIV(divider);
1784 u32 divider; local
1787 divider = did * 25;
1789 divider = (did - 64) * 50 + 1600;
1791 divider = (did - 96) * 100 + 3200;
1793 divider = 128 * 100;
1797 return ((pi->sys_info.dentist_vco_freq * 100) + (divider
564 trinity_set_ds_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument
576 trinity_set_ss_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument
[all...]
/linux-master/drivers/gpu/drm/vc4/
H A Dvc4_dsi.c575 u32 divider; member in struct:vc4_dsi
826 * DSI PLL divider.
830 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
831 * the pixel clock), only has an integer divider off of DSI.
846 unsigned long pll_clock = pixel_clock_hz * dsi->divider;
847 int divider; local
849 /* Find what divider gets us a faster clock than the requested
852 for (divider = 1; divider < 255; divider
[all...]
/linux-master/drivers/hwmon/
H A Dbt1-pvt.h227 * @divider: distributed divider per each degree.
228 * @divider_leftover: divider leftover, which couldn't be redistributed.
233 long divider; member in struct:pvt_poly_term
239 * @total_divider: total data divider.
H A Dltc4282.c1350 const char *divider; local
1464 &divider);
1467 ARRAY_SIZE(ltc4282_dividers), divider);
1470 "Invalid val(%s) for adi,overvoltage-divider\n",
1471 divider);
1479 &divider);
1482 ARRAY_SIZE(ltc4282_dividers), divider);
1485 "Invalid val(%s) for adi,undervoltage-divider\n",
1486 divider);
H A Dmlxreg-fan.c45 * RPM = 15000000 * 100 / ((Regval + samples) * divider).
103 * @divider: divider value for tachometer RPM calculation;
113 int divider; member in struct:mlxreg_fan
164 *val = MLXREG_FAN_GET_RPM(regval, fan->divider,
436 * Set divider value according to the capability register, in case it
442 fan->divider = regval * MLXREG_FAN_TACHO_DIV_MIN;
456 fan->divider = MLXREG_FAN_TACHO_DIV_DEF;
519 fan->divider = data->bit;
/linux-master/drivers/i2c/busses/
H A Di2c-bcm2835.c93 u32 divider = DIV_ROUND_UP(parent_rate, rate); local
98 * if the LSB is set, increment the divider to avoid any issue.
100 if (divider & 1)
101 divider++;
102 if ((divider < BCM2835_I2C_CDIV_MIN) ||
103 (divider > BCM2835_I2C_CDIV_MAX))
106 return divider;
114 u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate); local
116 if (divider == -EINVAL)
119 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider);
143 u32 divider = clk_bcm2835_i2c_calc_divider(rate, *parent_rate); local
152 u32 divider = bcm2835_i2c_readl(div->i2c_dev, BCM2835_I2C_DIV); local
[all...]
H A Di2c-mpc.c105 u16 divider; member in struct:mpc_i2c_divider
158 * 1. Set up the frequency divider and sampling rate.
244 u32 divider; local
253 /* Determine divider value */
254 divider = mpc5xxx_fwnode_get_bus_frequency(fwnode) / clock;
265 if (div->divider >= divider)
269 *real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / div->divider;
428 u32 divider; local
437 divider
[all...]
H A Di2c-mxs.c702 uint32_t divider; local
707 divider = DIV_ROUND_UP(clk, speed);
709 if (divider < 25) {
711 * limit the divider, so that min(low_count, high_count)
714 divider = 25;
718 clk / divider / 1000, clk / divider % 1000);
719 } else if (divider > 1897) {
721 * limit the divider, so that max(low_count, high_count)
724 divider
[all...]
/linux-master/drivers/iio/adc/
H A Dcpcap-adc.c171 * @divider: divider in the phasing table
178 unsigned short divider; member in struct:cpcap_adc_phasing_tbl
190 * @divider: conversion divider
198 int divider; member in struct:cpcap_adc_conversion_tbl
687 if (phase_tbl[index].divider == 0)
689 req->result /= phase_tbl[index].divider;
699 if (phase_tbl[index].divider == 0)
701 req->result /= phase_tbl[index].divider;
[all...]
H A Dstm32-dfsdm-core.c96 unsigned int spi_clk_out_div; /* SPI clkout divider value */
227 unsigned long clk_freq, divider; local
269 divider = div_u64_rem(clk_freq, spi_freq, &rem);
270 /* Round up divider when ckout isn't precise, not to exceed spi_freq */
272 divider++;
274 /* programmable divider is in range of [2:256] */
275 if (divider < 2 || divider > 256) {
280 /* SPI clock output divider is: divider
[all...]
/linux-master/drivers/iio/chemical/
H A Dsgp40.c104 u32 factorial, divider, xmax; local
120 divider = 0;
125 y += (xp >> divider) / factorial;
126 divider += power;
130 divider -= power;
/linux-master/drivers/iio/frequency/
H A Dadmv4420.c97 u32 divider; member in struct:admv4420_reference_block
216 return (tmp / (st->ref_block.divider * divide_by_2));
228 for (st->ref_block.divider = 1; st->ref_block.divider < MAX_R_DIVIDER;
229 st->ref_block.divider++) {
314 FIELD_GET(0xFF, st->ref_block.divider));
319 FIELD_GET(0xFF00, st->ref_block.divider));
/linux-master/drivers/iio/imu/inv_mpu6050/
H A Dinv_mpu_aux.c49 d = st->chip_config.divider;
59 regmap_write(st->map, st->reg->sample_rate_div, st->chip_config.divider);

Completed in 369 milliseconds

123456