1/* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef __R600_DPM_H__ 24#define __R600_DPM_H__ 25 26#include "radeon.h" 27 28#define R600_ASI_DFLT 10000 29#define R600_BSP_DFLT 0x41EB 30#define R600_BSU_DFLT 0x2 31#define R600_AH_DFLT 5 32#define R600_RLP_DFLT 25 33#define R600_RMP_DFLT 65 34#define R600_LHP_DFLT 40 35#define R600_LMP_DFLT 15 36#define R600_TD_DFLT 0 37#define R600_UTC_DFLT_00 0x24 38#define R600_UTC_DFLT_01 0x22 39#define R600_UTC_DFLT_02 0x22 40#define R600_UTC_DFLT_03 0x22 41#define R600_UTC_DFLT_04 0x22 42#define R600_UTC_DFLT_05 0x22 43#define R600_UTC_DFLT_06 0x22 44#define R600_UTC_DFLT_07 0x22 45#define R600_UTC_DFLT_08 0x22 46#define R600_UTC_DFLT_09 0x22 47#define R600_UTC_DFLT_10 0x22 48#define R600_UTC_DFLT_11 0x22 49#define R600_UTC_DFLT_12 0x22 50#define R600_UTC_DFLT_13 0x22 51#define R600_UTC_DFLT_14 0x22 52#define R600_DTC_DFLT_00 0x24 53#define R600_DTC_DFLT_01 0x22 54#define R600_DTC_DFLT_02 0x22 55#define R600_DTC_DFLT_03 0x22 56#define R600_DTC_DFLT_04 0x22 57#define R600_DTC_DFLT_05 0x22 58#define R600_DTC_DFLT_06 0x22 59#define R600_DTC_DFLT_07 0x22 60#define R600_DTC_DFLT_08 0x22 61#define R600_DTC_DFLT_09 0x22 62#define R600_DTC_DFLT_10 0x22 63#define R600_DTC_DFLT_11 0x22 64#define R600_DTC_DFLT_12 0x22 65#define R600_DTC_DFLT_13 0x22 66#define R600_DTC_DFLT_14 0x22 67#define R600_VRC_DFLT 0x0000C003 68#define R600_VOLTAGERESPONSETIME_DFLT 1000 69#define R600_BACKBIASRESPONSETIME_DFLT 1000 70#define R600_VRU_DFLT 0x3 71#define R600_SPLLSTEPTIME_DFLT 0x1000 72#define R600_SPLLSTEPUNIT_DFLT 0x3 73#define R600_TPU_DFLT 0 74#define R600_TPC_DFLT 0x200 75#define R600_SSTU_DFLT 0 76#define R600_SST_DFLT 0x00C8 77#define R600_GICST_DFLT 0x200 78#define R600_FCT_DFLT 0x0400 79#define R600_FCTU_DFLT 0 80#define R600_CTXCGTT3DRPHC_DFLT 0x20 81#define R600_CTXCGTT3DRSDC_DFLT 0x40 82#define R600_VDDC3DOORPHC_DFLT 0x100 83#define R600_VDDC3DOORSDC_DFLT 0x7 84#define R600_VDDC3DOORSU_DFLT 0 85#define R600_MPLLLOCKTIME_DFLT 100 86#define R600_MPLLRESETTIME_DFLT 150 87#define R600_VCOSTEPPCT_DFLT 20 88#define R600_ENDINGVCOSTEPPCT_DFLT 5 89#define R600_REFERENCEDIVIDER_DFLT 4 90 91#define R600_PM_NUMBER_OF_TC 15 92#define R600_PM_NUMBER_OF_SCLKS 20 93#define R600_PM_NUMBER_OF_MCLKS 4 94#define R600_PM_NUMBER_OF_VOLTAGE_LEVELS 4 95#define R600_PM_NUMBER_OF_ACTIVITY_LEVELS 3 96 97/* XXX are these ok? */ 98#define R600_TEMP_RANGE_MIN (90 * 1000) 99#define R600_TEMP_RANGE_MAX (120 * 1000) 100 101#define FDO_PWM_MODE_STATIC 1 102#define FDO_PWM_MODE_STATIC_RPM 5 103 104enum r600_power_level { 105 R600_POWER_LEVEL_LOW = 0, 106 R600_POWER_LEVEL_MEDIUM = 1, 107 R600_POWER_LEVEL_HIGH = 2, 108 R600_POWER_LEVEL_CTXSW = 3, 109}; 110 111enum r600_td { 112 R600_TD_AUTO, 113 R600_TD_UP, 114 R600_TD_DOWN, 115}; 116 117enum r600_display_watermark { 118 R600_DISPLAY_WATERMARK_LOW = 0, 119 R600_DISPLAY_WATERMARK_HIGH = 1, 120}; 121 122enum r600_display_gap { 123 R600_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, 124 R600_PM_DISPLAY_GAP_VBLANK = 1, 125 R600_PM_DISPLAY_GAP_WATERMARK = 2, 126 R600_PM_DISPLAY_GAP_IGNORE = 3, 127}; 128 129extern const u32 r600_utc[R600_PM_NUMBER_OF_TC]; 130extern const u32 r600_dtc[R600_PM_NUMBER_OF_TC]; 131 132void r600_dpm_print_class_info(u32 class, u32 class2); 133void r600_dpm_print_cap_info(u32 caps); 134void r600_dpm_print_ps_status(struct radeon_device *rdev, 135 struct radeon_ps *rps); 136u32 r600_dpm_get_vblank_time(struct radeon_device *rdev); 137u32 r600_dpm_get_vrefresh(struct radeon_device *rdev); 138bool r600_is_uvd_state(u32 class, u32 class2); 139void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, 140 u32 *p, u32 *u); 141int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th); 142void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable); 143void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable); 144void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable); 145void r600_enable_acpi_pm(struct radeon_device *rdev); 146void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable); 147bool r600_dynamicpm_enabled(struct radeon_device *rdev); 148void r600_enable_sclk_control(struct radeon_device *rdev, bool enable); 149void r600_enable_mclk_control(struct radeon_device *rdev, bool enable); 150void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable); 151void r600_wait_for_spll_change(struct radeon_device *rdev); 152void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p); 153void r600_set_at(struct radeon_device *rdev, 154 u32 l_to_m, u32 m_to_h, 155 u32 h_to_m, u32 m_to_l); 156void r600_set_tc(struct radeon_device *rdev, u32 index, u32 u_t, u32 d_t); 157void r600_select_td(struct radeon_device *rdev, enum r600_td td); 158void r600_set_vrc(struct radeon_device *rdev, u32 vrv); 159void r600_set_tpu(struct radeon_device *rdev, u32 u); 160void r600_set_tpc(struct radeon_device *rdev, u32 c); 161void r600_set_sstu(struct radeon_device *rdev, u32 u); 162void r600_set_sst(struct radeon_device *rdev, u32 t); 163void r600_set_git(struct radeon_device *rdev, u32 t); 164void r600_set_fctu(struct radeon_device *rdev, u32 u); 165void r600_set_fct(struct radeon_device *rdev, u32 t); 166void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p); 167void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s); 168void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u); 169void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p); 170void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s); 171void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time); 172void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time); 173void r600_engine_clock_entry_enable(struct radeon_device *rdev, 174 u32 index, bool enable); 175void r600_engine_clock_entry_enable_pulse_skipping(struct radeon_device *rdev, 176 u32 index, bool enable); 177void r600_engine_clock_entry_enable_post_divider(struct radeon_device *rdev, 178 u32 index, bool enable); 179void r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev, 180 u32 index, u32 divider); 181void r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev, 182 u32 index, u32 divider); 183void r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev, 184 u32 index, u32 divider); 185void r600_engine_clock_entry_set_step_time(struct radeon_device *rdev, 186 u32 index, u32 step_time); 187void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u); 188void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u); 189void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt); 190void r600_voltage_control_enable_pins(struct radeon_device *rdev, 191 u64 mask); 192void r600_voltage_control_program_voltages(struct radeon_device *rdev, 193 enum r600_power_level index, u64 pins); 194void r600_voltage_control_deactivate_static_control(struct radeon_device *rdev, 195 u64 mask); 196void r600_power_level_enable(struct radeon_device *rdev, 197 enum r600_power_level index, bool enable); 198void r600_power_level_set_voltage_index(struct radeon_device *rdev, 199 enum r600_power_level index, u32 voltage_index); 200void r600_power_level_set_mem_clock_index(struct radeon_device *rdev, 201 enum r600_power_level index, u32 mem_clock_index); 202void r600_power_level_set_eng_clock_index(struct radeon_device *rdev, 203 enum r600_power_level index, u32 eng_clock_index); 204void r600_power_level_set_watermark_id(struct radeon_device *rdev, 205 enum r600_power_level index, 206 enum r600_display_watermark watermark_id); 207void r600_power_level_set_pcie_gen2(struct radeon_device *rdev, 208 enum r600_power_level index, bool compatible); 209enum r600_power_level r600_power_level_get_current_index(struct radeon_device *rdev); 210enum r600_power_level r600_power_level_get_target_index(struct radeon_device *rdev); 211void r600_power_level_set_enter_index(struct radeon_device *rdev, 212 enum r600_power_level index); 213void r600_wait_for_power_level_unequal(struct radeon_device *rdev, 214 enum r600_power_level index); 215void r600_wait_for_power_level(struct radeon_device *rdev, 216 enum r600_power_level index); 217void r600_start_dpm(struct radeon_device *rdev); 218void r600_stop_dpm(struct radeon_device *rdev); 219 220bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor); 221 222int r600_get_platform_caps(struct radeon_device *rdev); 223 224int r600_parse_extended_power_table(struct radeon_device *rdev); 225void r600_free_extended_power_table(struct radeon_device *rdev); 226 227enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev, 228 u32 sys_mask, 229 enum radeon_pcie_gen asic_gen, 230 enum radeon_pcie_gen default_gen); 231 232u16 r600_get_pcie_lane_support(struct radeon_device *rdev, 233 u16 asic_lanes, 234 u16 default_lanes); 235u8 r600_encode_pci_lane_width(u32 lanes); 236 237#endif 238