/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | vega12_hwmgr.c | 430 data->total_active_cus = adev->gfx.cu_info.number;
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H A D | vega10_hwmgr.c | 914 data->total_active_cus = adev->gfx.cu_info.number; 1258 "Incorrect number of PCIE States from VBIOS!", 4999 /* If the two states don't even have the same number of performance levels
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/linux-master/drivers/gpu/drm/amd/display/dc/bios/ |
H A D | bios_parser.c | 192 uint32_t number; local 207 number = get_src_obj_list(bp, object, &id); 209 if (number <= index) 917 * @index: number of entries that match the converted info index 1079 * if the pointer to info is NULL, indicate the caller what to know the number 1560 * return: number of SS Entry that match the signal 1612 * return: number of SS Entry that match the id 1623 uint32_t number = 0; local 1629 return number; 1639 return number; 1746 uint32_t number = 0; local 2008 uint8_t *number; local [all...] |
/linux-master/drivers/gpu/drm/amd/amdkfd/ |
H A D | kfd_mqd_manager.c | 112 cu_active_per_node = cu_info->number / mm->dev->kfd->num_nodes;
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H A D | kfd_chardev.c | 775 /* Return number of nodes, so that user space can alloacate 1330 pdev->bus->number,
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfx_v9_4_3.c | 3068 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3846 /* no need to select if instance number is 1 */ 3876 /* no need to select if instance number is 1 */ 3914 /* no need to select if instance number is 1 */ 3936 /* no need to select if instance number is 1 */ 4251 cu_info->number = active_cu_number;
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H A D | gfx_v9_4_2.c | 522 adev->gfx.cu_info.number, 532 adev->gfx.cu_info.number * SIMD_ID_MAX * 2, 547 adev->gfx.cu_info.number * 2, 556 pattern[1], adev->gfx.cu_info.number * SIMD_ID_MAX * 6, 587 adev->gfx.cu_info.number, 597 adev->gfx.cu_info.number * SIMD_ID_MAX * 4, 665 adev->gfx.cu_info.number, 682 adev->gfx.cu_info.number * SIMD_ID_MAX,
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H A D | gfx_v9_0.c | 6823 * number of gfx waves. Setting 5 bit will make sure gfx only gets 7256 cu_info->number = active_cu_number;
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H A D | gfx_v8_0.c | 6843 * number of gfx waves. Setting 5 bit will make sure gfx only gets 7132 cu_info->number = active_cu_number;
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H A D | gfx_v7_0.c | 1883 * registers, maximum number of quad pipes, render backends... 2109 * @seq: sequence number 2112 * Emits a fence sequence number on the gfx ring and flushes 2152 * @seq: sequence number 2155 * Emits a fence sequence number on the compute ring and flushes 3170 * @vmid: vmid number to use 3791 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 5143 cu_info->number = active_cu_number;
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H A D | gfx_v6_0.c | 2751 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 3602 cu_info->number = active_cu_number;
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H A D | gfx_v11_0.c | 6483 cu_info->number = active_cu_number;
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H A D | gfx_v10_0.c | 9642 cu_info->number = active_cu_number;
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H A D | amdgpu_kms.c | 884 dev_info->cu_active_number = adev->gfx.cu_info.number;
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H A D | amdgpu_gfx.h | 252 /* total active CU number */ 253 uint32_t number; member in struct:amdgpu_cu_info
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H A D | amdgpu_drv.c | 452 * Override the max number of jobs supported in the sw queue. The default is 32. 454 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 459 * Override the max number of HW submissions. The default is 2. 461 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 530 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 730 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 731 * number of VMIDs assigned to the HWS, which is also the default. 750 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 756 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 933 * result in the GPU entering bad status when the number o [all...] |
H A D | amdgpu_device.c | 152 * The amdgpu driver provides a sysfs API for reporting the total number 155 * number of replays as a sum of the NAKs generated and NAKs received 1790 * The vm block size defines number of bits in page table versus page directory, 1796 /* defines number of bits in page table versus page directory, 2265 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, 2282 * the user and configues the virtual display configuration (number of 4317 adev->gfx.cu_info.number); 5574 adev->pdev->bus->number, 1); 5599 adev->pdev->bus->number, 1);
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/linux-master/arch/powerpc/xmon/ |
H A D | xmon.c | 225 c# try to switch to cpu number h (in hex)\n\ 1033 printf("Invalid number.\n"); 1509 "bc <n/addr> clear breakpoint number n or at addr\n" 1602 /* assume a breakpoint number */ 3898 printf("Unsupported TLB number !\n"); 4130 if (spu->number >= XMON_NUM_SPUS) { 4135 spu_info[spu->number].spu = spu; 4136 spu_info[spu->number].stopped_ok = 0; 4137 spu_info[spu->number].dump_addr = (unsigned long) 4138 spu_info[spu->number] [all...] |
/linux-master/arch/powerpc/platforms/pseries/ |
H A D | pci.c | 70 pdev->bus->number, 128 max_vfs = of_get_property(dn, "ibm,number-of-configurable-vfs", NULL); 229 if (dev->bus->number == 0 && dev->devfn == 0x81 &&
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H A D | lpar.c | 164 * This represents the number of cpus in the hypervisor. Since there is no 165 * architected way to discover the number of processors in the host, we 1086 * is the number of entries yet to process. 1349 static void do_block_remove(unsigned long number, struct ppc64_tlb_batch *batch, argument 1361 for (i = 0; i < number; i++) { 1474 * maximum it will be the number of possible page sizes *2 + 10 bytes. 1525 static void pSeries_lpar_flush_hash_range(unsigned long number, int local) argument 1541 do_block_remove(number, batch, param); 1548 for (i = 0; i < number; i++) {
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/linux-master/arch/powerpc/platforms/powernv/ |
H A D | pci-sriov.c | 26 * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs 36 * NB: $PE_COUNT is the number of PEs that the PHB supports. 48 * new_size = per-vf-size * number-of-PEs 58 * based on the maximum number of VFs supported by the device and we need 92 * PE number. This is handled in pnv_pci_vf_resource_shift(). 112 * 2) The number of MBT entries that we have is limited. PHB3 and PHB4 only 176 * number of VFs we can support. 353 * communicate the number of segments we want on a BAR. This wasn't 519 * address are the PE number [all...] |
/linux-master/arch/powerpc/platforms/maple/ |
H A D | pci.c | 127 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); 158 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); 264 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0)) 270 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 302 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0)) 308 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 382 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 413 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 442 /* On G5, we move AGP up to high bus number so we don't need 526 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number [all...] |
/linux-master/arch/powerpc/platforms/cell/spufs/ |
H A D | file.c | 1875 num = ctx->spu->number; 2465 p->spu_id = spu ? spu->number : -1; 2502 ctx->spu ? ctx->spu->number : -1,
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/linux-master/arch/powerpc/kvm/ |
H A D | book3s_xive.c | 314 pr_warn("XIVE: Weird guest interrupt number 0x%08x\n", hirq); 1040 /* Calculate max number of interrupts in that queue. */ 1225 prio, state->number); 1625 state->act_priority, state->number); 1708 state->act_priority, state->number); 2288 sb->irq_state[i].number = (bid << KVMPPC_XICS_ICS_SHIFT) | i; 2481 /* Increment the number of valid sources and mark this one valid */ 2765 /* KVM_MAX_VCPUS limits the number of VMs to roughly 64 per sockets 2865 seq_printf(m, "%08x %08x/%02x", state->number, hw_num,
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/linux-master/arch/arm64/kvm/ |
H A D | arm.c | 195 /* The maximum number of VCPUs is limited by the host's GIC model */ 360 * (bump this number if adding more devices) 1286 static int vcpu_interrupt_line(struct kvm_vcpu *vcpu, int number, bool level) argument 1292 if (number == KVM_ARM_IRQ_CPU_IRQ) 2055 * EL2 vectors can be mapped and rerouted in a number of ways,
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