#
56f7d2ac |
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18-Dec-2023 |
Victor Lu <victorchengchi.lu@amd.com> |
drm/amdgpu: Do not program SQ_TIMEOUT_CONFIG in SRIOV VF should not program this register. Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Zhigang Luo <Zhigang.Luo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4acd31e6 |
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18-Feb-2024 |
Ma Jun <Jun.Ma2@amd.com> |
drm/amdgpu: Drop redundant parameter in amdgpu_gfx_kiq_init_ring Drop redundant parameters in function amdgpu_gfx_kiq_init_ring to simplify the code Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b5387349 |
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11-Jan-2024 |
YuanShang <YuanShang.Mao@amd.com> |
drm/amd/amdgpu: Update RLC_SPM_MC_CNT by ring wreg in guest Submit command of wreg in GFX and COMPUTE ring to update RLC_SPM_MC_CNT in guest machine during runtime. Signed-off-by: YuanShang <YuanShang.Mao@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0f3cd24e |
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15-Nov-2023 |
Yang Wang <kevinyang.wang@amd.com> |
drm/amdgpu: add gfx v9.4.3 ACA support v1: add gfx v9.4.3 ACA driver support v2: use macro to define smn address value. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9f91e983 |
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12-Dec-2023 |
YiPeng Chai <YiPeng.Chai@amd.com> |
drm/amdgpu: MCA supports recording umc address information MCA supports recording umc address information. V2: Move err_addr variable from struct ras_err_node to struct ras_err_info. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
88f4b10a |
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20-Nov-2023 |
Tim Huang <Tim.Huang@amd.com> |
drm/amdgpu: fix memory overflow in the IB test Fix a memory overflow issue in the gfx IB test for some ASICs. At least 20 bytes are needed for the IB test packet. v2: correct code indentation errors. (Christian) Signed-off-by: Tim Huang <Tim.Huang@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
702e2fb5 |
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19-Nov-2023 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Retire query/reset_ras_err_status from gfx_v9_4_3 Not needed anymore. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Stanley Yang <Stanley.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6b0b7789 |
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20-Nov-2023 |
Tim Huang <Tim.Huang@amd.com> |
drm/amdgpu: fix memory overflow in the IB test Fix a memory overflow issue in the gfx IB test for some ASICs. At least 20 bytes are needed for the IB test packet. v2: correct code indentation errors. (Christian) Signed-off-by: Tim Huang <Tim.Huang@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
85150626 |
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03-Oct-2023 |
Victor Lu <victorchengchi.lu@amd.com> |
drm/amdgpu: Use correct KIQ MEC engine for gfx9.4.3 (v5) amdgpu_kiq_wreg/rreg is hardcoded to use MEC engine 0. Add an xcc_id parameter to amdgpu_kiq_wreg/rreg, define W/RREG32_XCC and amdgpu_device_xcc_wreg/rreg to use the new xcc_id parameter. Using amdgpu_sriov_runtime to determine whether to access via kiq or RLC is sufficient for now. v5: add condition in amdgpu_device_xcc_w/rreg, remove trace func call v4: avoid using amdgpu_sriov_w/rreg v3: use W/RREG32_XCC to handle non-kiq case v2: define amdgpu_device_xcc_wreg/rreg instead of changing parameters of amdgpu_device_wreg/rreg Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f64c3fce |
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08-Aug-2023 |
Victor Lu <victorchengchi.lu@amd.com> |
drm/amdgpu: Add flag to enable indirect RLCG access for gfx v9.4.3 The "rlcg_reg_access_supported" flag is missing. Add it back in. Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4eaa007c |
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30-Oct-2023 |
Yang Wang <kevinyang.wang@amd.com> |
drm/amdgpu: correct amdgpu ip block rev info correct following amdgpu ip block version information: - gfx_v9_4_3 - sdma_v4_4_2 Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
61fe5536 |
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30-Oct-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: handle extra UE register entries for gfx v9_4_3 The UE registe list is larger than CE list. Reported-by: yipeng.chai@amd.com Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3f69d586 |
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19-Oct-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add a read to GFX v9.4.3 ring test Issue a read to confirm the register write before ringing doorbell. With multiple XCCs there is chance for race condition. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d9443ac4 |
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17-Oct-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: drop status query/reset for GCEA 9.4.3 and MMEA 1.8 PMFW will be responsible for them. v2: remove query interfaces. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2d955a06 |
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11-Oct-2023 |
Mangesh Gadre <Mangesh.Gadre@amd.com> |
Revert "drm/amdgpu: Program xcp_ctl registers as needed" This reverts commit 0bdebfef3fb2b6291000765eaa9c6c8030293fce. XCP_CTL register is programmed by firmware and register access is protected. Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
156c2814 |
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26-Sep-2023 |
Yang Wang <kevinyang.wang@amd.com> |
drm/amdgpu: add RAS error info support for gfx_v9_4_3 add RAS error info support for gfx_v9_4_3. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4e8303cf |
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11-Sep-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use function for IP version check Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f705a6f0 |
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25-Aug-2023 |
Mukul Joshi <mukul.joshi@amd.com> |
drm/amdgpu: Store CU info from all XCCs for GFX v9.4.3 Currently, we store CU info only for a single XCC assuming that it is the same for all XCCs. However, that may not be true. As a result, store CU info for all XCCs. This info is later used for CU masking. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c2c23a10 |
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06-Sep-2023 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Correct se_num and reg_inst for gfx v9_4_3 ras counters gfx_v9_4_3_ue|ce_reg_list is an array per gfx core instance correct the settings of se_num and reg_inst for some of gfx ras counters so all the available register instances can be polled for ras status. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d30279a9 |
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24-Aug-2023 |
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> |
drm/amdgpu: Hide xcp partition sysfs under SRIOV XCP partitions should not be visible for the VF for GFXIP 9.4.3. Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ac3343c7 |
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25-Aug-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: use read-modify-write mode for gfx v9_4_3 SQ setting Instead of using direct update, avoid touching unrelated fields. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7caebc8f |
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21-Aug-2023 |
Mangesh Gadre <Mangesh.Gadre@amd.com> |
drm/amdgpu: Updated TCP/UTCL1 programming Update TCP/UTCL1 thrashing control settings v2: updated rev_id check Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
55925936 |
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15-Aug-2023 |
Mangesh Gadre <Mangesh.Gadre@amd.com> |
drm/amdgpu: Remove SRAM clock gater override by driver rlc firmware does required setting, driver need not do it. Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
97e3c6a8 |
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25-Aug-2023 |
Mukul Joshi <mukul.joshi@amd.com> |
drm/amdgpu: Store CU info from all XCCs for GFX v9.4.3 Currently, we store CU info only for a single XCC assuming that it is the same for all XCCs. However, that may not be true. As a result, store CU info for all XCCs. This info is later used for CU masking. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2031c46b |
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24-Aug-2023 |
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> |
drm/amdgpu: Hide xcp partition sysfs under SRIOV XCP partitions should not be visible for the VF for GFXIP 9.4.3. Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e23b1067 |
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25-Aug-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: use read-modify-write mode for gfx v9_4_3 SQ setting Instead of using direct update, avoid touching unrelated fields. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7b9f6235 |
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21-Aug-2023 |
Mangesh Gadre <Mangesh.Gadre@amd.com> |
drm/amdgpu: Updated TCP/UTCL1 programming Update TCP/UTCL1 thrashing control settings v2: updated rev_id check Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3f160967 |
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15-Aug-2023 |
Mangesh Gadre <Mangesh.Gadre@amd.com> |
drm/amdgpu: Remove SRAM clock gater override by driver rlc firmware does required setting, driver need not do it. Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b5cdaded |
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14-Aug-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Remove gfxoff check in GFX v9.4.3 GFXOFF feature is not there for GFX 9.4.3 ASICs. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
952ee945 |
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25-Jul-2023 |
Eric Huang <jinhuieric.huang@amd.com> |
drm/amdgpu: enable trap of each kfd vmid for gfx v9.4.3 To setup ttmp on as default for gfx v9.4.3 in IP hw init. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b5ac0880 |
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24-Jul-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Restore HQD persistent state register On GFX v9.4.3, compute queue MQD is populated using the values in HQD persistent state register. Hence don't clear the values on module unload, instead restore it to the default reset value so that MQD is initialized correctly during next module load. In particular, preload flag needs to be set on compute queue MQD, otherwise it could cause uninitialized values being used at device reset state resulting in EDC. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9bc12db4 |
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20-Jul-2023 |
Shiwu Zhang <shiwu.zhang@amd.com> |
drm/amdgpu: fix the indexing issue during rlcg access ctrl init In case that the GET_INST() is used for looping, only loops for the times of actual num of xcc, otherwise GET_INST() will return the invalid index, a.k.a -1 And also remove the redundant mask checking in case of GET_INST() Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0bdebfef |
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19-Jul-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Program xcp_ctl registers as needed XCP_CTL register is expected to be programmed by firmware. Under certain conditions FW may not have programmed it correctly. As a workaround, program it when FW has not programmed the right values. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8ed49dd1 |
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16-Jun-2023 |
Victor Lu <victorchengchi.lu@amd.com> |
drm/amdgpu: Add RLCG interface driver implementation for gfx v9.4.3 (v3) Add RLCG interface support for gfx v9.4.3 and multiple XCCs. Do not enable it yet. v2: Fix amdgpu_rlcg_reg_access_ctrl init, add support for multiple XCCs in amdgpu_mm_wreg_mmio_rlc v3: Use GET_INST() when indexing amdgpu_rlcg_reg_access_ctrl Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bd974498 |
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29-Mar-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add watchdog timer enablement for gfx_v9_4_3 Configure SQ watchdog timer setting. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
67769b7c |
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04-Jul-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Remove redundant GFX v9.4.3 sequence Programming of XCC id is already taken care with partition mode change. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4755bfbd |
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03-Jul-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Change golden settings for GFX v9.4.3 Change the settings applicable for A0. GRBM_MCM_ADDR setting will be applied by firmware. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Acked-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Tested-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bc1688fc |
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24-Jul-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Restore HQD persistent state register On GFX v9.4.3, compute queue MQD is populated using the values in HQD persistent state register. Hence don't clear the values on module unload, instead restore it to the default reset value so that MQD is initialized correctly during next module load. In particular, preload flag needs to be set on compute queue MQD, otherwise it could cause uninitialized values being used at device reset state resulting in EDC. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a28eb487 |
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22-Jun-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Keep non-psp path for partition switch When PSP block is not present, use direct programming. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Tested-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2036b34d |
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18-May-2023 |
Zhigang Luo <Zhigang.Luo@amd.com> |
drm/amdgpu: port SRIOV VF missed changes port SRIOV VF missed changes from gfx_v9_0 to gfx_v9_4_3. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Zhigang Luo <Zhigang.Luo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b00f5537 |
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13-Jun-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use PSP FW API for partition switch Use PSP firmware interface for switching compute partitions. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cab69d36 |
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06-Jun-2023 |
Yang Wang <kevinyang.wang@amd.com> |
drm/amdgpu: skip to resume rlcg for gc 9.4.3 in vf side skip to resume rlcg, because rlcg is already enabled in pf side. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
491ae278 |
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16-May-2023 |
Shiwu Zhang <shiwu.zhang@amd.com> |
drm/amdgpu: complement the 4, 6 and 8 XCC cases Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
89f85765 |
|
15-May-2023 |
Shiwu Zhang <shiwu.zhang@amd.com> |
drm/amdgpu: golden settings for ASIC rev_id 0 Suggested by FW team that GB_ADDR_CONFIG is handled by golden settings in driver to get the expected value Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a09e2065 |
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24-May-2023 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amdgpu: Fix defined but not used gfx9_cs_data in gfx_v9_4_3.c gcc with W=1 In file included from drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:33: drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h:939:36: warning: ‘gfx9_cs_data’ defined but not used [-Wunused-const-variable=] 939 | static const struct cs_section_def gfx9_cs_data[] = { | gfx9_cs_data is not used in gfx_v9_4_3.c, hence remove its include in gfx_v9_4_3.c Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
232f2431 |
|
12-May-2023 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu/gfx: set sched.ready status after ring/IB test in gfx sched.ready is nothing with ring initialization, it needs to set to be true after ring/IB test in amdgpu_ring_test_helper to tell the ring is ready for submission. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e7665d0c |
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22-May-2023 |
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> |
drm/amdgpu: Remove duplicate include ./drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c: amdgpu_xcp.h is included more than once. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=5281 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
803e4c9e |
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22-May-2023 |
Tom Rix <trix@redhat.com> |
drm/amdgpu: remove unused variable num_xcc gcc with W=1 reports drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:2138:13: error: variable ‘num_xcc’ set but not used [-Werror=unused-but-set-variable] 2138 | int num_xcc; | ^~~~~~~ This variable is not used so remove it. Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d7b8e68d |
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19-May-2023 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amdgpu: Fix uninitialized variable in gfx_v9_4_3_cp_resume drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:1925:6: error: variable 'r' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized] if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:1931:6: note: uninitialized use occurs here if (r) ^ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:1925:2: note: remove the 'if' if its condition is always true if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:1923:7: note: initialize the variable 'r' to silence this warning int r, i, num_xcc; ^ = 0 1 error generated. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Cc: Luben Tuikov <luben.tuikov@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
92ecb92c |
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08-Feb-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: initialize RAS for gfx_v9_4_3 Register GFX RAS functions and initialize GFX RAS. v2: remove xcp operations. v3: reuse the return value of gfx_ras_sw_init. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0386d52d |
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10-Feb-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add sq timeout status functions for gfx_v9_4_3 Query and reset sq timeout status. v2: change instance from 0 to xcc_id for register access. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
30feef06 |
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07-Feb-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add RAS error count reset for gfx_v9_4_3 Add GFX RAS error count reset function. v2: remove xcp operation. only select_se_sh when instance number is more than 1. v3: add check for se_num before select_se_sh. change instance from 0 to xcc_id for register access. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bfa84da6 |
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17-Mar-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add RAS error count query for gfx_v9_4_3 Query GFX RAS ce/ue count. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5c1c09a7 |
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05-Feb-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add RAS error count definitions for gfx_v9_4_3 Prepare for the query of GFX RAS ce/ue count. v2: remove xcp operation. only select_se_sh when instance number is more than 1. v3: add more CE/UE registsers to query list. add check for se_num before select_se_sh. change instance from 0 to xcc_id for register access. v4: move gfx memory id definitions to gfx_v9_4_3. v5: create a dedicated patch for adding error count query function. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
47e7f527 |
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02-Feb-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add RAS status reset for gfx_v9_4_3 Reset GFX RAS status registers. v2: fix typo in title. remove xcp operation. v3: change instance from 0 to xcc_id for register access. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bf16235b |
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02-Feb-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add RAS status query for gfx_v9_4_3 Query GFX RAS status. v2: remove xcp operation. v3: change instance from 0 to xcc_id for register access. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
00e1ab02 |
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24-Mar-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Skip halting RLC on GFX v9.4.3 RLC-PMFW handshake happens periodically when GFXCLK DPM is enabled and halting RLC may cause unexpected results. Avoid halting RLC from driver side. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1e91a5f7 |
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16-Mar-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Fix register accesses in GFX v9.4.3 Access registers with the right xcc id. Also, remove the unused logic as PG is not used in GFX v9.4.3 Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b6b85c8b |
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06-Mar-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Return error on invalid compute mode Return error if an invalid compute partition mode is requested. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b6f90baa |
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30-Jan-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Move memory partition query to gmc GMC block handles memory related information, it makes more sense to keep memory partition functions in gmc block. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ded7d99e |
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15-Jan-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add flags for partition mode query It's not required to take lock on all cases while querying partition mode. Querying partition mode during KFD init process doesn't need to take a lock. Init process after a switch will already be happening under lock. Control the behaviour by adding flags to xcp_query_partition_mode. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
228ce176 |
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27-Jan-2023 |
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> |
drm/amdgpu: Handle VRAM dependencies on GFXIP9.4.3 [For 1P NPS1 mode driver bringup] Changes required to initialize the amdgpu driver with frontdoor firmware loading and discovery=2 with the native mode SBIOS that enables CPU GPU unified interleaved memory. sudo modprobe amdgpu discovery=2 Once PSP TMR region is reported via the ACPI interface, the dependency on the ip_discovery.bin will be removed. Choice of where to allocate driver table is given to each IP version. In general, both GTT and VRAM domains will be considered. If one of the tables has a strict restriction for VRAM domain, then only VRAM domain is considered. Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> (lijo: Modified the handling for SMU Tables) Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c1d3f627 |
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19-Jan-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Fix mqd init on GFX v9.4.3 For MQD init, an XCC's queue is selected with GRBM select. However, for initialization of MQD, values read from logical XCC0 registers are used. This results in garbage values being read from XCC0 whose queue is not selected. Change to read from the right XCC for MQD initialization. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b7c7011e |
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19-Jan-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Enable CGCG/LS for GC 9.4.3 Enable coarse grain clockgating/light sleep for GC v9.4.3. Remove programming that is not meant for GC 9.4.3. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
233bb373 |
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19-Jan-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use unique doorbell range per xcc Program different ranges in each XCC with MEC_DOORBELL_RANGE_LOWER/HIGHER. Keeping the same range causes CPF in other XCCs also to be busy when an IB packet is submitted to KCQ. Only the XCC which processes the packet comes back to idle afterwards and this causes other CPs not be idle. This in turn affects clockgating behavior as RLC doesn't get idle interrupt. LOWER/HIGHER covers only KIQ/KCQs which are per XCC queues. Assigning different ranges doesn't seem to have any side effect as user queue ranges are outside of this range. User queue tests - PM4 through KFD and AQL through rocr - have the same results after this change. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
34fd9d68 |
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20-Dec-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add FGCG logic for GFX v9.4.3 Add logic for fine grain clock gating logic for GFX v9.4.3. The feature will be controlled using CG flags. Also, make a change so that RLC safe mode entry/exit is done only once during CG update sequence. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d524180b |
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19-Dec-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Fix GFX v9.4.3 EOP buffer allocation Each compute cluster gets 8 compute queues in GFX v9.4.3. Fix the EOP buffer allocation so that compute queue on every XCC gets a unique address. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Tested-and-Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
98b2e9ca |
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09-Dec-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: correct the vmhub index when page fault occurs The AMDGPU_GFXHUB was bind to each xcc in the logical order. Thus convert the node_id to logical xcc_id to index the correct AMDGPU_GFXHUB. And "node_id / 4" can get the correct AMDGPU_MMHUB0 index. Signed-off-by: Le Ma <le.ma@amd.com> Tested-by: Asad kamal <asad.kamal@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fee500fa |
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17-Nov-2022 |
Shiwu Zhang <shiwu.zhang@amd.com> |
drm/amdgpu: Fix the KCQ hang when binding back Just like the KIQ, KCQ need to clear the doorbell related regs as well to avoid hangs when to load driver again after unloading. Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
73c84f7c |
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23-Sep-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add XCP functions for GFX v9.4.3 Add functions to suspend/resume GFX instances belonging to an XCP. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8e7fd193 |
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16-Nov-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Switch to SOC partition funcs For GFXv9.4.3, use SOC level partition switch implementation rather than keeping them at GFX IP level. Change the exisiting implementation in GFX IP for keeping partition mode and restrict it to only GFX related switch. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
44b5cf2e |
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15-Nov-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add xcc specific functions Add more XCC specific functions and use them from IP block functions. RLC, CP functions are further split to have xcc specific versions. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
880f8b3f |
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20-Jul-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Rename xcc specific functions Add 'xcc' prefix to xcc specific functions to distinguish from IP block functions. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
993d218f |
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14-Nov-2022 |
Shiwu Zhang <shiwu.zhang@amd.com> |
drm/amdgpu: remove partition attributes sys file for gfx_v9_4_3 For driver de-init like rmmod operations those partition specific attributes need to be removed accordingly. Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d55391c2 |
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09-Nov-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Revert programming of CP_PSP_XCP_CTL Programming of this register is taken care by PSP. Incorrect programming causes CP not to detect its XCC. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reported-by: Alexander Turek <Alexander.Turek@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ea2d2f8e |
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05-Apr-2022 |
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> |
drm/amdgpu: detect current GPU memory partition mode - Add helpers to detect the current GPU memory partition. - Add current memory partition mode sysfs node. Tested-by: Ori Messinger <Ori.Messinger@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ebadc106 |
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06-Nov-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: retire render backend setup from gfx_v9_4_3 gfx v9_4_3 only support compute. render backend doesn't need to be involved in any compute shader execution. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
553f973a |
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11-Oct-2022 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Update debugfs for XCC support (v3) This patch updates the 'regs2' interface for MMIO registers to add a new IOCTL command for a 'v2' state data that includes the XCC ID. This patch then updates amdgpu_gfx_select_se_sh() and amdgpu_gfx_select_me_pipe_q() (and the implementations in the gfx drivers) to support an additional parameter. This patch then creates a new debugfs interface "gprwave" which is a merge of shader GPR and wave status access. This new inteface uses an IOCTL to select banks as well as XCC identity. (v2) Fix missing xcc_id in wave_ind function (v3) Fix pm runtime calls and mutex locking (v4) Fix bad label Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
870d1e5a |
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14-Oct-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Fix interrupt handling in GFX v9.4.3 IH follows a different identification scheme for its clients. Get the right mapping of xcc instance from IH node id. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5a8b26a8 |
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19-Sep-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Fix register access on GC v9.4.3 In GC v9.4.3 there are multiple XCCs. It's required to use physical instance number to get the right register offset. Use GET_INST API for that. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
955220b0 |
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06-Oct-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Fix programming of initial XCP mode On initialization set the partition mode correctly to SPX (default) or any other user specified partition mode. Use switch_compute_partition API so that all settings are initialized correctly. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9cd51d53 |
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25-Aug-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: drop redundant csb init for gfx943 It's not required for compute pipeline and will cause soft lockup on emulation due to long-time writing. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0b02364e |
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29-Jul-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Conform to SET_UCONFIG_REG spec The packet expects only 16 bits register offset. Hence pass register offset which is local to each XCC. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7aa8a266 |
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06-Jul-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Fix GRBM programming sequence It needs to be done only for XCC instances in non-AID0. Use the physical instance to determine non-AID0 XCC instances. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
659a4ab8 |
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04-Jul-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use instance lookup table for GC 9.4.3 Register accesses need to be based on physical instance on bare metal. Pass the right instance using logical to physical instance lookup table before accessing registers. Add a macro GET_INST to get the right physical instance of an IP corresponding to a logical instance. v2: fix gfx_v9_4_3_check_rlcg_range() (Alex) Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0c7315e7 |
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10-Jun-2022 |
Mukul Joshi <mukul.joshi@amd.com> |
drm/amdkfd: Add device repartition support GFX9.4.3 will support dynamic repartitioning of the GPU through sysfs. Add device repartitioning support in KFD to repartition GPU from one mode to other. v2: squash in fix ("drm/amdkfd: Fix warning kgd2kfd_unlock_kfd defined but not used") Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8078f1c6 |
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29-Jun-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Change num_xcd to xcc_mask Instead of number of XCCs, keep a mask of XCCs for the exact XCCs available on the ASIC. XCC configuration could differ based on different ASIC configs. v2: Rename num_xcd to num_xcc (Hawking) Use smaller xcc_mask size, changed to u16 (Le) Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
20bedf13 |
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25-Apr-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: introduce new doorbell assignment table for GC 9.4.3 Four basic reasons as below to do the change: 1. number of ring expand a lot on GC 9.4.3, and adjustment on old assignment cannot make each ring in a continuous doorbell space. 2. the SDMA doorbell index should not exceed 0x1FF on SDMA 4.2.2 due to regDOORBELLx_CTRL_ENTRY.BIF_DOORBELLx_RANGE_OFFSET_ENTRY field width. 3. re-design the doorbell assignment and unify the calculation as "start + ring/inst id" will make the code much concise. 4. only defining the START/END makes the table look simple v2: (Lijo) 1. replace name 2. use num_inst_per_aid/sdma_doorbell_range instead of hardcoding Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
36be0181 |
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20-Apr-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: program GRBM_MCM_ADDR for non-AID0 GRBM Otherwise the EOP interrupt on non-AID0 cannot route to IH0. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a8027fcd |
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02-Mar-2022 |
Mukul Joshi <mukul.joshi@amd.com> |
drm/amdgpu: Fix CP_HYP_XCP_CTL register programming in CPX mode Currently, in CPX mode, the CP_HYP_XCP_CTL register is programmed incorrectly with the number of XCCs in the partition. As a result, HIQ doesn't work in CPX mode. Fix this by programming the correct number of XCCs in a partition, which is 1, in CPX mode. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e6a02e2c |
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18-Feb-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add some XCC programming Add additional XCC programming sequences. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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15091a6f |
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19-Nov-2021 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add node_id to physical id conversion in EOP handler A new field nodeid in interrupt cookie indicates the node ID. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Shiwu Zhang <shiwu.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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147862d0 |
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02-Jun-2022 |
Shiwu Zhang <shiwu.zhang@amd.com> |
drm/amdgpu: enable the ring and IB test for slave kcq With the mec FW update to utilize the mqd base set by driver for kcq mapping, slave kcq ring test and IB test can be re-enabled. Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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89cf4549 |
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22-May-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: support gc v9_4_3 ring_test running on all xcc Each xcc has its own sratch_reg offset Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9b4fd276 |
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12-Jan-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use the correct API to read register Use SOC15 API so that the register offset is calculated correctly. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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0fa49d10 |
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16-Dec-2021 |
Shiwu Zhang <shiwu.zhang@amd.com> |
drm/amdgpu: override partition mode through module parameter Add a module parameter to override the partition mode. Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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98a54e88 |
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17-May-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add sysfs node for compute partition mode Add current/available compute partitin mode sysfs node. v2: make the sysfs node as IP independent one in amdgpu_gfx.c Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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3566938b |
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20-Dec-2021 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: assign different AMDGPU_GFXHUB for rings on each xcc Pass the xcc_id to AMDGPU_GFXHUB(x) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f4caf584 |
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14-Sep-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: introduce vmhub definition for multi-partition cases (v3) v1: Each partition has its own gfxhub or mmhub. adjust the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le) v2: re-design the AMDGPU_GFXHUB/AMDGPU_MMHUB layout (Le) v3: apply the gfxhub/mmhub layout to new IPs (Hawking) v4: fix up gmc11 (Alex) v5: rebase (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9e72813f |
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06-May-2023 |
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> |
drm/amdgpu: Remove the unused variable golden_settings_gc_9_4_3 Variable golden_settings_gc_9_4_3 is not effectively used, so delete it. drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:48:38: warning: ‘golden_settings_gc_9_4_3’ defined but not used. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4877 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f4409a23 |
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03-May-2023 |
Dan Carpenter <dan.carpenter@linaro.org> |
drm/amdgpu: unlock on error in gfx_v9_4_3_kiq_resume() Smatch complains that we need to drop this lock before returning. drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:1838 gfx_v9_4_3_kiq_resume() warn: inconsistent returns 'ring->mqd_obj->tbo.base.resv'. Fixes: 86301129698b ("drm/amdgpu: split gc v9_4_3 functionality from gc v9_0") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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45b54a7d |
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26-Apr-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/gfx9: always restore kcq MQDs Always restore the MQD not just when we do a reset. This allows us to move the MQD to VRAM if we want. v2: always reset ring pointer as well (Christian) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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3c4f6507 |
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26-Apr-2023 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: mark gfx_v9_4_3_disable_gpa_mode() static This was left global by accident, the corresponding functions for other hardware types are already static: drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:1072:6: error: no previous prototype for function 'gfx_v9_4_3_disable_gpa_mode' [-Werror,-Wmissing-prototypes] Fixes: 86301129698b ("drm/amdgpu: split gc v9_4_3 functionality from gc v9_0") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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47659738 |
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19-Nov-2021 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: allocate doorbell index for multi-die case Allocate different doorbell index for kiq/kcq rings on each die Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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66daccde |
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01-Dec-2021 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add master/slave check in init phase Skip KCQ setup on slave xcc as there's no use case. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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86b20703 |
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27-Jul-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add xcc index argument to rlc safe_mode func (v4) v1: To support multple XCD case (Le) v2: unify naming style (Le) v3: apply the changes to gc v11_0 (Hawking) v4: apply the changes to gc SOC21 (Morris) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Morris Zhang <Shiwu.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d51ac6d0 |
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23-May-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add xcc index argument to select_sh_se function v2 v1: To support multiple XCD case (Le) v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ec08571a |
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17-Nov-2021 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add xcc index argument to gfx v9_4_3 functions Change those v9_4_3 interfaces which are exposed in gfx_v9_0.c. For some active single-xcc emu models, the code path in gfx_v9_0.c is better to keep reserved for a while. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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6f917fdc |
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17-Nov-2021 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add multi-XCC initial support in gfx_v9_4_3.c Each XCD needs to be initialized respectively. The major changes are: 1. add iteration to do rlc/kiq/kcq init/fini for each xcd 2. load rlc/mec microcode to each xcd 3. add argument to specify xcc index in initialization functions Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5aa998ba |
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17-Nov-2021 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add xcc index argument to soc15_grbm_select To support grbm select for multiple XCD case. v2: unify naming style Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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86301129 |
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23-May-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: split gc v9_4_3 functionality from gc v9_0 To prepare for gc v9_4_3 specific feature. v2: fix exports (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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de7511ae |
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25-Oct-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to v9_4_3 gfx_funcs callbacks for GC 9.4.3 add gfx_funcs callbacks implemenation based on gc_v9_4_3 ip headers Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7c0f7ee0 |
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13-Oct-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add gc v9_4_3 rlc_funcs implementation all the gc v9_4_3 registers fall in gc_rlcpdec address range have different relative offsets and base_idx from the ones defined in gc v9_0 ip headers. gc_v9_0_rlc_funcs can not be reused anymore for gc v9_4_3 v2: drop unused handshake function (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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