Searched refs:pl (Results 26 - 50 of 136) sorted by path

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/linux-master/arch/arm/include/asm/
H A Dassembler.h206 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo variable
545 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo variable
/linux-master/arch/arm/mm/
H A Dcache-v7m.S66 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
75 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
/linux-master/arch/arm64/crypto/
H A DMakefile87 $(obj)/%-core.S: $(src)/%-armv8.pl
90 $(obj)/sha256-core.S: $(src)/sha512-armv8.pl
H A Daes-neonbs-core.S577 csel x23, x23, xzr, pl
651 csel x23, x23, xzr, pl
/linux-master/arch/arm64/kernel/
H A Defi-header.S17 ccmp x18, #0, #0xd, pl
/linux-master/arch/arm64/lib/
H A Dstrnlen.S82 ccmp tmp1, #0, #0, pl /* NZCV = 0000 */
/linux-master/arch/mips/crypto/
H A DMakefile21 $(obj)/poly1305-core.S: $(src)/poly1305-mips.pl FORCE
/linux-master/arch/mips/kernel/
H A Dpm-cps.c186 static void cps_gen_cache_routine(u32 **pp, struct uasm_label **pl, argument
209 uasm_build_label(pl, *pp, lbl);
230 static int cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl, argument
286 uasm_build_label(pl, *pp, lbl);
323 static void cps_gen_set_top_bit(u32 **pp, struct uasm_label **pl, argument
328 uasm_build_label(pl, *pp, lbl);
/linux-master/arch/powerpc/crypto/
H A DMakefile48 $(obj)/aesp10-ppc.S $(obj)/ghashp10-ppc.S: $(obj)/%.S: $(src)/%.pl FORCE
51 $(obj)/aesp8-ppc.S $(obj)/ghashp8-ppc.S: $(obj)/%.S: $(src)/%.pl FORCE
/linux-master/arch/powerpc/tools/
H A Dcheckpatch.sh9 exec $script_base/../../../scripts/checkpatch.pl \
/linux-master/arch/sh/lib/
H A Dchecksum.S313 cmp/pl r6
331 cmp/pl r6
/linux-master/arch/x86/crypto/
H A DMakefile114 $(obj)/%.S: $(src)/%.pl FORCE
/linux-master/drivers/acpi/acpica/
H A Dacdebug.h43 #define PARAM_LIST(pl) pl
/linux-master/drivers/ata/
H A Dpata_legacy.c1216 struct legacy_probe *pl = &probe_list[0]; local
1261 for (i = 0; i < NR_HOST; i++, pl++) {
1262 if (pl->port == 0)
1264 if (pl->type == UNKNOWN)
1265 pl->type = probe_chip_type(pl);
1266 pl->slot = slot++;
1267 if (legacy_init_one(pl) == 0)
/linux-master/drivers/atm/
H A Dnicstar.c2478 pool_levels pl; local
2486 (pl.buftype, &((pool_levels __user *) arg)->buftype))
2488 switch (pl.buftype) {
2490 pl.count =
2492 pl.level.min = card->sbnr.min;
2493 pl.level.init = card->sbnr.init;
2494 pl.level.max = card->sbnr.max;
2498 pl.count =
2500 pl.level.min = card->lbnr.min;
2501 pl
[all...]
/linux-master/drivers/crypto/
H A Dsa2ul.c1045 size_t ml, pl; local
1052 mdptr = (__be32 *)dmaengine_desc_get_metadata_ptr(rxd->tx_in, &pl,
1090 size_t pl, ml, split_size; local
1274 mdptr = (u32 *)dmaengine_desc_get_metadata_ptr(tx_out, &pl, &ml);
1360 size_t ml, pl; local
1369 mdptr = (__be32 *)dmaengine_desc_get_metadata_ptr(rxd->tx_in, &pl, &ml);
1699 size_t pl, ml; local
1710 mdptr = (u32 *)dmaengine_desc_get_metadata_ptr(rxd->tx_in, &pl, &ml);
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_dmub_srv.c1047 struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx,
1051 pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw;
1052 pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw;
1053 pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw;
1054 pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw;
1057 pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw;
1058 pl->position_cfg.pipe_idx = p_idx;
1046 dc_build_cursor_position_update_payload0( struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx, const struct hubp *hubp, const struct dpp *dpp) argument
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dkv_dpm.c2675 struct kv_pl *pl = &ps->levels[index]; local
2680 pl->sclk = sclk;
2681 pl->vddc_index = clock_info->sumo.vddcIndex;
2686 pl->ds_divider_index = 5;
2687 pl->ss_divider_index = 5;
2891 struct kv_pl *pl = &ps->levels[i]; local
2893 i, pl->sclk,
2894 kv_convert_8bit_index_to_voltage(adev, pl->vddc_index));
H A Dsi_dpm.c1842 struct rv7xx_pl *pl,
3284 struct rv7xx_pl *pl)
3287 if ((pl->mclk == 0) || (pl->sclk == 0))
3290 if (pl->mclk == pl->sclk)
3293 if (pl->mclk > pl->sclk) {
3294 if (((pl->mclk + (pl
3282 btc_adjust_clock_combinations(struct amdgpu_device *adev, const struct amdgpu_clock_and_voltage_limits *max_limits, struct rv7xx_pl *pl) argument
4751 si_populate_memory_timing_parameters(struct amdgpu_device *adev, struct rv7xx_pl *pl, SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) argument
5460 si_convert_power_level_to_smc(struct amdgpu_device *adev, struct rv7xx_pl *pl, SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) argument
6090 si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, struct rv7xx_pl *pl, SMC_SIslands_MCRegisterSet *mc_reg_table_data) argument
7188 struct rv7xx_pl *pl = &ps->performance_levels[index]; local
7533 struct rv7xx_pl *pl; local
7923 struct rv7xx_pl *pl; local
[all...]
H A Dsi_dpm.h331 struct rv7xx_pl *pl; member in struct:evergreen_ulv_param
961 struct rv7xx_pl pl; member in struct:si_ulv_param
/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dci_smumgr.c372 const struct phm_phase_shedding_limits_table *pl,
380 for (i = 0; i < pl->count; i++) {
381 if (sclk < pl->entries[i].Sclk) {
1157 static int ci_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, argument
1164 for (i = 0; i < pl->count; i++) {
1165 if (memory_clock < pl->entries[i].Mclk) {
371 ci_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, uint32_t sclk, uint32_t *p_shed) argument
H A Diceland_smumgr.c874 const struct phm_phase_shedding_limits_table *pl,
882 for (i = 0; i < pl->count; i++) {
883 if (sclk < pl->entries[i].Sclk) {
1210 static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, argument
1217 for (i = 0; i < pl->count; i++) {
1218 if (memory_clock < pl->entries[i].Mclk) {
873 iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, uint32_t sclk, uint32_t *p_shed) argument
/linux-master/drivers/gpu/drm/bridge/imx/
H A Dimx8qxp-pixel-link.c39 static void imx8qxp_pixel_link_enable_mst_en(struct imx8qxp_pixel_link *pl) argument
43 ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
44 pl->mst_en_ctrl, true);
46 DRM_DEV_ERROR(pl->dev,
48 pl->dc_id, pl->stream_id, ret);
51 static void imx8qxp_pixel_link_enable_mst_vld(struct imx8qxp_pixel_link *pl) argument
55 ret = imx_sc_misc_set_control(pl->ipc_handle, pl
63 imx8qxp_pixel_link_enable_sync(struct imx8qxp_pixel_link *pl) argument
75 imx8qxp_pixel_link_disable_mst_en(struct imx8qxp_pixel_link *pl) argument
89 imx8qxp_pixel_link_disable_mst_vld(struct imx8qxp_pixel_link *pl) argument
103 imx8qxp_pixel_link_disable_sync(struct imx8qxp_pixel_link *pl) argument
117 imx8qxp_pixel_link_set_mst_addr(struct imx8qxp_pixel_link *pl) argument
133 struct imx8qxp_pixel_link *pl = bridge->driver_private; local
156 struct imx8qxp_pixel_link *pl = bridge->driver_private; local
165 struct imx8qxp_pixel_link *pl = bridge->driver_private; local
176 struct imx8qxp_pixel_link *pl = bridge->driver_private; local
250 imx8qxp_pixel_link_disable_all_controls(struct imx8qxp_pixel_link *pl) argument
266 imx8qxp_pixel_link_find_next_bridge(struct imx8qxp_pixel_link *pl) argument
331 struct imx8qxp_pixel_link *pl; local
403 struct imx8qxp_pixel_link *pl = platform_get_drvdata(pdev); local
[all...]
/linux-master/drivers/gpu/drm/
H A Ddrm_gem_vram_helper.c544 struct ttm_placement *pl)
547 *pl = gbo->placement;
543 drm_gem_vram_bo_driver_evict_flags(struct drm_gem_vram_object *gbo, struct ttm_placement *pl) argument
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_execlists_submission.c370 struct list_head *pl; local
388 pl = i915_sched_lookup_priolist(engine->sched_engine,
393 list_move(&rq->sched.link, pl);
1075 static void defer_request(struct i915_request *rq, struct list_head * const pl) argument
1090 list_move_tail(&rq->sched.link, pl);

Completed in 382 milliseconds

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