1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef __SI_DPM_H__ 24#define __SI_DPM_H__ 25 26#include "amdgpu_atombios.h" 27#include "sislands_smc.h" 28 29#define MC_CG_CONFIG 0x96f 30#define MC_ARB_CG 0x9fa 31#define CG_ARB_REQ(x) ((x) << 0) 32#define CG_ARB_REQ_MASK (0xff << 0) 33 34#define MC_ARB_DRAM_TIMING_1 0x9fc 35#define MC_ARB_DRAM_TIMING_2 0x9fd 36#define MC_ARB_DRAM_TIMING_3 0x9fe 37#define MC_ARB_DRAM_TIMING2_1 0x9ff 38#define MC_ARB_DRAM_TIMING2_2 0xa00 39#define MC_ARB_DRAM_TIMING2_3 0xa01 40 41#define MAX_NO_OF_MVDD_VALUES 2 42#define MAX_NO_VREG_STEPS 32 43#define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 44#define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32 45#define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 46#define RV770_ASI_DFLT 1000 47#define CYPRESS_HASI_DFLT 400000 48#define PCIE_PERF_REQ_PECI_GEN1 2 49#define PCIE_PERF_REQ_PECI_GEN2 3 50#define PCIE_PERF_REQ_PECI_GEN3 4 51#define RV770_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ 52#define RV770_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ 53 54#define SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE 16 55 56#define RV770_SMC_TABLE_ADDRESS 0xB000 57#define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 3 58 59#define SMC_STROBE_RATIO 0x0F 60#define SMC_STROBE_ENABLE 0x10 61 62#define SMC_MC_EDC_RD_FLAG 0x01 63#define SMC_MC_EDC_WR_FLAG 0x02 64#define SMC_MC_RTT_ENABLE 0x04 65#define SMC_MC_STUTTER_EN 0x08 66 67#define RV770_SMC_VOLTAGEMASK_VDDC 0 68#define RV770_SMC_VOLTAGEMASK_MVDD 1 69#define RV770_SMC_VOLTAGEMASK_VDDCI 2 70#define RV770_SMC_VOLTAGEMASK_MAX 4 71 72#define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 73#define NISLANDS_SMC_STROBE_RATIO 0x0F 74#define NISLANDS_SMC_STROBE_ENABLE 0x10 75 76#define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01 77#define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02 78#define NISLANDS_SMC_MC_RTT_ENABLE 0x04 79#define NISLANDS_SMC_MC_STUTTER_EN 0x08 80 81#define MAX_NO_VREG_STEPS 32 82 83#define NISLANDS_SMC_VOLTAGEMASK_VDDC 0 84#define NISLANDS_SMC_VOLTAGEMASK_MVDD 1 85#define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2 86#define NISLANDS_SMC_VOLTAGEMASK_MAX 4 87 88#define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0 89#define SISLANDS_MCREGISTERTABLE_ACPI_SLOT 1 90#define SISLANDS_MCREGISTERTABLE_ULV_SLOT 2 91#define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 3 92 93#define SISLANDS_LEAKAGE_INDEX0 0xff01 94#define SISLANDS_MAX_LEAKAGE_COUNT 4 95 96#define SISLANDS_MAX_HARDWARE_POWERLEVELS 5 97#define SISLANDS_INITIAL_STATE_ARB_INDEX 0 98#define SISLANDS_ACPI_STATE_ARB_INDEX 1 99#define SISLANDS_ULV_STATE_ARB_INDEX 2 100#define SISLANDS_DRIVER_STATE_ARB_INDEX 3 101 102#define SISLANDS_DPM2_MAX_PULSE_SKIP 256 103 104#define SISLANDS_DPM2_NEAR_TDP_DEC 10 105#define SISLANDS_DPM2_ABOVE_SAFE_INC 5 106#define SISLANDS_DPM2_BELOW_SAFE_INC 20 107 108#define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80 109 110#define SISLANDS_DPM2_MAXPS_PERCENT_H 99 111#define SISLANDS_DPM2_MAXPS_PERCENT_M 99 112 113#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF 114#define SISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12 115#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 116#define SISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E 117#define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF 118 119#define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN 10 120 121#define SISLANDS_VRC_DFLT 0xC000B3 122#define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT 1687 123#define SISLANDS_CGULVPARAMETER_DFLT 0x00040035 124#define SISLANDS_CGULVCONTROL_DFLT 0x1f007550 125 126#define SI_ASI_DFLT 10000 127#define SI_BSP_DFLT 0x41EB 128#define SI_BSU_DFLT 0x2 129#define SI_AH_DFLT 5 130#define SI_RLP_DFLT 25 131#define SI_RMP_DFLT 65 132#define SI_LHP_DFLT 40 133#define SI_LMP_DFLT 15 134#define SI_TD_DFLT 0 135#define SI_UTC_DFLT_00 0x24 136#define SI_UTC_DFLT_01 0x22 137#define SI_UTC_DFLT_02 0x22 138#define SI_UTC_DFLT_03 0x22 139#define SI_UTC_DFLT_04 0x22 140#define SI_UTC_DFLT_05 0x22 141#define SI_UTC_DFLT_06 0x22 142#define SI_UTC_DFLT_07 0x22 143#define SI_UTC_DFLT_08 0x22 144#define SI_UTC_DFLT_09 0x22 145#define SI_UTC_DFLT_10 0x22 146#define SI_UTC_DFLT_11 0x22 147#define SI_UTC_DFLT_12 0x22 148#define SI_UTC_DFLT_13 0x22 149#define SI_UTC_DFLT_14 0x22 150#define SI_DTC_DFLT_00 0x24 151#define SI_DTC_DFLT_01 0x22 152#define SI_DTC_DFLT_02 0x22 153#define SI_DTC_DFLT_03 0x22 154#define SI_DTC_DFLT_04 0x22 155#define SI_DTC_DFLT_05 0x22 156#define SI_DTC_DFLT_06 0x22 157#define SI_DTC_DFLT_07 0x22 158#define SI_DTC_DFLT_08 0x22 159#define SI_DTC_DFLT_09 0x22 160#define SI_DTC_DFLT_10 0x22 161#define SI_DTC_DFLT_11 0x22 162#define SI_DTC_DFLT_12 0x22 163#define SI_DTC_DFLT_13 0x22 164#define SI_DTC_DFLT_14 0x22 165#define SI_VRC_DFLT 0x0000C003 166#define SI_VOLTAGERESPONSETIME_DFLT 1000 167#define SI_BACKBIASRESPONSETIME_DFLT 1000 168#define SI_VRU_DFLT 0x3 169#define SI_SPLLSTEPTIME_DFLT 0x1000 170#define SI_SPLLSTEPUNIT_DFLT 0x3 171#define SI_TPU_DFLT 0 172#define SI_TPC_DFLT 0x200 173#define SI_SSTU_DFLT 0 174#define SI_SST_DFLT 0x00C8 175#define SI_GICST_DFLT 0x200 176#define SI_FCT_DFLT 0x0400 177#define SI_FCTU_DFLT 0 178#define SI_CTXCGTT3DRPHC_DFLT 0x20 179#define SI_CTXCGTT3DRSDC_DFLT 0x40 180#define SI_VDDC3DOORPHC_DFLT 0x100 181#define SI_VDDC3DOORSDC_DFLT 0x7 182#define SI_VDDC3DOORSU_DFLT 0 183#define SI_MPLLLOCKTIME_DFLT 100 184#define SI_MPLLRESETTIME_DFLT 150 185#define SI_VCOSTEPPCT_DFLT 20 186#define SI_ENDINGVCOSTEPPCT_DFLT 5 187#define SI_REFERENCEDIVIDER_DFLT 4 188 189#define SI_PM_NUMBER_OF_TC 15 190#define SI_PM_NUMBER_OF_SCLKS 20 191#define SI_PM_NUMBER_OF_MCLKS 4 192#define SI_PM_NUMBER_OF_VOLTAGE_LEVELS 4 193#define SI_PM_NUMBER_OF_ACTIVITY_LEVELS 3 194 195/* XXX are these ok? */ 196#define SI_TEMP_RANGE_MIN (90 * 1000) 197#define SI_TEMP_RANGE_MAX (120 * 1000) 198 199#define FDO_PWM_MODE_STATIC 1 200#define FDO_PWM_MODE_STATIC_RPM 5 201 202enum ni_dc_cac_level 203{ 204 NISLANDS_DCCAC_LEVEL_0 = 0, 205 NISLANDS_DCCAC_LEVEL_1, 206 NISLANDS_DCCAC_LEVEL_2, 207 NISLANDS_DCCAC_LEVEL_3, 208 NISLANDS_DCCAC_LEVEL_4, 209 NISLANDS_DCCAC_LEVEL_5, 210 NISLANDS_DCCAC_LEVEL_6, 211 NISLANDS_DCCAC_LEVEL_7, 212 NISLANDS_DCCAC_MAX_LEVELS 213}; 214 215enum si_cac_config_reg_type 216{ 217 SISLANDS_CACCONFIG_MMR = 0, 218 SISLANDS_CACCONFIG_CGIND, 219 SISLANDS_CACCONFIG_MAX 220}; 221 222enum si_power_level { 223 SI_POWER_LEVEL_LOW = 0, 224 SI_POWER_LEVEL_MEDIUM = 1, 225 SI_POWER_LEVEL_HIGH = 2, 226 SI_POWER_LEVEL_CTXSW = 3, 227}; 228 229enum si_td { 230 SI_TD_AUTO, 231 SI_TD_UP, 232 SI_TD_DOWN, 233}; 234 235enum si_display_watermark { 236 SI_DISPLAY_WATERMARK_LOW = 0, 237 SI_DISPLAY_WATERMARK_HIGH = 1, 238}; 239 240enum si_display_gap 241{ 242 SI_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, 243 SI_PM_DISPLAY_GAP_VBLANK = 1, 244 SI_PM_DISPLAY_GAP_WATERMARK = 2, 245 SI_PM_DISPLAY_GAP_IGNORE = 3, 246}; 247 248extern const struct amdgpu_ip_block_version si_smu_ip_block; 249 250struct ni_leakage_coeffients 251{ 252 u32 at; 253 u32 bt; 254 u32 av; 255 u32 bv; 256 s32 t_slope; 257 s32 t_intercept; 258 u32 t_ref; 259}; 260 261struct SMC_Evergreen_MCRegisterAddress 262{ 263 uint16_t s0; 264 uint16_t s1; 265}; 266 267typedef struct SMC_Evergreen_MCRegisterAddress SMC_Evergreen_MCRegisterAddress; 268 269struct evergreen_mc_reg_entry { 270 u32 mclk_max; 271 u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 272}; 273 274struct evergreen_mc_reg_table { 275 u8 last; 276 u8 num_entries; 277 u16 valid_flag; 278 struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 279 SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 280}; 281 282struct SMC_Evergreen_MCRegisterSet 283{ 284 uint32_t value[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 285}; 286 287typedef struct SMC_Evergreen_MCRegisterSet SMC_Evergreen_MCRegisterSet; 288 289struct SMC_Evergreen_MCRegisters 290{ 291 uint8_t last; 292 uint8_t reserved[3]; 293 SMC_Evergreen_MCRegisterAddress address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 294 SMC_Evergreen_MCRegisterSet data[5]; 295}; 296 297typedef struct SMC_Evergreen_MCRegisters SMC_Evergreen_MCRegisters; 298 299struct SMC_NIslands_MCRegisterSet 300{ 301 uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 302}; 303 304typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet; 305 306struct ni_mc_reg_entry { 307 u32 mclk_max; 308 u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 309}; 310 311struct SMC_NIslands_MCRegisterAddress 312{ 313 uint16_t s0; 314 uint16_t s1; 315}; 316 317typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress; 318 319struct SMC_NIslands_MCRegisters 320{ 321 uint8_t last; 322 uint8_t reserved[3]; 323 SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 324 SMC_NIslands_MCRegisterSet data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; 325}; 326 327typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters; 328 329struct evergreen_ulv_param { 330 bool supported; 331 struct rv7xx_pl *pl; 332}; 333 334struct evergreen_arb_registers { 335 u32 mc_arb_dram_timing; 336 u32 mc_arb_dram_timing2; 337 u32 mc_arb_rfsh_rate; 338 u32 mc_arb_burst_time; 339}; 340 341struct at { 342 u32 rlp; 343 u32 rmp; 344 u32 lhp; 345 u32 lmp; 346}; 347 348struct ni_clock_registers { 349 u32 cg_spll_func_cntl; 350 u32 cg_spll_func_cntl_2; 351 u32 cg_spll_func_cntl_3; 352 u32 cg_spll_func_cntl_4; 353 u32 cg_spll_spread_spectrum; 354 u32 cg_spll_spread_spectrum_2; 355 u32 mclk_pwrmgt_cntl; 356 u32 dll_cntl; 357 u32 mpll_ad_func_cntl; 358 u32 mpll_ad_func_cntl_2; 359 u32 mpll_dq_func_cntl; 360 u32 mpll_dq_func_cntl_2; 361 u32 mpll_ss1; 362 u32 mpll_ss2; 363}; 364 365struct RV770_SMC_SCLK_VALUE 366{ 367 uint32_t vCG_SPLL_FUNC_CNTL; 368 uint32_t vCG_SPLL_FUNC_CNTL_2; 369 uint32_t vCG_SPLL_FUNC_CNTL_3; 370 uint32_t vCG_SPLL_SPREAD_SPECTRUM; 371 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 372 uint32_t sclk_value; 373}; 374 375typedef struct RV770_SMC_SCLK_VALUE RV770_SMC_SCLK_VALUE; 376 377struct RV770_SMC_MCLK_VALUE 378{ 379 uint32_t vMPLL_AD_FUNC_CNTL; 380 uint32_t vMPLL_AD_FUNC_CNTL_2; 381 uint32_t vMPLL_DQ_FUNC_CNTL; 382 uint32_t vMPLL_DQ_FUNC_CNTL_2; 383 uint32_t vMCLK_PWRMGT_CNTL; 384 uint32_t vDLL_CNTL; 385 uint32_t vMPLL_SS; 386 uint32_t vMPLL_SS2; 387 uint32_t mclk_value; 388}; 389 390typedef struct RV770_SMC_MCLK_VALUE RV770_SMC_MCLK_VALUE; 391 392 393struct RV730_SMC_MCLK_VALUE 394{ 395 uint32_t vMCLK_PWRMGT_CNTL; 396 uint32_t vDLL_CNTL; 397 uint32_t vMPLL_FUNC_CNTL; 398 uint32_t vMPLL_FUNC_CNTL2; 399 uint32_t vMPLL_FUNC_CNTL3; 400 uint32_t vMPLL_SS; 401 uint32_t vMPLL_SS2; 402 uint32_t mclk_value; 403}; 404 405typedef struct RV730_SMC_MCLK_VALUE RV730_SMC_MCLK_VALUE; 406 407struct RV770_SMC_VOLTAGE_VALUE 408{ 409 uint16_t value; 410 uint8_t index; 411 uint8_t padding; 412}; 413 414typedef struct RV770_SMC_VOLTAGE_VALUE RV770_SMC_VOLTAGE_VALUE; 415 416union RV7XX_SMC_MCLK_VALUE 417{ 418 RV770_SMC_MCLK_VALUE mclk770; 419 RV730_SMC_MCLK_VALUE mclk730; 420}; 421 422typedef union RV7XX_SMC_MCLK_VALUE RV7XX_SMC_MCLK_VALUE, *LPRV7XX_SMC_MCLK_VALUE; 423 424struct RV770_SMC_HW_PERFORMANCE_LEVEL 425{ 426 uint8_t arbValue; 427 union{ 428 uint8_t seqValue; 429 uint8_t ACIndex; 430 }; 431 uint8_t displayWatermark; 432 uint8_t gen2PCIE; 433 uint8_t gen2XSP; 434 uint8_t backbias; 435 uint8_t strobeMode; 436 uint8_t mcFlags; 437 uint32_t aT; 438 uint32_t bSP; 439 RV770_SMC_SCLK_VALUE sclk; 440 RV7XX_SMC_MCLK_VALUE mclk; 441 RV770_SMC_VOLTAGE_VALUE vddc; 442 RV770_SMC_VOLTAGE_VALUE mvdd; 443 RV770_SMC_VOLTAGE_VALUE vddci; 444 uint8_t reserved1; 445 uint8_t reserved2; 446 uint8_t stateFlags; 447 uint8_t padding; 448}; 449 450typedef struct RV770_SMC_HW_PERFORMANCE_LEVEL RV770_SMC_HW_PERFORMANCE_LEVEL; 451 452struct RV770_SMC_SWSTATE 453{ 454 uint8_t flags; 455 uint8_t padding1; 456 uint8_t padding2; 457 uint8_t padding3; 458 RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; 459}; 460 461typedef struct RV770_SMC_SWSTATE RV770_SMC_SWSTATE; 462 463struct RV770_SMC_VOLTAGEMASKTABLE 464{ 465 uint8_t highMask[RV770_SMC_VOLTAGEMASK_MAX]; 466 uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX]; 467}; 468 469typedef struct RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGEMASKTABLE; 470 471struct RV770_SMC_STATETABLE 472{ 473 uint8_t thermalProtectType; 474 uint8_t systemFlags; 475 uint8_t maxVDDCIndexInPPTable; 476 uint8_t extraFlags; 477 uint8_t highSMIO[MAX_NO_VREG_STEPS]; 478 uint32_t lowSMIO[MAX_NO_VREG_STEPS]; 479 RV770_SMC_VOLTAGEMASKTABLE voltageMaskTable; 480 RV770_SMC_SWSTATE initialState; 481 RV770_SMC_SWSTATE ACPIState; 482 RV770_SMC_SWSTATE driverState; 483 RV770_SMC_SWSTATE ULVState; 484}; 485 486typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE; 487 488struct vddc_table_entry { 489 u16 vddc; 490 u8 vddc_index; 491 u8 high_smio; 492 u32 low_smio; 493}; 494 495struct rv770_clock_registers { 496 u32 cg_spll_func_cntl; 497 u32 cg_spll_func_cntl_2; 498 u32 cg_spll_func_cntl_3; 499 u32 cg_spll_spread_spectrum; 500 u32 cg_spll_spread_spectrum_2; 501 u32 mpll_ad_func_cntl; 502 u32 mpll_ad_func_cntl_2; 503 u32 mpll_dq_func_cntl; 504 u32 mpll_dq_func_cntl_2; 505 u32 mclk_pwrmgt_cntl; 506 u32 dll_cntl; 507 u32 mpll_ss1; 508 u32 mpll_ss2; 509}; 510 511struct rv730_clock_registers { 512 u32 cg_spll_func_cntl; 513 u32 cg_spll_func_cntl_2; 514 u32 cg_spll_func_cntl_3; 515 u32 cg_spll_spread_spectrum; 516 u32 cg_spll_spread_spectrum_2; 517 u32 mclk_pwrmgt_cntl; 518 u32 dll_cntl; 519 u32 mpll_func_cntl; 520 u32 mpll_func_cntl2; 521 u32 mpll_func_cntl3; 522 u32 mpll_ss; 523 u32 mpll_ss2; 524}; 525 526union r7xx_clock_registers { 527 struct rv770_clock_registers rv770; 528 struct rv730_clock_registers rv730; 529}; 530 531struct rv7xx_power_info { 532 /* flags */ 533 bool mem_gddr5; 534 bool pcie_gen2; 535 bool dynamic_pcie_gen2; 536 bool acpi_pcie_gen2; 537 bool boot_in_gen2; 538 bool voltage_control; /* vddc */ 539 bool mvdd_control; 540 bool sclk_ss; 541 bool mclk_ss; 542 bool dynamic_ss; 543 bool gfx_clock_gating; 544 bool mg_clock_gating; 545 bool mgcgtssm; 546 bool power_gating; 547 bool thermal_protection; 548 bool display_gap; 549 bool dcodt; 550 bool ulps; 551 /* registers */ 552 union r7xx_clock_registers clk_regs; 553 u32 s0_vid_lower_smio_cntl; 554 /* voltage */ 555 u32 vddc_mask_low; 556 u32 mvdd_mask_low; 557 u32 mvdd_split_frequency; 558 u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES]; 559 u16 max_vddc; 560 u16 max_vddc_in_table; 561 u16 min_vddc_in_table; 562 struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS]; 563 u8 valid_vddc_entries; 564 /* dc odt */ 565 u32 mclk_odt_threshold; 566 u8 odt_value_0[2]; 567 u8 odt_value_1[2]; 568 /* stored values */ 569 u32 boot_sclk; 570 u16 acpi_vddc; 571 u32 ref_div; 572 u32 active_auto_throttle_sources; 573 u32 mclk_stutter_mode_threshold; 574 u32 mclk_strobe_mode_threshold; 575 u32 mclk_edc_enable_threshold; 576 u32 bsp; 577 u32 bsu; 578 u32 pbsp; 579 u32 pbsu; 580 u32 dsp; 581 u32 psp; 582 u32 asi; 583 u32 pasi; 584 u32 vrc; 585 u32 restricted_levels; 586 u32 rlp; 587 u32 rmp; 588 u32 lhp; 589 u32 lmp; 590 /* smc offsets */ 591 u16 state_table_start; 592 u16 soft_regs_start; 593 u16 sram_end; 594 /* scratch structs */ 595 RV770_SMC_STATETABLE smc_statetable; 596}; 597 598enum si_pcie_gen { 599 SI_PCIE_GEN1 = 0, 600 SI_PCIE_GEN2 = 1, 601 SI_PCIE_GEN3 = 2, 602 SI_PCIE_GEN_INVALID = 0xffff 603}; 604 605struct rv7xx_pl { 606 u32 sclk; 607 u32 mclk; 608 u16 vddc; 609 u16 vddci; /* eg+ only */ 610 u32 flags; 611 enum si_pcie_gen pcie_gen; /* si+ only */ 612}; 613 614struct rv7xx_ps { 615 struct rv7xx_pl high; 616 struct rv7xx_pl medium; 617 struct rv7xx_pl low; 618 bool dc_compatible; 619}; 620 621struct si_ps { 622 u16 performance_level_count; 623 bool dc_compatible; 624 struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; 625}; 626 627struct ni_mc_reg_table { 628 u8 last; 629 u8 num_entries; 630 u16 valid_flag; 631 struct ni_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 632 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 633}; 634 635struct ni_cac_data 636{ 637 struct ni_leakage_coeffients leakage_coefficients; 638 u32 i_leakage; 639 s32 leakage_minimum_temperature; 640 u32 pwr_const; 641 u32 dc_cac_value; 642 u32 bif_cac_value; 643 u32 lkge_pwr; 644 u8 mc_wr_weight; 645 u8 mc_rd_weight; 646 u8 allow_ovrflw; 647 u8 num_win_tdp; 648 u8 l2num_win_tdp; 649 u8 lts_truncate_n; 650}; 651 652struct evergreen_power_info { 653 /* must be first! */ 654 struct rv7xx_power_info rv7xx; 655 /* flags */ 656 bool vddci_control; 657 bool dynamic_ac_timing; 658 bool abm; 659 bool mcls; 660 bool light_sleep; 661 bool memory_transition; 662 bool pcie_performance_request; 663 bool pcie_performance_request_registered; 664 bool sclk_deep_sleep; 665 bool dll_default_on; 666 bool ls_clock_gating; 667 bool smu_uvd_hs; 668 bool uvd_enabled; 669 /* stored values */ 670 u16 acpi_vddci; 671 u8 mvdd_high_index; 672 u8 mvdd_low_index; 673 u32 mclk_edc_wr_enable_threshold; 674 struct evergreen_mc_reg_table mc_reg_table; 675 struct atom_voltage_table vddc_voltage_table; 676 struct atom_voltage_table vddci_voltage_table; 677 struct evergreen_arb_registers bootup_arb_registers; 678 struct evergreen_ulv_param ulv; 679 struct at ats[2]; 680 /* smc offsets */ 681 u16 mc_reg_table_start; 682 struct amdgpu_ps current_rps; 683 struct rv7xx_ps current_ps; 684 struct amdgpu_ps requested_rps; 685 struct rv7xx_ps requested_ps; 686}; 687 688struct PP_NIslands_Dpm2PerfLevel 689{ 690 uint8_t MaxPS; 691 uint8_t TgtAct; 692 uint8_t MaxPS_StepInc; 693 uint8_t MaxPS_StepDec; 694 uint8_t PSST; 695 uint8_t NearTDPDec; 696 uint8_t AboveSafeInc; 697 uint8_t BelowSafeInc; 698 uint8_t PSDeltaLimit; 699 uint8_t PSDeltaWin; 700 uint8_t Reserved[6]; 701}; 702 703typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel; 704 705struct PP_NIslands_DPM2Parameters 706{ 707 uint32_t TDPLimit; 708 uint32_t NearTDPLimit; 709 uint32_t SafePowerLimit; 710 uint32_t PowerBoostLimit; 711}; 712typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters; 713 714struct NISLANDS_SMC_SCLK_VALUE 715{ 716 uint32_t vCG_SPLL_FUNC_CNTL; 717 uint32_t vCG_SPLL_FUNC_CNTL_2; 718 uint32_t vCG_SPLL_FUNC_CNTL_3; 719 uint32_t vCG_SPLL_FUNC_CNTL_4; 720 uint32_t vCG_SPLL_SPREAD_SPECTRUM; 721 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 722 uint32_t sclk_value; 723}; 724 725typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE; 726 727struct NISLANDS_SMC_MCLK_VALUE 728{ 729 uint32_t vMPLL_FUNC_CNTL; 730 uint32_t vMPLL_FUNC_CNTL_1; 731 uint32_t vMPLL_FUNC_CNTL_2; 732 uint32_t vMPLL_AD_FUNC_CNTL; 733 uint32_t vMPLL_AD_FUNC_CNTL_2; 734 uint32_t vMPLL_DQ_FUNC_CNTL; 735 uint32_t vMPLL_DQ_FUNC_CNTL_2; 736 uint32_t vMCLK_PWRMGT_CNTL; 737 uint32_t vDLL_CNTL; 738 uint32_t vMPLL_SS; 739 uint32_t vMPLL_SS2; 740 uint32_t mclk_value; 741}; 742 743typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE; 744 745struct NISLANDS_SMC_VOLTAGE_VALUE 746{ 747 uint16_t value; 748 uint8_t index; 749 uint8_t padding; 750}; 751 752typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE; 753 754struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL 755{ 756 uint8_t arbValue; 757 uint8_t ACIndex; 758 uint8_t displayWatermark; 759 uint8_t gen2PCIE; 760 uint8_t reserved1; 761 uint8_t reserved2; 762 uint8_t strobeMode; 763 uint8_t mcFlags; 764 uint32_t aT; 765 uint32_t bSP; 766 NISLANDS_SMC_SCLK_VALUE sclk; 767 NISLANDS_SMC_MCLK_VALUE mclk; 768 NISLANDS_SMC_VOLTAGE_VALUE vddc; 769 NISLANDS_SMC_VOLTAGE_VALUE mvdd; 770 NISLANDS_SMC_VOLTAGE_VALUE vddci; 771 NISLANDS_SMC_VOLTAGE_VALUE std_vddc; 772 uint32_t powergate_en; 773 uint8_t hUp; 774 uint8_t hDown; 775 uint8_t stateFlags; 776 uint8_t arbRefreshState; 777 uint32_t SQPowerThrottle; 778 uint32_t SQPowerThrottle_2; 779 uint32_t reserved[2]; 780 PP_NIslands_Dpm2PerfLevel dpm2; 781}; 782 783typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL; 784 785struct NISLANDS_SMC_SWSTATE 786{ 787 uint8_t flags; 788 uint8_t levelCount; 789 uint8_t padding2; 790 uint8_t padding3; 791 NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[]; 792}; 793 794typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE; 795 796struct NISLANDS_SMC_VOLTAGEMASKTABLE 797{ 798 uint8_t highMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 799 uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 800}; 801 802typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE; 803 804#define NISLANDS_MAX_NO_VREG_STEPS 32 805 806struct NISLANDS_SMC_STATETABLE 807{ 808 uint8_t thermalProtectType; 809 uint8_t systemFlags; 810 uint8_t maxVDDCIndexInPPTable; 811 uint8_t extraFlags; 812 uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 813 uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 814 NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; 815 PP_NIslands_DPM2Parameters dpm2Params; 816 NISLANDS_SMC_SWSTATE initialState; 817 NISLANDS_SMC_SWSTATE ACPIState; 818 NISLANDS_SMC_SWSTATE ULVState; 819 NISLANDS_SMC_SWSTATE driverState; 820 NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1]; 821}; 822 823typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE; 824 825struct ni_power_info { 826 /* must be first! */ 827 struct evergreen_power_info eg; 828 struct ni_clock_registers clock_registers; 829 struct ni_mc_reg_table mc_reg_table; 830 u32 mclk_rtt_mode_threshold; 831 /* flags */ 832 bool use_power_boost_limit; 833 bool support_cac_long_term_average; 834 bool cac_enabled; 835 bool cac_configuration_required; 836 bool driver_calculate_cac_leakage; 837 bool pc_enabled; 838 bool enable_power_containment; 839 bool enable_cac; 840 bool enable_sq_ramping; 841 /* smc offsets */ 842 u16 arb_table_start; 843 u16 fan_table_start; 844 u16 cac_table_start; 845 u16 spll_table_start; 846 /* CAC stuff */ 847 struct ni_cac_data cac_data; 848 u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS]; 849 const struct ni_cac_weights *cac_weights; 850 u8 lta_window_size; 851 u8 lts_truncate; 852 struct si_ps current_ps; 853 struct si_ps requested_ps; 854 /* scratch structs */ 855 SMC_NIslands_MCRegisters smc_mc_reg_table; 856 NISLANDS_SMC_STATETABLE smc_statetable; 857}; 858 859struct si_cac_config_reg 860{ 861 u32 offset; 862 u32 mask; 863 u32 shift; 864 u32 value; 865 enum si_cac_config_reg_type type; 866}; 867 868struct si_powertune_data 869{ 870 u32 cac_window; 871 u32 l2_lta_window_size_default; 872 u8 lts_truncate_default; 873 u8 shift_n_default; 874 u8 operating_temp; 875 struct ni_leakage_coeffients leakage_coefficients; 876 u32 fixed_kt; 877 u32 lkge_lut_v0_percent; 878 u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS]; 879 bool enable_powertune_by_default; 880}; 881 882struct si_dyn_powertune_data 883{ 884 u32 cac_leakage; 885 s32 leakage_minimum_temperature; 886 u32 wintime; 887 u32 l2_lta_window_size; 888 u8 lts_truncate; 889 u8 shift_n; 890 u8 dc_pwr_value; 891 bool disable_uvd_powertune; 892}; 893 894struct si_dte_data 895{ 896 u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 897 u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 898 u32 k; 899 u32 t0; 900 u32 max_t; 901 u8 window_size; 902 u8 temp_select; 903 u8 dte_mode; 904 u8 tdep_count; 905 u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 906 u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 907 u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 908 u32 t_threshold; 909 bool enable_dte_by_default; 910}; 911 912struct si_clock_registers { 913 u32 cg_spll_func_cntl; 914 u32 cg_spll_func_cntl_2; 915 u32 cg_spll_func_cntl_3; 916 u32 cg_spll_func_cntl_4; 917 u32 cg_spll_spread_spectrum; 918 u32 cg_spll_spread_spectrum_2; 919 u32 dll_cntl; 920 u32 mclk_pwrmgt_cntl; 921 u32 mpll_ad_func_cntl; 922 u32 mpll_dq_func_cntl; 923 u32 mpll_func_cntl; 924 u32 mpll_func_cntl_1; 925 u32 mpll_func_cntl_2; 926 u32 mpll_ss1; 927 u32 mpll_ss2; 928}; 929 930struct si_mc_reg_entry { 931 u32 mclk_max; 932 u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 933}; 934 935struct si_mc_reg_table { 936 u8 last; 937 u8 num_entries; 938 u16 valid_flag; 939 struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 940 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 941}; 942 943struct si_leakage_voltage_entry 944{ 945 u16 voltage; 946 u16 leakage_index; 947}; 948 949struct si_leakage_voltage 950{ 951 u16 count; 952 struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT]; 953}; 954 955 956struct si_ulv_param { 957 bool supported; 958 u32 cg_ulv_control; 959 u32 cg_ulv_parameter; 960 u32 volt_change_delay; 961 struct rv7xx_pl pl; 962 bool one_pcie_lane_in_ulv; 963}; 964 965struct si_power_info { 966 /* must be first! */ 967 struct ni_power_info ni; 968 struct si_clock_registers clock_registers; 969 struct si_mc_reg_table mc_reg_table; 970 struct atom_voltage_table mvdd_voltage_table; 971 struct atom_voltage_table vddc_phase_shed_table; 972 struct si_leakage_voltage leakage_voltage; 973 u16 mvdd_bootup_value; 974 struct si_ulv_param ulv; 975 u32 max_cu; 976 /* pcie gen */ 977 enum si_pcie_gen force_pcie_gen; 978 enum si_pcie_gen boot_pcie_gen; 979 enum si_pcie_gen acpi_pcie_gen; 980 u32 sys_pcie_mask; 981 /* flags */ 982 bool enable_dte; 983 bool enable_ppm; 984 bool vddc_phase_shed_control; 985 bool pspp_notify_required; 986 bool sclk_deep_sleep_above_low; 987 bool voltage_control_svi2; 988 bool vddci_control_svi2; 989 /* smc offsets */ 990 u32 sram_end; 991 u32 state_table_start; 992 u32 soft_regs_start; 993 u32 mc_reg_table_start; 994 u32 arb_table_start; 995 u32 cac_table_start; 996 u32 dte_table_start; 997 u32 spll_table_start; 998 u32 papm_cfg_table_start; 999 u32 fan_table_start; 1000 /* CAC stuff */ 1001 const struct si_cac_config_reg *cac_weights; 1002 const struct si_cac_config_reg *lcac_config; 1003 const struct si_cac_config_reg *cac_override; 1004 const struct si_powertune_data *powertune_data; 1005 struct si_dyn_powertune_data dyn_powertune_data; 1006 /* DTE stuff */ 1007 struct si_dte_data dte_data; 1008 /* scratch structs */ 1009 SMC_SIslands_MCRegisters smc_mc_reg_table; 1010 SISLANDS_SMC_STATETABLE smc_statetable; 1011 PP_SIslands_PAPMParameters papm_parm; 1012 /* SVI2 */ 1013 u8 svd_gpio_id; 1014 u8 svc_gpio_id; 1015 /* fan control */ 1016 bool fan_ctrl_is_in_default_mode; 1017 u32 t_min; 1018 u32 fan_ctrl_default_mode; 1019 bool fan_is_controlled_by_smc; 1020}; 1021 1022#endif 1023