Searched refs:intr (Results 201 - 225 of 528) sorted by last modified time

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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Drunl.h3 #include <core/intr.h>
H A Dpriv.h26 irqreturn_t (*intr)(struct nvkm_inth *); member in struct:nvkm_fifo_func
H A Dbase.c278 if (fifo->func->intr) {
279 ret = nvkm_inth_add(&device->mc->intr, NVKM_INTR_SUBDEV, NVKM_INTR_PRIO_NORMAL,
280 subdev, fifo->func->intr, &subdev->inth);
282 nvkm_error(subdev, "intr %d\n", ret);
287 /* Initialise non-stall intr handling. */
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/
H A Dfalcon.c66 u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16); local
73 if (intr & 0x00000040) {
74 if (falcon->func->intr) {
75 falcon->func->intr(falcon, chan);
77 intr &= ~0x00000040;
81 if (intr & 0x00000010) {
84 intr &= ~0x00000010;
87 if (intr) {
88 nvkm_error(subdev, "intr %08x\n", intr);
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dtu102.c215 .intr = gv100_disp_intr,
H A Dpriv.h25 void (*intr)(struct nvkm_disp *); member in struct:nvkm_disp_func
H A Dnv50.c621 .intr = nv50_disp_chan_intr,
710 .intr = nv50_disp_chan_intr,
1000 .intr = nv50_disp_chan_intr,
1772 .intr = nv50_disp_intr,
H A Dgv100.c406 .intr = gv100_disp_wimm_intr,
532 .intr = gv100_disp_wndw_intr,
599 .intr = gv100_disp_curs_intr,
781 .intr = gv100_disp_core_intr,
1114 nvkm_warn(subdev, "intr %08x\n", stat);
1231 .intr = gv100_disp_intr,
H A Dgf119.c563 .intr = gf119_disp_chan_intr,
630 .intr = gf119_disp_chan_intr,
997 .intr = gf119_disp_chan_intr,
1106 u32 intr = nvkm_rd32(device, 0x610088); local
1108 if (intr & 0x00000001) {
1115 intr &= ~0x00000001;
1118 if (intr & 0x00000002) {
1123 intr &= ~0x00000002;
1126 if (intr & 0x00100000) {
1140 intr
[all...]
H A Dga102.c129 .intr = gv100_disp_intr,
H A Dchan.h39 void (*intr)(struct nvkm_disp_chan *, bool en); member in struct:nvkm_disp_chan_func
H A Dmcp89.c64 .intr = nv50_disp_intr,
H A Dgt215.c244 .intr = nv50_disp_intr,
H A Dgp100.c63 .intr = gf119_disp_intr,
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A Dtu102.c30 .intr = gp100_ce_intr,
H A Dga100.c35 nvkm_error(subdev, "intr\n");
71 return nvkm_inth_add(&device->vfn->intr, vector, NVKM_INTR_PRIO_NORMAL,
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/engine/
H A Dfifo.h71 struct nvkm_inth intr; member in struct:nvkm_fifo::__anon144
H A Dfalcon.h73 int (*bind_stat)(struct nvkm_falcon *, bool intr);
103 void (*intr)(struct nvkm_falcon *, struct nvkm_chan *); member in struct:nvkm_falcon_func
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Ddevice.h5 #include <core/intr.h>
67 struct list_head intr; member in struct:nvkm_device::__anon129
74 } intr; member in struct:nvkm_device
/linux-master/arch/powerpc/platforms/8xx/
H A Dcpm1.c144 __be16 dir, par, odr_sor, dat, intr; member in struct:cpm_ioport16
230 setbits16(&iop->intr, pin);
232 clrbits16(&iop->intr, pin);
/linux-master/sound/soc/fsl/
H A Dfsl_spdif.c741 u32 intr = SIE_INTR_FOR(tx); local
748 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
755 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
840 /* Clear intr */
/linux-master/include/trace/events/
H A Dufs.h272 u32 intr, u64 lba, u8 opcode, u8 group_id),
274 TP_ARGS(sdev, str_t, tag, doorbell, hwq_id, transfer_len, intr, lba,
283 __field(u32, intr)
296 __entry->intr = intr;
307 __entry->doorbell, __entry->transfer_len, __entry->intr,
/linux-master/include/linux/
H A Dkey.h385 extern int wait_for_key_construction(struct key *key, bool intr);
/linux-master/drivers/scsi/
H A Dips.c596 ha->func.intr = ips_intr_morpheus;
606 ha->func.intr = ips_intr_copperhead;
623 ha->func.intr = ips_intr_copperhead;
1219 (*ha->func.intr) (ha);
1230 irqstatus = (*ha->func.intr) (ha);
1542 ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr) argument
2213 ips_get_bios_version(ips_ha_t * ha, int intr) argument
2334 intr)) == IPS_FAILURE)
2507 ips_next(ips_ha_t * ha, int intr) argument
2525 if (intr
3368 ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr) argument
5516 ips_wait(ips_ha_t * ha, int time, int intr) argument
5574 ips_write_driver_status(ips_ha_t * ha, int intr) argument
5639 ips_read_adapter_status(ips_ha_t * ha, int intr) argument
5682 ips_read_subsystem_parameters(ips_ha_t * ha, int intr) argument
5726 ips_read_config(ips_ha_t * ha, int intr) argument
5784 ips_readwrite_page5(ips_ha_t * ha, int write, int intr) argument
5834 ips_clear_adapter(ips_ha_t * ha, int intr) argument
5897 ips_ffdc_reset(ips_ha_t * ha, int intr) argument
[all...]
/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_fence.c465 * @intr: use interruptable sleep
470 * @intr selects whether to use interruptable (true) or non-interruptable
478 u64 *target_seq, bool intr,
496 if (intr) {
524 * @intr: use interruptible sleep
527 * @intr selects whether to use interruptable (true) or non-interruptable
533 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool intr, long timeout)
545 return dma_fence_wait(&fence->base, intr);
548 r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, timeout);
560 * @intr
476 radeon_fence_wait_seq_timeout(struct radeon_device *rdev, u64 *target_seq, bool intr, long timeout) argument
532 radeon_fence_wait_timeout(struct radeon_fence *fence, bool intr, long timeout) argument
566 radeon_fence_wait(struct radeon_fence *fence, bool intr) argument
589 radeon_fence_wait_any(struct radeon_device *rdev, struct radeon_fence **fences, bool intr) argument
1051 radeon_fence_default_wait(struct dma_fence *f, bool intr, signed long t) argument
[all...]

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