1/* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22#include "priv.h" 23#include "chan.h" 24#include "hdmi.h" 25#include "head.h" 26#include "ior.h" 27#include "outp.h" 28 29#include <core/client.h> 30#include <core/gpuobj.h> 31#include <core/ramht.h> 32#include <subdev/timer.h> 33 34#include <nvif/class.h> 35#include <nvif/unpack.h> 36 37static void 38gv100_sor_hda_device_entry(struct nvkm_ior *ior, int head) 39{ 40 struct nvkm_device *device = ior->disp->engine.subdev.device; 41 const u32 hoff = 0x800 * head; 42 43 nvkm_mask(device, 0x616528 + hoff, 0x00000070, head << 4); 44} 45 46const struct nvkm_ior_func_hda 47gv100_sor_hda = { 48 .hpd = gf119_sor_hda_hpd, 49 .eld = gf119_sor_hda_eld, 50 .device_entry = gv100_sor_hda_device_entry, 51}; 52 53void 54gv100_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark) 55{ 56 struct nvkm_device *device = sor->disp->engine.subdev.device; 57 const u32 hoff = head * 0x800; 58 59 nvkm_mask(device, 0x616550 + hoff, 0x0c00003f, 0x08000000 | watermark); 60} 61 62void 63gv100_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v) 64{ 65 struct nvkm_device *device = sor->disp->engine.subdev.device; 66 const u32 hoff = head * 0x800; 67 68 nvkm_mask(device, 0x616568 + hoff, 0x0000ffff, h); 69 nvkm_mask(device, 0x61656c + hoff, 0x00ffffff, v); 70} 71 72void 73gv100_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable) 74{ 75 struct nvkm_device *device = sor->disp->engine.subdev.device; 76 const u32 hoff = 0x800 * head; 77 const u32 data = 0x80000000 | (0x00000001 * enable); 78 const u32 mask = 0x8000000d; 79 80 nvkm_mask(device, 0x616560 + hoff, mask, data); 81 nvkm_msec(device, 2000, 82 if (!(nvkm_rd32(device, 0x616560 + hoff) & 0x80000000)) 83 break; 84 ); 85} 86 87static const struct nvkm_ior_func_dp 88gv100_sor_dp = { 89 .lanes = { 0, 1, 2, 3 }, 90 .links = gf119_sor_dp_links, 91 .power = g94_sor_dp_power, 92 .pattern = gm107_sor_dp_pattern, 93 .drive = gm200_sor_dp_drive, 94 .audio = gv100_sor_dp_audio, 95 .audio_sym = gv100_sor_dp_audio_sym, 96 .watermark = gv100_sor_dp_watermark, 97}; 98 99void 100gv100_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior, int head, void *data, u32 size) 101{ 102 struct nvkm_device *device = ior->disp->engine.subdev.device; 103 struct packed_hdmi_infoframe vsi; 104 const u32 hoff = head * 0x400; 105 106 pack_hdmi_infoframe(&vsi, data, size); 107 108 nvkm_mask(device, 0x6f0100 + hoff, 0x00010001, 0x00000000); 109 if (!size) 110 return; 111 112 nvkm_wr32(device, 0x6f0108 + hoff, vsi.header); 113 nvkm_wr32(device, 0x6f010c + hoff, vsi.subpack0_low); 114 nvkm_wr32(device, 0x6f0110 + hoff, vsi.subpack0_high); 115 nvkm_wr32(device, 0x6f0114 + hoff, 0x00000000); 116 nvkm_wr32(device, 0x6f0118 + hoff, 0x00000000); 117 nvkm_wr32(device, 0x6f011c + hoff, 0x00000000); 118 nvkm_wr32(device, 0x6f0120 + hoff, 0x00000000); 119 nvkm_wr32(device, 0x6f0124 + hoff, 0x00000000); 120 nvkm_mask(device, 0x6f0100 + hoff, 0x00000001, 0x00000001); 121} 122 123void 124gv100_sor_hdmi_infoframe_avi(struct nvkm_ior *ior, int head, void *data, u32 size) 125{ 126 struct nvkm_device *device = ior->disp->engine.subdev.device; 127 struct packed_hdmi_infoframe avi; 128 const u32 hoff = head * 0x400; 129 130 pack_hdmi_infoframe(&avi, data, size); 131 132 nvkm_mask(device, 0x6f0000 + hoff, 0x00000001, 0x00000000); 133 if (!size) 134 return; 135 136 nvkm_wr32(device, 0x6f0008 + hoff, avi.header); 137 nvkm_wr32(device, 0x6f000c + hoff, avi.subpack0_low); 138 nvkm_wr32(device, 0x6f0010 + hoff, avi.subpack0_high); 139 nvkm_wr32(device, 0x6f0014 + hoff, avi.subpack1_low); 140 nvkm_wr32(device, 0x6f0018 + hoff, avi.subpack1_high); 141 142 nvkm_mask(device, 0x6f0000 + hoff, 0x00000001, 0x00000001); 143} 144 145static void 146gv100_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet, u8 rekey) 147{ 148 struct nvkm_device *device = ior->disp->engine.subdev.device; 149 const u32 ctrl = 0x40000000 * enable | 150 max_ac_packet << 16 | 151 rekey; 152 const u32 hoff = head * 0x800; 153 const u32 hdmi = head * 0x400; 154 155 if (!(ctrl & 0x40000000)) { 156 nvkm_mask(device, 0x6165c0 + hoff, 0x40000000, 0x00000000); 157 nvkm_mask(device, 0x6f0100 + hdmi, 0x00000001, 0x00000000); 158 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000000); 159 nvkm_mask(device, 0x6f0000 + hdmi, 0x00000001, 0x00000000); 160 return; 161 } 162 163 /* General Control (GCP). */ 164 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000000); 165 nvkm_wr32(device, 0x6f00cc + hdmi, 0x00000010); 166 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000001); 167 168 /* Audio Clock Regeneration (ACR). */ 169 nvkm_wr32(device, 0x6f0080 + hdmi, 0x82000000); 170 171 /* NV_PDISP_SF_HDMI_CTRL. */ 172 nvkm_mask(device, 0x6165c0 + hoff, 0x401f007f, ctrl); 173} 174 175const struct nvkm_ior_func_hdmi 176gv100_sor_hdmi = { 177 .ctrl = gv100_sor_hdmi_ctrl, 178 .scdc = gm200_sor_hdmi_scdc, 179 .infoframe_avi = gv100_sor_hdmi_infoframe_avi, 180 .infoframe_vsi = gv100_sor_hdmi_infoframe_vsi, 181}; 182 183void 184gv100_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state) 185{ 186 struct nvkm_device *device = sor->disp->engine.subdev.device; 187 const u32 coff = (state == &sor->arm) * 0x8000 + sor->id * 0x20; 188 u32 ctrl = nvkm_rd32(device, 0x680300 + coff); 189 190 state->proto_evo = (ctrl & 0x00000f00) >> 8; 191 switch (state->proto_evo) { 192 case 0: state->proto = LVDS; state->link = 1; break; 193 case 1: state->proto = TMDS; state->link = 1; break; 194 case 2: state->proto = TMDS; state->link = 2; break; 195 case 5: state->proto = TMDS; state->link = 3; break; 196 case 8: state->proto = DP; state->link = 1; break; 197 case 9: state->proto = DP; state->link = 2; break; 198 default: 199 state->proto = UNKNOWN; 200 break; 201 } 202 203 state->head = ctrl & 0x000000ff; 204} 205 206static const struct nvkm_ior_func 207gv100_sor = { 208 .route = { 209 .get = gm200_sor_route_get, 210 .set = gm200_sor_route_set, 211 }, 212 .state = gv100_sor_state, 213 .power = nv50_sor_power, 214 .clock = gf119_sor_clock, 215 .bl = >215_sor_bl, 216 .hdmi = &gv100_sor_hdmi, 217 .dp = &gv100_sor_dp, 218 .hda = &gv100_sor_hda, 219}; 220 221static int 222gv100_sor_new(struct nvkm_disp *disp, int id) 223{ 224 struct nvkm_device *device = disp->engine.subdev.device; 225 u32 hda; 226 227 if (!((hda = nvkm_rd32(device, 0x08a15c)) & 0x40000000)) 228 hda = nvkm_rd32(device, 0x118fb0) >> 8; 229 230 return nvkm_ior_new_(&gv100_sor, disp, SOR, id, hda & BIT(id)); 231} 232 233int 234gv100_sor_cnt(struct nvkm_disp *disp, unsigned long *pmask) 235{ 236 struct nvkm_device *device = disp->engine.subdev.device; 237 238 *pmask = (nvkm_rd32(device, 0x610060) & 0x0000ff00) >> 8; 239 return (nvkm_rd32(device, 0x610074) & 0x00000f00) >> 8; 240} 241 242static void 243gv100_head_vblank_put(struct nvkm_head *head) 244{ 245 struct nvkm_device *device = head->disp->engine.subdev.device; 246 nvkm_mask(device, 0x611d80 + (head->id * 4), 0x00000004, 0x00000000); 247} 248 249static void 250gv100_head_vblank_get(struct nvkm_head *head) 251{ 252 struct nvkm_device *device = head->disp->engine.subdev.device; 253 nvkm_mask(device, 0x611d80 + (head->id * 4), 0x00000004, 0x00000004); 254} 255 256static void 257gv100_head_rgpos(struct nvkm_head *head, u16 *hline, u16 *vline) 258{ 259 struct nvkm_device *device = head->disp->engine.subdev.device; 260 const u32 hoff = head->id * 0x800; 261 /* vline read locks hline. */ 262 *vline = nvkm_rd32(device, 0x616330 + hoff) & 0x0000ffff; 263 *hline = nvkm_rd32(device, 0x616334 + hoff) & 0x0000ffff; 264} 265 266static void 267gv100_head_state(struct nvkm_head *head, struct nvkm_head_state *state) 268{ 269 struct nvkm_device *device = head->disp->engine.subdev.device; 270 const u32 hoff = (state == &head->arm) * 0x8000 + head->id * 0x400; 271 u32 data; 272 273 data = nvkm_rd32(device, 0x682064 + hoff); 274 state->vtotal = (data & 0xffff0000) >> 16; 275 state->htotal = (data & 0x0000ffff); 276 data = nvkm_rd32(device, 0x682068 + hoff); 277 state->vsynce = (data & 0xffff0000) >> 16; 278 state->hsynce = (data & 0x0000ffff); 279 data = nvkm_rd32(device, 0x68206c + hoff); 280 state->vblanke = (data & 0xffff0000) >> 16; 281 state->hblanke = (data & 0x0000ffff); 282 data = nvkm_rd32(device, 0x682070 + hoff); 283 state->vblanks = (data & 0xffff0000) >> 16; 284 state->hblanks = (data & 0x0000ffff); 285 state->hz = nvkm_rd32(device, 0x68200c + hoff); 286 287 data = nvkm_rd32(device, 0x682004 + hoff); 288 switch ((data & 0x000000f0) >> 4) { 289 case 5: state->or.depth = 30; break; 290 case 4: state->or.depth = 24; break; 291 case 1: state->or.depth = 18; break; 292 default: 293 state->or.depth = 18; 294 WARN_ON(1); 295 break; 296 } 297} 298 299static const struct nvkm_head_func 300gv100_head = { 301 .state = gv100_head_state, 302 .rgpos = gv100_head_rgpos, 303 .rgclk = gf119_head_rgclk, 304 .vblank_get = gv100_head_vblank_get, 305 .vblank_put = gv100_head_vblank_put, 306}; 307 308int 309gv100_head_new(struct nvkm_disp *disp, int id) 310{ 311 struct nvkm_device *device = disp->engine.subdev.device; 312 313 if (!(nvkm_rd32(device, 0x610060) & (0x00000001 << id))) 314 return 0; 315 316 return nvkm_head_new_(&gv100_head, disp, id); 317} 318 319int 320gv100_head_cnt(struct nvkm_disp *disp, unsigned long *pmask) 321{ 322 struct nvkm_device *device = disp->engine.subdev.device; 323 324 *pmask = nvkm_rd32(device, 0x610060) & 0x000000ff; 325 return nvkm_rd32(device, 0x610074) & 0x0000000f; 326} 327 328const struct nvkm_event_func 329gv100_disp_chan_uevent = { 330}; 331 332u64 333gv100_disp_chan_user(struct nvkm_disp_chan *chan, u64 *psize) 334{ 335 *psize = 0x1000; 336 return 0x690000 + ((chan->chid.user - 1) * 0x1000); 337} 338 339static int 340gv100_disp_dmac_idle(struct nvkm_disp_chan *chan) 341{ 342 struct nvkm_device *device = chan->disp->engine.subdev.device; 343 const u32 soff = (chan->chid.ctrl - 1) * 0x04; 344 nvkm_msec(device, 2000, 345 u32 stat = nvkm_rd32(device, 0x610664 + soff); 346 if ((stat & 0x000f0000) == 0x00040000) 347 return 0; 348 ); 349 return -EBUSY; 350} 351 352int 353gv100_disp_dmac_bind(struct nvkm_disp_chan *chan, 354 struct nvkm_object *object, u32 handle) 355{ 356 return nvkm_ramht_insert(chan->disp->ramht, object, chan->chid.user, -9, handle, 357 chan->chid.user << 25 | 0x00000040); 358} 359 360void 361gv100_disp_dmac_fini(struct nvkm_disp_chan *chan) 362{ 363 struct nvkm_device *device = chan->disp->engine.subdev.device; 364 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; 365 const u32 coff = chan->chid.ctrl * 0x04; 366 nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000000); 367 gv100_disp_dmac_idle(chan); 368 nvkm_mask(device, 0x6104e0 + coff, 0x00000002, 0x00000000); 369 chan->suspend_put = nvkm_rd32(device, 0x690000 + uoff); 370} 371 372int 373gv100_disp_dmac_init(struct nvkm_disp_chan *chan) 374{ 375 struct nvkm_subdev *subdev = &chan->disp->engine.subdev; 376 struct nvkm_device *device = subdev->device; 377 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; 378 const u32 poff = chan->chid.ctrl * 0x10; 379 const u32 coff = chan->chid.ctrl * 0x04; 380 381 nvkm_wr32(device, 0x610b24 + poff, lower_32_bits(chan->push)); 382 nvkm_wr32(device, 0x610b20 + poff, upper_32_bits(chan->push)); 383 nvkm_wr32(device, 0x610b28 + poff, 0x00000001); 384 nvkm_wr32(device, 0x610b2c + poff, 0x00000040); 385 386 nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000010); 387 nvkm_wr32(device, 0x690000 + uoff, chan->suspend_put); 388 nvkm_wr32(device, 0x6104e0 + coff, 0x00000013); 389 return gv100_disp_dmac_idle(chan); 390} 391 392static void 393gv100_disp_wimm_intr(struct nvkm_disp_chan *chan, bool en) 394{ 395 struct nvkm_device *device = chan->disp->engine.subdev.device; 396 const u32 mask = 0x00000001 << chan->head; 397 const u32 data = en ? mask : 0; 398 nvkm_mask(device, 0x611da8, mask, data); 399} 400 401static const struct nvkm_disp_chan_func 402gv100_disp_wimm_func = { 403 .push = nv50_disp_dmac_push, 404 .init = gv100_disp_dmac_init, 405 .fini = gv100_disp_dmac_fini, 406 .intr = gv100_disp_wimm_intr, 407 .user = gv100_disp_chan_user, 408}; 409 410const struct nvkm_disp_chan_user 411gv100_disp_wimm = { 412 .func = &gv100_disp_wimm_func, 413 .ctrl = 33, 414 .user = 33, 415}; 416 417static const struct nvkm_disp_mthd_list 418gv100_disp_wndw_mthd_base = { 419 .mthd = 0x0000, 420 .addr = 0x000000, 421 .data = { 422 { 0x0200, 0x690200 }, 423 { 0x020c, 0x69020c }, 424 { 0x0210, 0x690210 }, 425 { 0x0214, 0x690214 }, 426 { 0x0218, 0x690218 }, 427 { 0x021c, 0x69021c }, 428 { 0x0220, 0x690220 }, 429 { 0x0224, 0x690224 }, 430 { 0x0228, 0x690228 }, 431 { 0x022c, 0x69022c }, 432 { 0x0230, 0x690230 }, 433 { 0x0234, 0x690234 }, 434 { 0x0238, 0x690238 }, 435 { 0x0240, 0x690240 }, 436 { 0x0244, 0x690244 }, 437 { 0x0248, 0x690248 }, 438 { 0x024c, 0x69024c }, 439 { 0x0250, 0x690250 }, 440 { 0x0254, 0x690254 }, 441 { 0x0260, 0x690260 }, 442 { 0x0264, 0x690264 }, 443 { 0x0268, 0x690268 }, 444 { 0x026c, 0x69026c }, 445 { 0x0270, 0x690270 }, 446 { 0x0274, 0x690274 }, 447 { 0x0280, 0x690280 }, 448 { 0x0284, 0x690284 }, 449 { 0x0288, 0x690288 }, 450 { 0x028c, 0x69028c }, 451 { 0x0290, 0x690290 }, 452 { 0x0298, 0x690298 }, 453 { 0x029c, 0x69029c }, 454 { 0x02a0, 0x6902a0 }, 455 { 0x02a4, 0x6902a4 }, 456 { 0x02a8, 0x6902a8 }, 457 { 0x02ac, 0x6902ac }, 458 { 0x02b0, 0x6902b0 }, 459 { 0x02b4, 0x6902b4 }, 460 { 0x02b8, 0x6902b8 }, 461 { 0x02bc, 0x6902bc }, 462 { 0x02c0, 0x6902c0 }, 463 { 0x02c4, 0x6902c4 }, 464 { 0x02c8, 0x6902c8 }, 465 { 0x02cc, 0x6902cc }, 466 { 0x02d0, 0x6902d0 }, 467 { 0x02d4, 0x6902d4 }, 468 { 0x02d8, 0x6902d8 }, 469 { 0x02dc, 0x6902dc }, 470 { 0x02e0, 0x6902e0 }, 471 { 0x02e4, 0x6902e4 }, 472 { 0x02e8, 0x6902e8 }, 473 { 0x02ec, 0x6902ec }, 474 { 0x02f0, 0x6902f0 }, 475 { 0x02f4, 0x6902f4 }, 476 { 0x02f8, 0x6902f8 }, 477 { 0x02fc, 0x6902fc }, 478 { 0x0300, 0x690300 }, 479 { 0x0304, 0x690304 }, 480 { 0x0308, 0x690308 }, 481 { 0x0310, 0x690310 }, 482 { 0x0314, 0x690314 }, 483 { 0x0318, 0x690318 }, 484 { 0x031c, 0x69031c }, 485 { 0x0320, 0x690320 }, 486 { 0x0324, 0x690324 }, 487 { 0x0328, 0x690328 }, 488 { 0x032c, 0x69032c }, 489 { 0x033c, 0x69033c }, 490 { 0x0340, 0x690340 }, 491 { 0x0344, 0x690344 }, 492 { 0x0348, 0x690348 }, 493 { 0x034c, 0x69034c }, 494 { 0x0350, 0x690350 }, 495 { 0x0354, 0x690354 }, 496 { 0x0358, 0x690358 }, 497 { 0x0364, 0x690364 }, 498 { 0x0368, 0x690368 }, 499 { 0x036c, 0x69036c }, 500 { 0x0370, 0x690370 }, 501 { 0x0374, 0x690374 }, 502 { 0x0380, 0x690380 }, 503 {} 504 } 505}; 506 507static const struct nvkm_disp_chan_mthd 508gv100_disp_wndw_mthd = { 509 .name = "Window", 510 .addr = 0x001000, 511 .prev = 0x000800, 512 .data = { 513 { "Global", 1, &gv100_disp_wndw_mthd_base }, 514 {} 515 } 516}; 517 518static void 519gv100_disp_wndw_intr(struct nvkm_disp_chan *chan, bool en) 520{ 521 struct nvkm_device *device = chan->disp->engine.subdev.device; 522 const u32 mask = 0x00000001 << chan->head; 523 const u32 data = en ? mask : 0; 524 nvkm_mask(device, 0x611da4, mask, data); 525} 526 527static const struct nvkm_disp_chan_func 528gv100_disp_wndw_func = { 529 .push = nv50_disp_dmac_push, 530 .init = gv100_disp_dmac_init, 531 .fini = gv100_disp_dmac_fini, 532 .intr = gv100_disp_wndw_intr, 533 .user = gv100_disp_chan_user, 534 .bind = gv100_disp_dmac_bind, 535}; 536 537const struct nvkm_disp_chan_user 538gv100_disp_wndw = { 539 .func = &gv100_disp_wndw_func, 540 .ctrl = 1, 541 .user = 1, 542 .mthd = &gv100_disp_wndw_mthd, 543}; 544 545int 546gv100_disp_wndw_cnt(struct nvkm_disp *disp, unsigned long *pmask) 547{ 548 struct nvkm_device *device = disp->engine.subdev.device; 549 550 *pmask = nvkm_rd32(device, 0x610064); 551 return (nvkm_rd32(device, 0x610074) & 0x03f00000) >> 20; 552} 553 554static int 555gv100_disp_curs_idle(struct nvkm_disp_chan *chan) 556{ 557 struct nvkm_device *device = chan->disp->engine.subdev.device; 558 const u32 soff = (chan->chid.ctrl - 1) * 0x04; 559 nvkm_msec(device, 2000, 560 u32 stat = nvkm_rd32(device, 0x610664 + soff); 561 if ((stat & 0x00070000) == 0x00040000) 562 return 0; 563 ); 564 return -EBUSY; 565} 566 567static void 568gv100_disp_curs_intr(struct nvkm_disp_chan *chan, bool en) 569{ 570 struct nvkm_device *device = chan->disp->engine.subdev.device; 571 const u32 mask = 0x00010000 << chan->head; 572 const u32 data = en ? mask : 0; 573 nvkm_mask(device, 0x611dac, mask, data); 574} 575 576static void 577gv100_disp_curs_fini(struct nvkm_disp_chan *chan) 578{ 579 struct nvkm_device *device = chan->disp->engine.subdev.device; 580 const u32 hoff = chan->chid.ctrl * 4; 581 nvkm_mask(device, 0x6104e0 + hoff, 0x00000010, 0x00000010); 582 gv100_disp_curs_idle(chan); 583 nvkm_mask(device, 0x6104e0 + hoff, 0x00000001, 0x00000000); 584} 585 586static int 587gv100_disp_curs_init(struct nvkm_disp_chan *chan) 588{ 589 struct nvkm_subdev *subdev = &chan->disp->engine.subdev; 590 struct nvkm_device *device = subdev->device; 591 nvkm_wr32(device, 0x6104e0 + chan->chid.ctrl * 4, 0x00000001); 592 return gv100_disp_curs_idle(chan); 593} 594 595static const struct nvkm_disp_chan_func 596gv100_disp_curs_func = { 597 .init = gv100_disp_curs_init, 598 .fini = gv100_disp_curs_fini, 599 .intr = gv100_disp_curs_intr, 600 .user = gv100_disp_chan_user, 601}; 602 603const struct nvkm_disp_chan_user 604gv100_disp_curs = { 605 .func = &gv100_disp_curs_func, 606 .ctrl = 73, 607 .user = 73, 608}; 609 610static const struct nvkm_disp_mthd_list 611gv100_disp_core_mthd_base = { 612 .mthd = 0x0000, 613 .addr = 0x000000, 614 .data = { 615 { 0x0200, 0x680200 }, 616 { 0x0208, 0x680208 }, 617 { 0x020c, 0x68020c }, 618 { 0x0210, 0x680210 }, 619 { 0x0214, 0x680214 }, 620 { 0x0218, 0x680218 }, 621 { 0x021c, 0x68021c }, 622 {} 623 } 624}; 625 626static const struct nvkm_disp_mthd_list 627gv100_disp_core_mthd_sor = { 628 .mthd = 0x0020, 629 .addr = 0x000020, 630 .data = { 631 { 0x0300, 0x680300 }, 632 { 0x0304, 0x680304 }, 633 { 0x0308, 0x680308 }, 634 { 0x030c, 0x68030c }, 635 {} 636 } 637}; 638 639static const struct nvkm_disp_mthd_list 640gv100_disp_core_mthd_wndw = { 641 .mthd = 0x0080, 642 .addr = 0x000080, 643 .data = { 644 { 0x1000, 0x681000 }, 645 { 0x1004, 0x681004 }, 646 { 0x1008, 0x681008 }, 647 { 0x100c, 0x68100c }, 648 { 0x1010, 0x681010 }, 649 {} 650 } 651}; 652 653static const struct nvkm_disp_mthd_list 654gv100_disp_core_mthd_head = { 655 .mthd = 0x0400, 656 .addr = 0x000400, 657 .data = { 658 { 0x2000, 0x682000 }, 659 { 0x2004, 0x682004 }, 660 { 0x2008, 0x682008 }, 661 { 0x200c, 0x68200c }, 662 { 0x2014, 0x682014 }, 663 { 0x2018, 0x682018 }, 664 { 0x201c, 0x68201c }, 665 { 0x2020, 0x682020 }, 666 { 0x2028, 0x682028 }, 667 { 0x202c, 0x68202c }, 668 { 0x2030, 0x682030 }, 669 { 0x2038, 0x682038 }, 670 { 0x203c, 0x68203c }, 671 { 0x2048, 0x682048 }, 672 { 0x204c, 0x68204c }, 673 { 0x2050, 0x682050 }, 674 { 0x2054, 0x682054 }, 675 { 0x2058, 0x682058 }, 676 { 0x205c, 0x68205c }, 677 { 0x2060, 0x682060 }, 678 { 0x2064, 0x682064 }, 679 { 0x2068, 0x682068 }, 680 { 0x206c, 0x68206c }, 681 { 0x2070, 0x682070 }, 682 { 0x2074, 0x682074 }, 683 { 0x2078, 0x682078 }, 684 { 0x207c, 0x68207c }, 685 { 0x2080, 0x682080 }, 686 { 0x2088, 0x682088 }, 687 { 0x2090, 0x682090 }, 688 { 0x209c, 0x68209c }, 689 { 0x20a0, 0x6820a0 }, 690 { 0x20a4, 0x6820a4 }, 691 { 0x20a8, 0x6820a8 }, 692 { 0x20ac, 0x6820ac }, 693 { 0x2180, 0x682180 }, 694 { 0x2184, 0x682184 }, 695 { 0x218c, 0x68218c }, 696 { 0x2194, 0x682194 }, 697 { 0x2198, 0x682198 }, 698 { 0x219c, 0x68219c }, 699 { 0x21a0, 0x6821a0 }, 700 { 0x21a4, 0x6821a4 }, 701 { 0x2214, 0x682214 }, 702 { 0x2218, 0x682218 }, 703 {} 704 } 705}; 706 707static const struct nvkm_disp_chan_mthd 708gv100_disp_core_mthd = { 709 .name = "Core", 710 .addr = 0x000000, 711 .prev = 0x008000, 712 .data = { 713 { "Global", 1, &gv100_disp_core_mthd_base }, 714 { "SOR", 4, &gv100_disp_core_mthd_sor }, 715 { "WINDOW", 8, &gv100_disp_core_mthd_wndw }, 716 { "HEAD", 4, &gv100_disp_core_mthd_head }, 717 {} 718 } 719}; 720 721static int 722gv100_disp_core_idle(struct nvkm_disp_chan *chan) 723{ 724 struct nvkm_device *device = chan->disp->engine.subdev.device; 725 nvkm_msec(device, 2000, 726 u32 stat = nvkm_rd32(device, 0x610630); 727 if ((stat & 0x001f0000) == 0x000b0000) 728 return 0; 729 ); 730 return -EBUSY; 731} 732 733static u64 734gv100_disp_core_user(struct nvkm_disp_chan *chan, u64 *psize) 735{ 736 *psize = 0x10000; 737 return 0x680000; 738} 739 740static void 741gv100_disp_core_intr(struct nvkm_disp_chan *chan, bool en) 742{ 743 struct nvkm_device *device = chan->disp->engine.subdev.device; 744 const u32 mask = 0x00000001; 745 const u32 data = en ? mask : 0; 746 nvkm_mask(device, 0x611dac, mask, data); 747} 748 749static void 750gv100_disp_core_fini(struct nvkm_disp_chan *chan) 751{ 752 struct nvkm_device *device = chan->disp->engine.subdev.device; 753 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000000); 754 gv100_disp_core_idle(chan); 755 nvkm_mask(device, 0x6104e0, 0x00000002, 0x00000000); 756 chan->suspend_put = nvkm_rd32(device, 0x680000); 757} 758 759static int 760gv100_disp_core_init(struct nvkm_disp_chan *chan) 761{ 762 struct nvkm_subdev *subdev = &chan->disp->engine.subdev; 763 struct nvkm_device *device = subdev->device; 764 765 nvkm_wr32(device, 0x610b24, lower_32_bits(chan->push)); 766 nvkm_wr32(device, 0x610b20, upper_32_bits(chan->push)); 767 nvkm_wr32(device, 0x610b28, 0x00000001); 768 nvkm_wr32(device, 0x610b2c, 0x00000040); 769 770 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000010); 771 nvkm_wr32(device, 0x680000, chan->suspend_put); 772 nvkm_wr32(device, 0x6104e0, 0x00000013); 773 return gv100_disp_core_idle(chan); 774} 775 776static const struct nvkm_disp_chan_func 777gv100_disp_core_func = { 778 .push = nv50_disp_dmac_push, 779 .init = gv100_disp_core_init, 780 .fini = gv100_disp_core_fini, 781 .intr = gv100_disp_core_intr, 782 .user = gv100_disp_core_user, 783 .bind = gv100_disp_dmac_bind, 784}; 785 786const struct nvkm_disp_chan_user 787gv100_disp_core = { 788 .func = &gv100_disp_core_func, 789 .ctrl = 0, 790 .user = 0, 791 .mthd = &gv100_disp_core_mthd, 792}; 793 794#define gv100_disp_caps(p) container_of((p), struct gv100_disp_caps, object) 795 796struct gv100_disp_caps { 797 struct nvkm_object object; 798 struct nvkm_disp *disp; 799}; 800 801static int 802gv100_disp_caps_map(struct nvkm_object *object, void *argv, u32 argc, 803 enum nvkm_object_map *type, u64 *addr, u64 *size) 804{ 805 struct gv100_disp_caps *caps = gv100_disp_caps(object); 806 struct nvkm_device *device = caps->disp->engine.subdev.device; 807 *type = NVKM_OBJECT_MAP_IO; 808 *addr = 0x640000 + device->func->resource_addr(device, 0); 809 *size = 0x1000; 810 return 0; 811} 812 813static const struct nvkm_object_func 814gv100_disp_caps = { 815 .map = gv100_disp_caps_map, 816}; 817 818int 819gv100_disp_caps_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, 820 struct nvkm_object **pobject) 821{ 822 struct nvkm_disp *disp = nvkm_udisp(oclass->parent); 823 struct gv100_disp_caps *caps; 824 825 if (!(caps = kzalloc(sizeof(*caps), GFP_KERNEL))) 826 return -ENOMEM; 827 *pobject = &caps->object; 828 829 nvkm_object_ctor(&gv100_disp_caps, oclass, &caps->object); 830 caps->disp = disp; 831 return 0; 832} 833 834void 835gv100_disp_super(struct work_struct *work) 836{ 837 struct nvkm_disp *disp = container_of(work, struct nvkm_disp, super.work); 838 struct nvkm_subdev *subdev = &disp->engine.subdev; 839 struct nvkm_device *device = subdev->device; 840 struct nvkm_head *head; 841 u32 stat, mask[4]; 842 843 mutex_lock(&disp->super.mutex); 844 stat = nvkm_rd32(device, 0x6107a8); 845 846 nvkm_debug(subdev, "supervisor %d: %08x\n", ffs(disp->super.pending), stat); 847 list_for_each_entry(head, &disp->heads, head) { 848 mask[head->id] = nvkm_rd32(device, 0x6107ac + (head->id * 4)); 849 HEAD_DBG(head, "%08x", mask[head->id]); 850 } 851 852 if (disp->super.pending & 0x00000001) { 853 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); 854 nv50_disp_super_1(disp); 855 list_for_each_entry(head, &disp->heads, head) { 856 if (!(mask[head->id] & 0x00001000)) 857 continue; 858 nv50_disp_super_1_0(disp, head); 859 } 860 } else 861 if (disp->super.pending & 0x00000002) { 862 list_for_each_entry(head, &disp->heads, head) { 863 if (!(mask[head->id] & 0x00001000)) 864 continue; 865 nv50_disp_super_2_0(disp, head); 866 } 867 list_for_each_entry(head, &disp->heads, head) { 868 if (!(mask[head->id] & 0x00010000)) 869 continue; 870 nv50_disp_super_2_1(disp, head); 871 } 872 list_for_each_entry(head, &disp->heads, head) { 873 if (!(mask[head->id] & 0x00001000)) 874 continue; 875 nv50_disp_super_2_2(disp, head); 876 } 877 } else 878 if (disp->super.pending & 0x00000004) { 879 list_for_each_entry(head, &disp->heads, head) { 880 if (!(mask[head->id] & 0x00001000)) 881 continue; 882 nv50_disp_super_3_0(disp, head); 883 } 884 } 885 886 list_for_each_entry(head, &disp->heads, head) 887 nvkm_wr32(device, 0x6107ac + (head->id * 4), 0x00000000); 888 889 nvkm_wr32(device, 0x6107a8, 0x80000000); 890 mutex_unlock(&disp->super.mutex); 891} 892 893static void 894gv100_disp_exception(struct nvkm_disp *disp, int chid) 895{ 896 struct nvkm_subdev *subdev = &disp->engine.subdev; 897 struct nvkm_device *device = subdev->device; 898 u32 stat = nvkm_rd32(device, 0x611020 + (chid * 12)); 899 u32 type = (stat & 0x00007000) >> 12; 900 u32 mthd = (stat & 0x00000fff) << 2; 901 const struct nvkm_enum *reason = 902 nvkm_enum_find(nv50_disp_intr_error_type, type); 903 904 /*TODO: Suspect 33->41 are for WRBK channel exceptions, but we 905 * don't support those currently. 906 * 907 * CORE+WIN CHIDs map directly to the FE_EXCEPT() slots. 908 */ 909 if (chid <= 32) { 910 u32 data = nvkm_rd32(device, 0x611024 + (chid * 12)); 911 u32 code = nvkm_rd32(device, 0x611028 + (chid * 12)); 912 nvkm_error(subdev, "chid %d stat %08x reason %d [%s] " 913 "mthd %04x data %08x code %08x\n", 914 chid, stat, type, reason ? reason->name : "", 915 mthd, data, code); 916 } else { 917 nvkm_error(subdev, "chid %d stat %08x reason %d [%s] " 918 "mthd %04x\n", 919 chid, stat, type, reason ? reason->name : "", mthd); 920 } 921 922 if (chid < ARRAY_SIZE(disp->chan) && disp->chan[chid]) { 923 switch (mthd) { 924 case 0x0200: 925 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); 926 break; 927 default: 928 break; 929 } 930 } 931 932 nvkm_wr32(device, 0x611020 + (chid * 12), 0x90000000); 933} 934 935static void 936gv100_disp_intr_ctrl_disp(struct nvkm_disp *disp) 937{ 938 struct nvkm_subdev *subdev = &disp->engine.subdev; 939 struct nvkm_device *device = subdev->device; 940 u32 stat = nvkm_rd32(device, 0x611c30); 941 942 if (stat & 0x00000007) { 943 disp->super.pending = (stat & 0x00000007); 944 queue_work(disp->super.wq, &disp->super.work); 945 nvkm_wr32(device, 0x611860, disp->super.pending); 946 stat &= ~0x00000007; 947 } 948 949 /*TODO: I would guess this is VBIOS_RELEASE, however, NFI how to 950 * ACK it, nor does RM appear to bother. 951 */ 952 if (stat & 0x00000008) 953 stat &= ~0x00000008; 954 955 if (stat & 0x00000080) { 956 u32 error = nvkm_mask(device, 0x611848, 0x00000000, 0x00000000); 957 nvkm_warn(subdev, "error %08x\n", error); 958 stat &= ~0x00000080; 959 } 960 961 if (stat & 0x00000100) { 962 unsigned long wndws = nvkm_rd32(device, 0x611858); 963 unsigned long other = nvkm_rd32(device, 0x61185c); 964 int wndw; 965 966 nvkm_wr32(device, 0x611858, wndws); 967 nvkm_wr32(device, 0x61185c, other); 968 969 /* AWAKEN_OTHER_CORE. */ 970 if (other & 0x00000001) 971 nv50_disp_chan_uevent_send(disp, 0); 972 973 /* AWAKEN_WIN_CH(n). */ 974 for_each_set_bit(wndw, &wndws, disp->wndw.nr) { 975 nv50_disp_chan_uevent_send(disp, 1 + wndw); 976 } 977 } 978 979 if (stat) 980 nvkm_warn(subdev, "ctrl %08x\n", stat); 981} 982 983static void 984gv100_disp_intr_exc_other(struct nvkm_disp *disp) 985{ 986 struct nvkm_subdev *subdev = &disp->engine.subdev; 987 struct nvkm_device *device = subdev->device; 988 u32 stat = nvkm_rd32(device, 0x611854); 989 unsigned long mask; 990 int head; 991 992 if (stat & 0x00000001) { 993 nvkm_wr32(device, 0x611854, 0x00000001); 994 gv100_disp_exception(disp, 0); 995 stat &= ~0x00000001; 996 } 997 998 if ((mask = (stat & 0x00ff0000) >> 16)) { 999 for_each_set_bit(head, &mask, disp->wndw.nr) { 1000 nvkm_wr32(device, 0x611854, 0x00010000 << head); 1001 gv100_disp_exception(disp, 73 + head); 1002 stat &= ~(0x00010000 << head); 1003 } 1004 } 1005 1006 if (stat) { 1007 nvkm_warn(subdev, "exception %08x\n", stat); 1008 nvkm_wr32(device, 0x611854, stat); 1009 } 1010} 1011 1012static void 1013gv100_disp_intr_exc_winim(struct nvkm_disp *disp) 1014{ 1015 struct nvkm_subdev *subdev = &disp->engine.subdev; 1016 struct nvkm_device *device = subdev->device; 1017 unsigned long stat = nvkm_rd32(device, 0x611850); 1018 int wndw; 1019 1020 for_each_set_bit(wndw, &stat, disp->wndw.nr) { 1021 nvkm_wr32(device, 0x611850, BIT(wndw)); 1022 gv100_disp_exception(disp, 33 + wndw); 1023 stat &= ~BIT(wndw); 1024 } 1025 1026 if (stat) { 1027 nvkm_warn(subdev, "wimm %08x\n", (u32)stat); 1028 nvkm_wr32(device, 0x611850, stat); 1029 } 1030} 1031 1032static void 1033gv100_disp_intr_exc_win(struct nvkm_disp *disp) 1034{ 1035 struct nvkm_subdev *subdev = &disp->engine.subdev; 1036 struct nvkm_device *device = subdev->device; 1037 unsigned long stat = nvkm_rd32(device, 0x61184c); 1038 int wndw; 1039 1040 for_each_set_bit(wndw, &stat, disp->wndw.nr) { 1041 nvkm_wr32(device, 0x61184c, BIT(wndw)); 1042 gv100_disp_exception(disp, 1 + wndw); 1043 stat &= ~BIT(wndw); 1044 } 1045 1046 if (stat) { 1047 nvkm_warn(subdev, "wndw %08x\n", (u32)stat); 1048 nvkm_wr32(device, 0x61184c, stat); 1049 } 1050} 1051 1052static void 1053gv100_disp_intr_head_timing(struct nvkm_disp *disp, int head) 1054{ 1055 struct nvkm_subdev *subdev = &disp->engine.subdev; 1056 struct nvkm_device *device = subdev->device; 1057 u32 stat = nvkm_rd32(device, 0x611800 + (head * 0x04)); 1058 1059 /* LAST_DATA, LOADV. */ 1060 if (stat & 0x00000003) { 1061 nvkm_wr32(device, 0x611800 + (head * 0x04), stat & 0x00000003); 1062 stat &= ~0x00000003; 1063 } 1064 1065 if (stat & 0x00000004) { 1066 nvkm_disp_vblank(disp, head); 1067 nvkm_wr32(device, 0x611800 + (head * 0x04), 0x00000004); 1068 stat &= ~0x00000004; 1069 } 1070 1071 if (stat) { 1072 nvkm_warn(subdev, "head %08x\n", stat); 1073 nvkm_wr32(device, 0x611800 + (head * 0x04), stat); 1074 } 1075} 1076 1077void 1078gv100_disp_intr(struct nvkm_disp *disp) 1079{ 1080 struct nvkm_subdev *subdev = &disp->engine.subdev; 1081 struct nvkm_device *device = subdev->device; 1082 u32 stat = nvkm_rd32(device, 0x611ec0); 1083 unsigned long mask; 1084 int head; 1085 1086 if ((mask = (stat & 0x000000ff))) { 1087 for_each_set_bit(head, &mask, 8) { 1088 gv100_disp_intr_head_timing(disp, head); 1089 stat &= ~BIT(head); 1090 } 1091 } 1092 1093 if (stat & 0x00000200) { 1094 gv100_disp_intr_exc_win(disp); 1095 stat &= ~0x00000200; 1096 } 1097 1098 if (stat & 0x00000400) { 1099 gv100_disp_intr_exc_winim(disp); 1100 stat &= ~0x00000400; 1101 } 1102 1103 if (stat & 0x00000800) { 1104 gv100_disp_intr_exc_other(disp); 1105 stat &= ~0x00000800; 1106 } 1107 1108 if (stat & 0x00001000) { 1109 gv100_disp_intr_ctrl_disp(disp); 1110 stat &= ~0x00001000; 1111 } 1112 1113 if (stat) 1114 nvkm_warn(subdev, "intr %08x\n", stat); 1115} 1116 1117void 1118gv100_disp_fini(struct nvkm_disp *disp, bool suspend) 1119{ 1120 struct nvkm_device *device = disp->engine.subdev.device; 1121 nvkm_wr32(device, 0x611db0, 0x00000000); 1122} 1123 1124static int 1125gv100_disp_init(struct nvkm_disp *disp) 1126{ 1127 struct nvkm_device *device = disp->engine.subdev.device; 1128 struct nvkm_head *head; 1129 int i, j; 1130 u32 tmp; 1131 1132 /* Claim ownership of display. */ 1133 if (nvkm_rd32(device, 0x6254e8) & 0x00000002) { 1134 nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000); 1135 if (nvkm_msec(device, 2000, 1136 if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002)) 1137 break; 1138 ) < 0) 1139 return -EBUSY; 1140 } 1141 1142 /* Lock pin capabilities. */ 1143 tmp = nvkm_rd32(device, 0x610068); 1144 nvkm_wr32(device, 0x640008, tmp); 1145 1146 /* SOR capabilities. */ 1147 for (i = 0; i < disp->sor.nr; i++) { 1148 tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); 1149 nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i); 1150 nvkm_wr32(device, 0x640144 + (i * 0x08), tmp); 1151 } 1152 1153 /* Head capabilities. */ 1154 list_for_each_entry(head, &disp->heads, head) { 1155 const int id = head->id; 1156 1157 /* RG. */ 1158 tmp = nvkm_rd32(device, 0x616300 + (id * 0x800)); 1159 nvkm_wr32(device, 0x640048 + (id * 0x020), tmp); 1160 1161 /* POSTCOMP. */ 1162 for (j = 0; j < 6 * 4; j += 4) { 1163 tmp = nvkm_rd32(device, 0x616100 + (id * 0x800) + j); 1164 nvkm_wr32(device, 0x640030 + (id * 0x20) + j, tmp); 1165 } 1166 } 1167 1168 /* Window capabilities. */ 1169 for (i = 0; i < disp->wndw.nr; i++) { 1170 nvkm_mask(device, 0x640004, 1 << i, 1 << i); 1171 for (j = 0; j < 6 * 4; j += 4) { 1172 tmp = nvkm_rd32(device, 0x630050 + (i * 0x800) + j); 1173 nvkm_wr32(device, 0x6401e4 + (i * 0x20) + j, tmp); 1174 } 1175 } 1176 1177 /* IHUB capabilities. */ 1178 for (i = 0; i < 4; i++) { 1179 tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04)); 1180 nvkm_wr32(device, 0x640010 + (i * 0x04), tmp); 1181 } 1182 1183 nvkm_mask(device, 0x610078, 0x00000001, 0x00000001); 1184 1185 /* Setup instance memory. */ 1186 switch (nvkm_memory_target(disp->inst->memory)) { 1187 case NVKM_MEM_TARGET_VRAM: tmp = 0x00000001; break; 1188 case NVKM_MEM_TARGET_NCOH: tmp = 0x00000002; break; 1189 case NVKM_MEM_TARGET_HOST: tmp = 0x00000003; break; 1190 default: 1191 break; 1192 } 1193 nvkm_wr32(device, 0x610010, 0x00000008 | tmp); 1194 nvkm_wr32(device, 0x610014, disp->inst->addr >> 16); 1195 1196 /* CTRL_DISP: AWAKEN, ERROR, SUPERVISOR[1-3]. */ 1197 nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */ 1198 nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */ 1199 1200 /* EXC_OTHER: CURSn, CORE. */ 1201 nvkm_wr32(device, 0x611cec, disp->head.mask << 16 | 1202 0x00000001); /* MSK. */ 1203 nvkm_wr32(device, 0x611dac, 0x00000000); /* EN. */ 1204 1205 /* EXC_WINIM. */ 1206 nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */ 1207 nvkm_wr32(device, 0x611da8, 0x00000000); /* EN. */ 1208 1209 /* EXC_WIN. */ 1210 nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */ 1211 nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */ 1212 1213 /* HEAD_TIMING(n): VBLANK. */ 1214 list_for_each_entry(head, &disp->heads, head) { 1215 const u32 hoff = head->id * 4; 1216 nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */ 1217 nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */ 1218 } 1219 1220 /* OR. */ 1221 nvkm_wr32(device, 0x611cf4, 0x00000000); /* MSK. */ 1222 nvkm_wr32(device, 0x611db4, 0x00000000); /* EN. */ 1223 return 0; 1224} 1225 1226static const struct nvkm_disp_func 1227gv100_disp = { 1228 .oneinit = nv50_disp_oneinit, 1229 .init = gv100_disp_init, 1230 .fini = gv100_disp_fini, 1231 .intr = gv100_disp_intr, 1232 .super = gv100_disp_super, 1233 .uevent = &gv100_disp_chan_uevent, 1234 .wndw = { .cnt = gv100_disp_wndw_cnt }, 1235 .head = { .cnt = gv100_head_cnt, .new = gv100_head_new }, 1236 .sor = { .cnt = gv100_sor_cnt, .new = gv100_sor_new }, 1237 .ramht_size = 0x2000, 1238 .root = { 0, 0,GV100_DISP }, 1239 .user = { 1240 {{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new }, 1241 {{ 0, 0,GV100_DISP_CURSOR }, nvkm_disp_chan_new, &gv100_disp_curs }, 1242 {{ 0, 0,GV100_DISP_WINDOW_IMM_CHANNEL_DMA}, nvkm_disp_wndw_new, &gv100_disp_wimm }, 1243 {{ 0, 0,GV100_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gv100_disp_core }, 1244 {{ 0, 0,GV100_DISP_WINDOW_CHANNEL_DMA }, nvkm_disp_wndw_new, &gv100_disp_wndw }, 1245 {} 1246 }, 1247}; 1248 1249int 1250gv100_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 1251 struct nvkm_disp **pdisp) 1252{ 1253 return nvkm_disp_new_(&gv100_disp, device, type, inst, pdisp); 1254} 1255