1/*
2 * Copyright 2018 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#include "chan.h"
23#include "priv.h"
24#include "head.h"
25#include "ior.h"
26
27#include <core/gpuobj.h>
28#include <subdev/gsp.h>
29#include <subdev/timer.h>
30
31#include <nvif/class.h>
32
33void
34tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head, u8 slot, u8 slot_nr, u16 pbn, u16 aligned)
35{
36	struct nvkm_device *device = sor->disp->engine.subdev.device;
37	const u32 hoff = head * 0x800;
38
39	nvkm_mask(device, 0x61657c + hoff, 0xffffffff, (aligned << 16) | pbn);
40	nvkm_mask(device, 0x616578 + hoff, 0x00003f3f, (slot_nr << 8) | slot);
41}
42
43static int
44tu102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
45{
46	struct nvkm_device *device = sor->disp->engine.subdev.device;
47	const u32 soff = nv50_ior_base(sor);
48	const u32 loff = nv50_sor_link(sor);
49	u32 dpctrl = 0x00000000;
50	u32 clksor = 0x00000000;
51
52	clksor |= sor->dp.bw << 18;
53	dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
54	if (sor->dp.mst)
55		dpctrl |= 0x40000000;
56	if (sor->dp.ef)
57		dpctrl |= 0x00004000;
58
59	nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
60
61	/*XXX*/
62	nvkm_msec(device, 40, NVKM_DELAY);
63	nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000);
64	nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001);
65
66	nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
67	return 0;
68}
69
70static const struct nvkm_ior_func_dp
71tu102_sor_dp = {
72	.lanes = { 0, 1, 2, 3 },
73	.links = tu102_sor_dp_links,
74	.power = g94_sor_dp_power,
75	.pattern = gm107_sor_dp_pattern,
76	.drive = gm200_sor_dp_drive,
77	.vcpi = tu102_sor_dp_vcpi,
78	.audio = gv100_sor_dp_audio,
79	.audio_sym = gv100_sor_dp_audio_sym,
80	.watermark = gv100_sor_dp_watermark,
81};
82
83static const struct nvkm_ior_func
84tu102_sor = {
85	.route = {
86		.get = gm200_sor_route_get,
87		.set = gm200_sor_route_set,
88	},
89	.state = gv100_sor_state,
90	.power = nv50_sor_power,
91	.clock = gf119_sor_clock,
92	.bl = &gt215_sor_bl,
93	.hdmi = &gv100_sor_hdmi,
94	.dp = &tu102_sor_dp,
95	.hda = &gv100_sor_hda,
96};
97
98static int
99tu102_sor_new(struct nvkm_disp *disp, int id)
100{
101	struct nvkm_device *device = disp->engine.subdev.device;
102	u32 hda = nvkm_rd32(device, 0x08a15c);
103
104	return nvkm_ior_new_(&tu102_sor, disp, SOR, id, hda & BIT(id));
105}
106
107int
108tu102_disp_init(struct nvkm_disp *disp)
109{
110	struct nvkm_device *device = disp->engine.subdev.device;
111	struct nvkm_head *head;
112	int i, j;
113	u32 tmp;
114
115	/* Claim ownership of display. */
116	if (nvkm_rd32(device, 0x6254e8) & 0x00000002) {
117		nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000);
118		if (nvkm_msec(device, 2000,
119			if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002))
120				break;
121		) < 0)
122			return -EBUSY;
123	}
124
125	/* Lock pin capabilities. */
126	tmp = 0x00000021; /*XXX*/
127	nvkm_wr32(device, 0x640008, tmp);
128
129	/* SOR capabilities. */
130	for (i = 0; i < disp->sor.nr; i++) {
131		tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
132		nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i);
133		nvkm_wr32(device, 0x640144 + (i * 0x08), tmp);
134	}
135
136	/* Head capabilities. */
137	list_for_each_entry(head, &disp->heads, head) {
138		const int id = head->id;
139
140		/* RG. */
141		tmp = nvkm_rd32(device, 0x616300 + (id * 0x800));
142		nvkm_wr32(device, 0x640048 + (id * 0x020), tmp);
143
144		/* POSTCOMP. */
145		for (j = 0; j < 5 * 4; j += 4) {
146			tmp = nvkm_rd32(device, 0x616140 + (id * 0x800) + j);
147			nvkm_wr32(device, 0x640680 + (id * 0x20) + j, tmp);
148		}
149	}
150
151	/* Window capabilities. */
152	for (i = 0; i < disp->wndw.nr; i++) {
153		nvkm_mask(device, 0x640004, 1 << i, 1 << i);
154		for (j = 0; j < 6 * 4; j += 4) {
155			tmp = nvkm_rd32(device, 0x630100 + (i * 0x800) + j);
156			nvkm_mask(device, 0x640780 + (i * 0x20) + j, 0xffffffff, tmp);
157		}
158		nvkm_mask(device, 0x64000c, 0x00000100, 0x00000100);
159	}
160
161	/* IHUB capabilities. */
162	for (i = 0; i < 3; i++) {
163		tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04));
164		nvkm_wr32(device, 0x640010 + (i * 0x04), tmp);
165	}
166
167	nvkm_mask(device, 0x610078, 0x00000001, 0x00000001);
168
169	/* Setup instance memory. */
170	switch (nvkm_memory_target(disp->inst->memory)) {
171	case NVKM_MEM_TARGET_VRAM: tmp = 0x00000001; break;
172	case NVKM_MEM_TARGET_NCOH: tmp = 0x00000002; break;
173	case NVKM_MEM_TARGET_HOST: tmp = 0x00000003; break;
174	default:
175		break;
176	}
177	nvkm_wr32(device, 0x610010, 0x00000008 | tmp);
178	nvkm_wr32(device, 0x610014, disp->inst->addr >> 16);
179
180	/* CTRL_DISP: AWAKEN, ERROR, SUPERVISOR[1-3]. */
181	nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */
182	nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */
183
184	/* EXC_OTHER: CURSn, CORE. */
185	nvkm_wr32(device, 0x611cec, disp->head.mask << 16 |
186				    0x00000001); /* MSK. */
187	nvkm_wr32(device, 0x611dac, 0x00000000); /* EN. */
188
189	/* EXC_WINIM. */
190	nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */
191	nvkm_wr32(device, 0x611da8, 0x00000000); /* EN. */
192
193	/* EXC_WIN. */
194	nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */
195	nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */
196
197	/* HEAD_TIMING(n): VBLANK. */
198	list_for_each_entry(head, &disp->heads, head) {
199		const u32 hoff = head->id * 4;
200		nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */
201		nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */
202	}
203
204	/* OR. */
205	nvkm_wr32(device, 0x611cf4, 0x00000000); /* MSK. */
206	nvkm_wr32(device, 0x611db4, 0x00000000); /* EN. */
207	return 0;
208}
209
210static const struct nvkm_disp_func
211tu102_disp = {
212	.oneinit = nv50_disp_oneinit,
213	.init = tu102_disp_init,
214	.fini = gv100_disp_fini,
215	.intr = gv100_disp_intr,
216	.super = gv100_disp_super,
217	.uevent = &gv100_disp_chan_uevent,
218	.wndw = { .cnt = gv100_disp_wndw_cnt },
219	.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
220	.sor = { .cnt = gv100_sor_cnt, .new = tu102_sor_new },
221	.ramht_size = 0x2000,
222	.root = {  0, 0,TU102_DISP },
223	.user = {
224		{{-1,-1,GV100_DISP_CAPS                  }, gv100_disp_caps_new },
225		{{ 0, 0,TU102_DISP_CURSOR                },  nvkm_disp_chan_new, &gv100_disp_curs },
226		{{ 0, 0,TU102_DISP_WINDOW_IMM_CHANNEL_DMA},  nvkm_disp_wndw_new, &gv100_disp_wimm },
227		{{ 0, 0,TU102_DISP_CORE_CHANNEL_DMA      },  nvkm_disp_core_new, &gv100_disp_core },
228		{{ 0, 0,TU102_DISP_WINDOW_CHANNEL_DMA    },  nvkm_disp_wndw_new, &gv100_disp_wndw },
229		{}
230	},
231};
232
233int
234tu102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
235	       struct nvkm_disp **pdisp)
236{
237	if (nvkm_gsp_rm(device->gsp))
238		return r535_disp_new(&tu102_disp, device, type, inst, pdisp);
239
240	return nvkm_disp_new_(&tu102_disp, device, type, inst, pdisp);
241}
242