1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "priv.h"
25#include "chan.h"
26#include "hdmi.h"
27#include "head.h"
28#include "ior.h"
29
30#include <subdev/timer.h>
31
32#include <nvif/class.h>
33
34static void
35gt215_sor_hda_eld(struct nvkm_ior *ior, int head, u8 *data, u8 size)
36{
37	struct nvkm_device *device = ior->disp->engine.subdev.device;
38	const u32 soff = ior->id * 0x800;
39	int i;
40
41	for (i = 0; i < size; i++)
42		nvkm_wr32(device, 0x61c440 + soff, (i << 8) | data[i]);
43	for (; i < 0x60; i++)
44		nvkm_wr32(device, 0x61c440 + soff, (i << 8));
45	nvkm_mask(device, 0x61c448 + soff, 0x80000002, 0x80000002);
46}
47
48static void
49gt215_sor_hda_hpd(struct nvkm_ior *ior, int head, bool present)
50{
51	struct nvkm_device *device = ior->disp->engine.subdev.device;
52	u32 data = 0x80000000;
53	u32 mask = 0x80000001;
54	if (present)
55		data |= 0x00000001;
56	else
57		mask |= 0x00000002;
58	nvkm_mask(device, 0x61c448 + ior->id * 0x800, mask, data);
59}
60
61const struct nvkm_ior_func_hda
62gt215_sor_hda = {
63	.hpd = gt215_sor_hda_hpd,
64	.eld = gt215_sor_hda_eld,
65};
66
67void
68gt215_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable)
69{
70	struct nvkm_device *device = sor->disp->engine.subdev.device;
71	const u32 soff = nv50_ior_base(sor);
72	const u32 data = 0x80000000 | (0x00000001 * enable);
73	const u32 mask = 0x8000000d;
74
75	nvkm_mask(device, 0x61c1e0 + soff, mask, data);
76	nvkm_msec(device, 2000,
77		if (!(nvkm_rd32(device, 0x61c1e0 + soff) & 0x80000000))
78			break;
79	);
80}
81
82static const struct nvkm_ior_func_dp
83gt215_sor_dp = {
84	.lanes = { 2, 1, 0, 3 },
85	.links = g94_sor_dp_links,
86	.power = g94_sor_dp_power,
87	.pattern = g94_sor_dp_pattern,
88	.drive = g94_sor_dp_drive,
89	.audio = gt215_sor_dp_audio,
90	.audio_sym = g94_sor_dp_audio_sym,
91	.activesym = g94_sor_dp_activesym,
92	.watermark = g94_sor_dp_watermark,
93};
94
95static void
96gt215_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior, int head, void *data, u32 size)
97{
98	struct nvkm_device *device = ior->disp->engine.subdev.device;
99	struct packed_hdmi_infoframe vsi;
100	const u32 soff = nv50_ior_base(ior);
101
102	pack_hdmi_infoframe(&vsi, data, size);
103
104	nvkm_mask(device, 0x61c53c + soff, 0x00010001, 0x00010000);
105	if (!size)
106		return;
107
108	nvkm_wr32(device, 0x61c544 + soff, vsi.header);
109	nvkm_wr32(device, 0x61c548 + soff, vsi.subpack0_low);
110	nvkm_wr32(device, 0x61c54c + soff, vsi.subpack0_high);
111	/* Is there a second (or up to fourth?) set of subpack registers here? */
112	/* nvkm_wr32(device, 0x61c550 + soff, vsi.subpack1_low); */
113	/* nvkm_wr32(device, 0x61c554 + soff, vsi.subpack1_high); */
114
115	nvkm_mask(device, 0x61c53c + soff, 0x00010001, 0x00010001);
116}
117
118static void
119gt215_sor_hdmi_infoframe_avi(struct nvkm_ior *ior, int head, void *data, u32 size)
120{
121	struct nvkm_device *device = ior->disp->engine.subdev.device;
122	struct packed_hdmi_infoframe avi;
123	const u32 soff = nv50_ior_base(ior);
124
125	pack_hdmi_infoframe(&avi, data, size);
126
127	nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000);
128	if (!size)
129		return;
130
131	nvkm_wr32(device, 0x61c528 + soff, avi.header);
132	nvkm_wr32(device, 0x61c52c + soff, avi.subpack0_low);
133	nvkm_wr32(device, 0x61c530 + soff, avi.subpack0_high);
134	nvkm_wr32(device, 0x61c534 + soff, avi.subpack1_low);
135	nvkm_wr32(device, 0x61c538 + soff, avi.subpack1_high);
136
137	nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000001);
138}
139
140static void
141gt215_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet, u8 rekey)
142{
143	struct nvkm_device *device = ior->disp->engine.subdev.device;
144	const u32 ctrl = 0x40000000 * enable |
145			 0x1f000000 /* ??? */ |
146			 max_ac_packet << 16 |
147			 rekey;
148	const u32 soff = nv50_ior_base(ior);
149
150	if (!(ctrl & 0x40000000)) {
151		nvkm_mask(device, 0x61c5a4 + soff, 0x40000000, 0x00000000);
152		nvkm_mask(device, 0x61c53c + soff, 0x00000001, 0x00000000);
153		nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000);
154		nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000);
155		return;
156	}
157
158	/* Audio InfoFrame */
159	nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000);
160	nvkm_wr32(device, 0x61c508 + soff, 0x000a0184);
161	nvkm_wr32(device, 0x61c50c + soff, 0x00000071);
162	nvkm_wr32(device, 0x61c510 + soff, 0x00000000);
163	nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000001);
164
165	nvkm_mask(device, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
166	nvkm_mask(device, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
167	nvkm_mask(device, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
168
169	/* ??? */
170	nvkm_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
171	nvkm_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
172	nvkm_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
173
174	/* HDMI_CTRL */
175	nvkm_mask(device, 0x61c5a4 + soff, 0x5f1f007f, ctrl);
176}
177
178const struct nvkm_ior_func_hdmi
179gt215_sor_hdmi = {
180	.ctrl = gt215_sor_hdmi_ctrl,
181	.infoframe_avi = gt215_sor_hdmi_infoframe_avi,
182	.infoframe_vsi = gt215_sor_hdmi_infoframe_vsi,
183};
184
185static int
186gt215_sor_bl_set(struct nvkm_ior *ior, int lvl)
187{
188	struct nvkm_device *device = ior->disp->engine.subdev.device;
189	const u32 soff = nv50_ior_base(ior);
190	u32 div, val;
191
192	div = nvkm_rd32(device, 0x61c080 + soff);
193	val = (lvl * div) / 100;
194	if (div)
195		nvkm_wr32(device, 0x61c084 + soff, 0xc0000000 | val);
196
197	return 0;
198}
199
200static int
201gt215_sor_bl_get(struct nvkm_ior *ior)
202{
203	struct nvkm_device *device = ior->disp->engine.subdev.device;
204	const u32 soff = nv50_ior_base(ior);
205	u32 div, val;
206
207	div  = nvkm_rd32(device, 0x61c080 + soff);
208	val  = nvkm_rd32(device, 0x61c084 + soff);
209	val &= 0x00ffffff;
210	if (div && div >= val)
211		return ((val * 100) + (div / 2)) / div;
212
213	return 100;
214}
215
216const struct nvkm_ior_func_bl
217gt215_sor_bl = {
218	.get = gt215_sor_bl_get,
219	.set = gt215_sor_bl_set,
220};
221
222static const struct nvkm_ior_func
223gt215_sor = {
224	.state = g94_sor_state,
225	.power = nv50_sor_power,
226	.clock = nv50_sor_clock,
227	.bl = &gt215_sor_bl,
228	.hdmi = &gt215_sor_hdmi,
229	.dp = &gt215_sor_dp,
230	.hda = &gt215_sor_hda,
231};
232
233static int
234gt215_sor_new(struct nvkm_disp *disp, int id)
235{
236	return nvkm_ior_new_(&gt215_sor, disp, SOR, id, true);
237}
238
239static const struct nvkm_disp_func
240gt215_disp = {
241	.oneinit = nv50_disp_oneinit,
242	.init = nv50_disp_init,
243	.fini = nv50_disp_fini,
244	.intr = nv50_disp_intr,
245	.super = nv50_disp_super,
246	.uevent = &nv50_disp_chan_uevent,
247	.head = { .cnt = nv50_head_cnt, .new = nv50_head_new },
248	.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
249	.sor = { .cnt = g94_sor_cnt, .new = gt215_sor_new },
250	.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
251	.root = { 0,0,GT214_DISP },
252	.user = {
253		{{0,0,GT214_DISP_CURSOR             }, nvkm_disp_chan_new, & nv50_disp_curs },
254		{{0,0,GT214_DISP_OVERLAY            }, nvkm_disp_chan_new, & nv50_disp_oimm },
255		{{0,0,GT214_DISP_BASE_CHANNEL_DMA   }, nvkm_disp_chan_new, &  g84_disp_base },
256		{{0,0,GT214_DISP_CORE_CHANNEL_DMA   }, nvkm_disp_core_new, &  g94_disp_core },
257		{{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, &  g84_disp_ovly },
258		{}
259	},
260};
261
262int
263gt215_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
264	       struct nvkm_disp **pdisp)
265{
266	return nvkm_disp_new_(&gt215_disp, device, type, inst, pdisp);
267}
268