1/*
2 * Copyright 2021 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#include "priv.h"
23#include "chan.h"
24#include "head.h"
25#include "ior.h"
26
27#include <subdev/gsp.h>
28#include <subdev/timer.h>
29
30#include <nvif/class.h>
31
32static int
33ga102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
34{
35	struct nvkm_device *device = sor->disp->engine.subdev.device;
36	const u32 soff = nv50_ior_base(sor);
37	const u32 loff = nv50_sor_link(sor);
38	u32 dpctrl = 0x00000000;
39	u32 clksor = 0x00000000;
40
41	switch (sor->dp.bw) {
42	case 0x06: clksor |= 0x00000000; break;
43	case 0x0a: clksor |= 0x00040000; break;
44	case 0x14: clksor |= 0x00080000; break;
45	case 0x1e: clksor |= 0x000c0000; break;
46	case 0x08: clksor |= 0x00100000; break;
47	case 0x09: clksor |= 0x00140000; break;
48	case 0x0c: clksor |= 0x00180000; break;
49	case 0x10: clksor |= 0x001c0000; break;
50	default:
51		WARN_ON(1);
52		return -EINVAL;
53	}
54
55	dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
56	if (sor->dp.mst)
57		dpctrl |= 0x40000000;
58	if (sor->dp.ef)
59		dpctrl |= 0x00004000;
60
61	nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
62
63	/*XXX*/
64	nvkm_msec(device, 40, NVKM_DELAY);
65	nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000);
66	nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001);
67
68	nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
69	return 0;
70}
71
72static const struct nvkm_ior_func_dp
73ga102_sor_dp = {
74	.lanes = { 0, 1, 2, 3 },
75	.links = ga102_sor_dp_links,
76	.power = g94_sor_dp_power,
77	.pattern = gm107_sor_dp_pattern,
78	.drive = gm200_sor_dp_drive,
79	.vcpi = tu102_sor_dp_vcpi,
80	.audio = gv100_sor_dp_audio,
81	.audio_sym = gv100_sor_dp_audio_sym,
82	.watermark = gv100_sor_dp_watermark,
83};
84
85static void
86ga102_sor_clock(struct nvkm_ior *sor)
87{
88	struct nvkm_device *device = sor->disp->engine.subdev.device;
89	u32 div2 = 0;
90
91	if (sor->asy.proto == TMDS) {
92		if (sor->tmds.high_speed)
93			div2 = 1;
94	}
95
96	nvkm_wr32(device, 0x00ec08 + (sor->id * 0x10), 0x00000000);
97	nvkm_wr32(device, 0x00ec04 + (sor->id * 0x10), div2);
98}
99
100static const struct nvkm_ior_func
101ga102_sor = {
102	.route = {
103		.get = gm200_sor_route_get,
104		.set = gm200_sor_route_set,
105	},
106	.state = gv100_sor_state,
107	.power = nv50_sor_power,
108	.clock = ga102_sor_clock,
109	.bl = &gt215_sor_bl,
110	.hdmi = &gv100_sor_hdmi,
111	.dp = &ga102_sor_dp,
112	.hda = &gv100_sor_hda,
113};
114
115static int
116ga102_sor_new(struct nvkm_disp *disp, int id)
117{
118	struct nvkm_device *device = disp->engine.subdev.device;
119	u32 hda = nvkm_rd32(device, 0x08a15c);
120
121	return nvkm_ior_new_(&ga102_sor, disp, SOR, id, hda & BIT(id));
122}
123
124static const struct nvkm_disp_func
125ga102_disp = {
126	.oneinit = nv50_disp_oneinit,
127	.init = tu102_disp_init,
128	.fini = gv100_disp_fini,
129	.intr = gv100_disp_intr,
130	.super = gv100_disp_super,
131	.uevent = &gv100_disp_chan_uevent,
132	.wndw = { .cnt = gv100_disp_wndw_cnt },
133	.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
134	.sor = { .cnt = gv100_sor_cnt, .new = ga102_sor_new },
135	.ramht_size = 0x2000,
136	.root = {  0, 0,GA102_DISP },
137	.user = {
138		{{-1,-1,GV100_DISP_CAPS                  }, gv100_disp_caps_new },
139		{{ 0, 0,GA102_DISP_CURSOR                }, nvkm_disp_chan_new, &gv100_disp_curs },
140		{{ 0, 0,GA102_DISP_WINDOW_IMM_CHANNEL_DMA}, nvkm_disp_wndw_new, &gv100_disp_wimm },
141		{{ 0, 0,GA102_DISP_CORE_CHANNEL_DMA      }, nvkm_disp_core_new, &gv100_disp_core },
142		{{ 0, 0,GA102_DISP_WINDOW_CHANNEL_DMA    }, nvkm_disp_wndw_new, &gv100_disp_wndw },
143		{}
144	},
145};
146
147int
148ga102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
149	       struct nvkm_disp **pdisp)
150{
151	if (nvkm_gsp_rm(device->gsp))
152		return r535_disp_new(&ga102_disp, device, type, inst, pdisp);
153
154	return nvkm_disp_new_(&ga102_disp, device, type, inst, pdisp);
155}
156