Searched refs:base (Results 176 - 200 of 6511) sorted by relevance

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/linux-master/sound/pci/hda/
H A Dcs35l56_hda.c58 pm_runtime_get_sync(cs35l56->base.dev);
59 ret = cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_AUDIO_PLAY);
62 ret = regmap_read_poll_timeout(cs35l56->base.regmap,
68 dev_warn(cs35l56->base.dev, "PS0 wait failed: %d\n", ret);
70 regmap_set_bits(cs35l56->base.regmap, CS35L56_ASP1_ENABLES1,
79 cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_AUDIO_PAUSE);
80 regmap_clear_bits(cs35l56->base.regmap, CS35L56_ASP1_ENABLES1,
85 pm_runtime_mark_last_busy(cs35l56->base.dev);
86 pm_runtime_put_autosuspend(cs35l56->base.dev);
93 dev_dbg(cs35l56->base
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce80/
H A Ddce80_resource.c513 return &tg110->base;
528 return &opp->base;
548 return &aux_engine->base;
611 return &enc110->base;
687 return &dce_mi->base;
709 return &transform->base;
739 return &enc110->base;
756 return &panel_cntl->base;
774 clk_src->base.dp_clk_src = dp_clk_src;
775 return &clk_src->base;
[all...]
/linux-master/drivers/mmc/host/
H A Dmmci_qcom_dml.c51 void __iomem *base = host->base + DML_OFFSET; local
61 config = readl_relaxed(base + DML_CONFIG);
64 writel_relaxed(config, base + DML_CONFIG);
67 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE);
71 base + DML_PRODUCER_BAM_TRANS_SIZE);
73 config = readl_relaxed(base + DML_CONFIG);
75 writel_relaxed(config, base + DML_CONFIG);
77 writel_relaxed(1, base + DML_PRODUCER_START);
81 config = readl_relaxed(base
122 void __iomem *base; local
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/linux-master/drivers/irqchip/
H A Dirq-ath79-misc.c36 void __iomem *base = domain->host_data; local
41 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
42 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
62 void __iomem *base = irq_data_get_irq_chip_data(d); local
66 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
67 __raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
70 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
75 void __iomem *base = irq_data_get_irq_chip_data(d); local
79 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
80 __raw_writel(t & ~BIT(irq), base
88 void __iomem *base = irq_data_get_irq_chip_data(d); local
120 void __iomem *base = domain->host_data; local
135 void __iomem *base; local
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/linux-master/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_resource.c506 return &tg110->base;
521 return &opp->base;
541 return &aux_engine->base;
604 return &enc110->base;
680 return &dce_mi->base;
702 return &transform->base;
732 return &enc110->base;
749 return &panel_cntl->base;
767 clk_src->base.dp_clk_src = dp_clk_src;
768 return &clk_src->base;
[all...]
/linux-master/arch/arm/common/
H A Dscoop.c32 void __iomem *base; member in struct:scoop_dev
44 iowrite16(0x0100, sdev->base + SCOOP_MCR); /* 00 */
45 iowrite16(0x0000, sdev->base + SCOOP_CDR); /* 04 */
46 iowrite16(0x0000, sdev->base + SCOOP_CCR); /* 10 */
47 iowrite16(0x0000, sdev->base + SCOOP_IMR); /* 18 */
48 iowrite16(0x00FF, sdev->base + SCOOP_IRM); /* 14 */
49 iowrite16(0x0000, sdev->base + SCOOP_ISR); /* 1C */
50 iowrite16(0x0000, sdev->base + SCOOP_IRM);
58 gpwr = ioread16(sdev->base + SCOOP_GPWR);
63 iowrite16(gpwr, sdev->base
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/linux-master/drivers/misc/lkdtm/
H A Dheap.c68 int *base, *again; local
75 size_t offset = (len / sizeof(*base)) / 2;
77 base = kmalloc(len, GFP_KERNEL);
78 if (!base)
80 pr_info("Allocated memory %p-%p\n", base, &base[offset * 2]);
82 &base[offset]);
83 kfree(base);
84 base[offset] = 0x0abcdef0;
88 if (again != base)
94 int *base, *val, saw; local
138 int *base, val, saw; local
218 int *base; local
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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/volt/
H A Dgk104.c32 #define gk104_volt(p) container_of((p), struct gk104_volt, base)
34 struct nvkm_volt base; member in struct:gk104_volt
39 gk104_volt_get(struct nvkm_volt *base) argument
41 struct nvbios_volt *bios = &gk104_volt(base)->bios;
42 struct nvkm_device *device = base->subdev.device;
48 return bios->base + bios->pwm_range * duty / div;
52 gk104_volt_set(struct nvkm_volt *base, u32 uv) argument
54 struct nvbios_volt *bios = &gk104_volt(base)->bios;
55 struct nvkm_device *device = base->subdev.device;
60 duty = DIV_ROUND_UP((uv - bios->base) * di
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/linux-master/arch/x86/crypto/
H A Dtwofish_avx_glue.c33 return twofish_setkey(&tfm->base, key, keylen);
77 .base.cra_name = "__ecb(twofish)",
78 .base.cra_driver_name = "__ecb-twofish-avx",
79 .base.cra_priority = 400,
80 .base.cra_flags = CRYPTO_ALG_INTERNAL,
81 .base.cra_blocksize = TF_BLOCK_SIZE,
82 .base.cra_ctxsize = sizeof(struct twofish_ctx),
83 .base.cra_module = THIS_MODULE,
90 .base.cra_name = "__cbc(twofish)",
91 .base
[all...]
H A Dcast6_avx_glue.c31 return cast6_setkey(&tfm->base, key, keylen);
67 .base.cra_name = "__ecb(cast6)",
68 .base.cra_driver_name = "__ecb-cast6-avx",
69 .base.cra_priority = 200,
70 .base.cra_flags = CRYPTO_ALG_INTERNAL,
71 .base.cra_blocksize = CAST6_BLOCK_SIZE,
72 .base.cra_ctxsize = sizeof(struct cast6_ctx),
73 .base.cra_module = THIS_MODULE,
80 .base.cra_name = "__cbc(cast6)",
81 .base
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H A Dcast5_avx_glue.c31 return cast5_setkey(&tfm->base, key, keylen);
67 .base.cra_name = "__ecb(cast5)",
68 .base.cra_driver_name = "__ecb-cast5-avx",
69 .base.cra_priority = 200,
70 .base.cra_flags = CRYPTO_ALG_INTERNAL,
71 .base.cra_blocksize = CAST5_BLOCK_SIZE,
72 .base.cra_ctxsize = sizeof(struct cast5_ctx),
73 .base.cra_module = THIS_MODULE,
80 .base.cra_name = "__cbc(cast5)",
81 .base
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/linux-master/drivers/clocksource/
H A Dclksrc_st_lpc.c27 void __iomem *base; member in struct:st_clksrc_ddata
32 writel_relaxed(0, ddata.base + LPC_LPT_START_OFF);
33 writel_relaxed(0, ddata.base + LPC_LPT_MSB_OFF);
34 writel_relaxed(0, ddata.base + LPC_LPT_LSB_OFF);
35 writel_relaxed(1, ddata.base + LPC_LPT_START_OFF);
40 return (u64)readl_relaxed(ddata.base + LPC_LPT_LSB_OFF);
54 ret = clocksource_mmio_init(ddata.base + LPC_LPT_LSB_OFF,
106 ddata.base = of_iomap(np, 0);
107 if (!ddata.base) {
114 iounmap(ddata.base);
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H A Dtimer-lpc32xx.c42 void __iomem *base; member in struct:lpc32xx_clock_event_ddata
75 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR);
76 writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0);
77 writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR);
88 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR);
102 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR);
106 LPC32XX_TIMER_MCR_MR0S, ddata->base + LPC32XX_TIMER_MCR);
117 ddata->base + LPC32XX_TIMER_MCR);
123 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR);
124 writel_relaxed(ddata->ticks_per_jiffy, ddata->base
157 void __iomem *base; local
218 void __iomem *base; local
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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A Dgk104.c47 gk104_ce_intr_launcherr(struct nvkm_engine *ce, const u32 base) argument
51 u32 stat = nvkm_rd32(device, 0x104f14 + base);
55 nvkm_wr32(device, 0x104f14 + base, 0x00000000);
63 const u32 base = subdev->inst * 0x1000; local
64 u32 mask = nvkm_rd32(device, 0x104904 + base);
65 u32 intr = nvkm_rd32(device, 0x104908 + base) & mask;
68 nvkm_wr32(device, 0x104908 + base, 0x00000001);
73 nvkm_wr32(device, 0x104908 + base, 0x00000002);
77 gk104_ce_intr_launcherr(ce, base);
78 nvkm_wr32(device, 0x104908 + base,
[all...]
/linux-master/drivers/crypto/intel/keembay/
H A Dkeembay-ocs-aes-core.c197 tfm->base.crt_flags &
323 skcipher_request_set_callback(subreq, req->base.flags, NULL,
649 aead_request_set_callback(subreq, req->base.flags,
650 req->base.complete, req->base.data);
949 container_of(areq, struct skcipher_request, base);
976 struct aead_request, base);
1150 const char *alg_name = crypto_tfm_alg_name(&tfm->base);
1197 const char *alg_name = crypto_tfm_alg_name(&tfm->base);
1261 .base
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/linux-master/kernel/time/
H A Dtimer.c192 * If multiple bases need to be locked, use the base ordering for lock
207 * struct timer_base - Per CPU timer base (number of base depends on config)
226 * @clk: clock of the timer base; is updated before enqueue
233 * @cpu: Number of CPU the timer base belongs to
239 * base. Deferrable timers, which are enqueued remotely
241 * for this base.
242 * @timers_pending: Is set, when a timer is pending in the base. It is only
624 trigger_dyntick_cpu(struct timer_base *base, struct timer_list *timer) argument
630 * nothing will be done with the deferrable timer base
656 enqueue_timer(struct timer_base *base, struct timer_list *timer, unsigned int idx, unsigned long bucket_expiry) argument
683 internal_add_timer(struct timer_base *base, struct timer_list *timer) argument
941 detach_if_pending(struct timer_list *timer, struct timer_base *base, bool clear_pending) argument
961 struct timer_base *base; local
977 struct timer_base *base; local
995 __forward_timer_base(struct timer_base *base, unsigned long basej) argument
1019 forward_timer_base(struct timer_base *base) argument
1040 struct timer_base *base; variable in typeref:struct:timer_base
1069 struct timer_base *base, *new_base; local
1349 struct timer_base *new_base, *base; local
1410 struct timer_base *base; local
1501 struct timer_base *base; local
1542 timer_base_init_expiry_lock(struct timer_base *base) argument
1547 timer_base_lock_expiry(struct timer_base *base) argument
1552 timer_base_unlock_expiry(struct timer_base *base) argument
1564 timer_sync_wait_running(struct timer_base *base) argument
1590 struct timer_base *base = get_timer_base(tf); local
1607 timer_base_init_expiry_lock(struct timer_base *base) argument
1608 timer_base_lock_expiry(struct timer_base *base) argument
1609 timer_base_unlock_expiry(struct timer_base *base) argument
1610 timer_sync_wait_running(struct timer_base *base) argument
1811 expire_timers(struct timer_base *base, struct hlist_head *head) argument
1852 collect_expired_timers(struct timer_base *base, struct hlist_head *heads) argument
1882 next_pending_bucket(struct timer_base *base, unsigned offset, unsigned clk) argument
1902 next_expiry_recalc(struct timer_base *base) argument
2007 next_timer_interrupt(struct timer_base *base, unsigned long basej) argument
2179 struct timer_base *base = per_cpu_ptr(&timer_bases[BASE_GLOBAL], cpu); local
2388 __run_timers(struct timer_base *base) argument
2422 __run_timer_base(struct timer_base *base) argument
2436 struct timer_base *base = this_cpu_ptr(&timer_bases[index]); local
2461 struct timer_base *base = this_cpu_ptr(&timer_bases[BASE_LOCAL]); local
2647 struct timer_base *base; local
2700 struct timer_base *base; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dio_link_encoder.c38 enc10->base.ctx
40 enc10->base.ctx->logger
106 enc10->base.funcs = &dcn30_link_enc_funcs;
107 enc10->base.ctx = init_data->ctx;
108 enc10->base.id = init_data->encoder;
110 enc10->base.hpd_source = init_data->hpd_source;
111 enc10->base.connector = init_data->connector;
113 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
115 enc10->base.features = *enc_features;
117 enc10->base
[all...]
/linux-master/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_28nm.c101 void __iomem *base = pll_28nm->phy->pll_base; local
107 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG,
109 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1);
120 void __iomem *base = pll_28nm->phy->pll_base; local
131 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3);
142 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance);
145 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
146 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
171 sdm_cfg1 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
198 dsi_phy_write(base
244 void __iomem *base = pll_28nm->phy->pll_base; local
291 void __iomem *base = pll_28nm->phy->pll_base; local
385 void __iomem *base = pll_28nm->phy->pll_base; local
453 void __iomem *base = pll_28nm->phy->pll_base; local
560 void __iomem *base = pll_28nm->phy->pll_base; local
577 void __iomem *base = pll_28nm->phy->pll_base; local
701 void __iomem *base = phy->base; local
733 void __iomem *base = phy->reg_base; local
748 void __iomem *base = phy->reg_base; local
783 void __iomem *base = phy->base; local
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/linux-master/arch/powerpc/include/asm/
H A Dppc_asm.h23 * op reg, (offset + (width * reg))(base)
28 .macro OP_REGS op, width, start, end, base, offset variable
31 \op .Lreg, \offset + \width * .Lreg(\base)
55 #define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0
56 #define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0
57 #define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base)
58 #define REST_NVGPRS(base) REST_GPR
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/linux-master/tools/testing/selftests/powerpc/primitives/asm/
H A Dppc_asm.h23 * op reg, (offset + (width * reg))(base)
28 .macro OP_REGS op, width, start, end, base, offset variable
31 \op .Lreg, \offset + \width * .Lreg(\base)
55 #define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0
56 #define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0
57 #define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base)
58 #define REST_NVGPRS(base) REST_GPR
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_link_encoder.c45 enc10->base.ctx
47 enc10->base.ctx->logger
163 cmd->query_dp_alt.data.phy_id = phy_id_from_transmitter(enc10->base.transmitter);
244 enc10->base.funcs = &dcn32_link_enc_funcs;
245 enc10->base.ctx = init_data->ctx;
246 enc10->base.id = init_data->encoder;
248 enc10->base.hpd_source = init_data->hpd_source;
249 enc10->base.connector = init_data->connector;
251 if (enc10->base.connector.id == CONNECTOR_ID_USBC)
252 enc10->base
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dio_link_encoder.c32 enc10->base.ctx
34 enc10->base.ctx->logger
180 enc10->base.funcs = &dcn35_link_enc_funcs;
181 enc10->base.ctx = init_data->ctx;
182 enc10->base.id = init_data->encoder;
184 enc10->base.hpd_source = init_data->hpd_source;
185 enc10->base.connector = init_data->connector;
187 if (enc10->base.connector.id == CONNECTOR_ID_USBC)
188 enc10->base.features.flags.bits.DP_IS_USB_C = 1;
190 enc10->base
[all...]
/linux-master/drivers/gpio/
H A Dgpio-mlxbf.c43 void __iomem *base; member in struct:mlxbf_gpio_state
61 gs->base = devm_platform_ioremap_resource(pdev, 0);
62 if (IS_ERR(gs->base))
63 return PTR_ERR(gs->base);
67 gs->base + MLXBF_GPIO_PIN_STATE,
70 gs->base + MLXBF_GPIO_PIN_DIR_O,
71 gs->base + MLXBF_GPIO_PIN_DIR_I,
95 gs->csave_regs.scratchpad = readq(gs->base + MLXBF_GPIO_SCRATCHPAD);
97 readq(gs->base + MLXBF_GPIO_PAD_CONTROL_FIRST_WORD);
99 readq(gs->base
[all...]
/linux-master/arch/arm/mach-s3c/
H A Dgpio-samsung.c43 void __iomem *reg = chip->base + 0x08;
58 void __iomem *reg = chip->base + 0x08;
71 void __iomem *reg = chip->base;
106 con = __raw_readl(chip->base);
134 void __iomem *reg = chip->base;
169 void __iomem *reg = chip->base;
238 * base + 0x00: Control register, 2 bits per gpio
241 * base + 0x04: Data register, 1 bit per gpio
248 void __iomem *base = ourchip->base; local
267 void __iomem *base = ourchip->base; local
311 void __iomem *base = ourchip->base; local
330 void __iomem *base = ourchip->base; local
380 void __iomem *base = ourchip->base; local
402 void __iomem *base = ourchip->base; local
437 void __iomem *base = ourchip->base; local
537 samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip, int nr_chips, void __iomem *base, unsigned int offset) argument
574 samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip, int nr_chips, void __iomem *base) argument
[all...]
/linux-master/arch/powerpc/kernel/
H A Dfpu.S26 #define __REST_1FPVSR(n,c,base) \
30 REST_FPR(n,base); \
32 2: REST_VSR(n,c,base); \
35 #define __REST_32FPVSRS(n,c,base) \
39 REST_32FPRS(n,base); \
41 2: REST_32VSRS(n,c,base); \
44 #define __SAVE_32FPVSRS(n,c,base) \
48 SAVE_32FPRS(n,base); \
50 2: SAVE_32VSRS(n,c,base); \
53 #define __REST_1FPVSR(n,b,base) REST_FP
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Completed in 191 milliseconds

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