drivers/clocksource/timer-lpc32xx.c

42 	void __iomem *base;
75 	writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR);
76 	writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0);
77 	writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR);
88 	writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR);
102 	writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR);
106 		       LPC32XX_TIMER_MCR_MR0S, ddata->base + LPC32XX_TIMER_MCR);
117 		       ddata->base + LPC32XX_TIMER_MCR);
123 	writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR);
124 	writel_relaxed(ddata->ticks_per_jiffy, ddata->base + LPC32XX_TIMER_MR0);
125 	writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR);
135 	writel_relaxed(LPC32XX_TIMER_IR_MR0INT, ddata->base + LPC32XX_TIMER_IR);
157 	void __iomem *base;
174 	base = of_iomap(np, 0);
175 	if (!base) {
186 	writel_relaxed(LPC32XX_TIMER_TCR_CRST, base + LPC32XX_TIMER_TCR);
187 	writel_relaxed(0, base + LPC32XX_TIMER_PR);
188 	writel_relaxed(0, base + LPC32XX_TIMER_MCR);
189 	writel_relaxed(0, base + LPC32XX_TIMER_CTCR);
190 	writel_relaxed(LPC32XX_TIMER_TCR_CEN, base + LPC32XX_TIMER_TCR);
193 	ret = clocksource_mmio_init(base + LPC32XX_TIMER_TC, "lpc3220 timer",
200 	clocksource_timer_counter = base + LPC32XX_TIMER_TC;
208 	iounmap(base);
218 	void __iomem *base;
235 	base = of_iomap(np, 0);
236 	if (!base) {
253 	writel_relaxed(0, base + LPC32XX_TIMER_TCR);
254 	writel_relaxed(0, base + LPC32XX_TIMER_PR);
255 	writel_relaxed(0, base + LPC32XX_TIMER_CTCR);
256 	writel_relaxed(LPC32XX_TIMER_IR_MR0INT, base + LPC32XX_TIMER_IR);
259 	lpc32xx_clk_event_ddata.base = base;
275 	iounmap(base);