1/* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4#ifndef _ASM_POWERPC_PPC_ASM_H 5#define _ASM_POWERPC_PPC_ASM_H 6 7#include <linux/stringify.h> 8#include <asm/asm-compat.h> 9#include <asm/processor.h> 10#include <asm/ppc-opcode.h> 11#include <asm/firmware.h> 12#include <asm/feature-fixups.h> 13#include <asm/extable.h> 14 15#ifdef __ASSEMBLY__ 16 17#define SZL (BITS_PER_LONG/8) 18 19/* 20 * This expands to a sequence of operations with reg incrementing from 21 * start to end inclusive, of this form: 22 * 23 * op reg, (offset + (width * reg))(base) 24 * 25 * Note that offset is not the offset of the first operation unless start 26 * is zero (or width is zero). 27 */ 28.macro OP_REGS op, width, start, end, base, offset 29 .Lreg=\start 30 .rept (\end - \start + 1) 31 \op .Lreg, \offset + \width * .Lreg(\base) 32 .Lreg=.Lreg+1 33 .endr 34.endm 35 36/* 37 * This expands to a sequence of register clears for regs start to end 38 * inclusive, of the form: 39 * 40 * li rN, 0 41 */ 42.macro ZEROIZE_REGS start, end 43 .Lreg=\start 44 .rept (\end - \start + 1) 45 li .Lreg, 0 46 .Lreg=.Lreg+1 47 .endr 48.endm 49 50/* 51 * Macros for storing registers into and loading registers from 52 * exception frames. 53 */ 54#ifdef __powerpc64__ 55#define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0 56#define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0 57#define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base) 58#define REST_NVGPRS(base) REST_GPRS(14, 31, base) 59#else 60#define SAVE_GPRS(start, end, base) OP_REGS stw, 4, start, end, base, GPR0 61#define REST_GPRS(start, end, base) OP_REGS lwz, 4, start, end, base, GPR0 62#define SAVE_NVGPRS(base) SAVE_GPRS(13, 31, base) 63#define REST_NVGPRS(base) REST_GPRS(13, 31, base) 64#endif 65 66#define ZEROIZE_GPRS(start, end) ZEROIZE_REGS start, end 67#ifdef __powerpc64__ 68#define ZEROIZE_NVGPRS() ZEROIZE_GPRS(14, 31) 69#else 70#define ZEROIZE_NVGPRS() ZEROIZE_GPRS(13, 31) 71#endif 72#define ZEROIZE_GPR(n) ZEROIZE_GPRS(n, n) 73 74#define SAVE_GPR(n, base) SAVE_GPRS(n, n, base) 75#define REST_GPR(n, base) REST_GPRS(n, n, base) 76 77/* macros for handling user register sanitisation */ 78#ifdef CONFIG_INTERRUPT_SANITIZE_REGISTERS 79#define SANITIZE_SYSCALL_GPRS() ZEROIZE_GPR(0); \ 80 ZEROIZE_GPRS(5, 12); \ 81 ZEROIZE_NVGPRS() 82#define SANITIZE_GPR(n) ZEROIZE_GPR(n) 83#define SANITIZE_GPRS(start, end) ZEROIZE_GPRS(start, end) 84#define SANITIZE_NVGPRS() ZEROIZE_NVGPRS() 85#define SANITIZE_RESTORE_NVGPRS() REST_NVGPRS(r1) 86#define HANDLER_RESTORE_NVGPRS() 87#else 88#define SANITIZE_SYSCALL_GPRS() 89#define SANITIZE_GPR(n) 90#define SANITIZE_GPRS(start, end) 91#define SANITIZE_NVGPRS() 92#define SANITIZE_RESTORE_NVGPRS() 93#define HANDLER_RESTORE_NVGPRS() REST_NVGPRS(r1) 94#endif /* CONFIG_INTERRUPT_SANITIZE_REGISTERS */ 95 96#define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) 97#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 98#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 99#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 100#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 101#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 102#define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) 103#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 104#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 105#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 106#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 107#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 108 109#define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b 110#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 111#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 112#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 113#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 114#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 115#define REST_VR(n,b,base) li b,16*(n); lvx n,base,b 116#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 117#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 118#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 119#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 120#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 121 122#ifdef __BIG_ENDIAN__ 123#define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) 124#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) 125#else 126#define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ 127 STXVD2X(n,b,base); \ 128 XXSWAPD(n,n) 129 130#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ 131 XXSWAPD(n,n) 132#endif 133/* Save the lower 32 VSRs in the thread VSR region */ 134#define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) 135#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 136#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 137#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 138#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 139#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 140#define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) 141#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 142#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 143#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 144#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 145#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 146 147/* 148 * b = base register for addressing, o = base offset from register of 1st EVR 149 * n = first EVR, s = scratch 150 */ 151#define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 152#define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 153#define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 154#define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 155#define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 156#define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 157#define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 158#define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 159#define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 160#define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 161#define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 162#define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 163 164/* Macros to adjust thread priority for hardware multithreading */ 165#define HMT_VERY_LOW or 31,31,31 # very low priority 166#define HMT_LOW or 1,1,1 167#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 168#define HMT_MEDIUM or 2,2,2 169#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 170#define HMT_HIGH or 3,3,3 171#define HMT_EXTRA_HIGH or 7,7,7 # power7 only 172 173#ifdef CONFIG_PPC64 174#define ULONG_SIZE 8 175#else 176#define ULONG_SIZE 4 177#endif 178#define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 179#define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 180 181#ifdef __KERNEL__ 182 183/* 184 * Used to name C functions called from asm 185 */ 186#ifdef CONFIG_PPC_KERNEL_PCREL 187#define CFUNC(name) name@notoc 188#else 189#define CFUNC(name) name 190#endif 191 192/* 193 * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit 194 * version below in the else case of the ifdef. 195 */ 196#ifdef __powerpc64__ 197 198#define STACKFRAMESIZE 256 199#define __STK_REG(i) (112 + ((i)-14)*8) 200#define STK_REG(i) __STK_REG(__REG_##i) 201 202#ifdef CONFIG_PPC64_ELF_ABI_V2 203#define STK_GOT 24 204#define STK_PARAM_AREA 32 205#else 206#define STK_GOT 40 207#define STK_PARAM_AREA 48 208#endif 209 210#define __STK_PARAM(i) (STK_PARAM_AREA + ((i)-3)*8) 211#define STK_PARAM(i) __STK_PARAM(__REG_##i) 212 213#ifdef CONFIG_PPC64_ELF_ABI_V2 214 215#define _GLOBAL(name) \ 216 .align 2 ; \ 217 .type name,@function; \ 218 .globl name; \ 219name: 220 221#ifdef CONFIG_PPC_KERNEL_PCREL 222#define _GLOBAL_TOC _GLOBAL 223#else 224#define _GLOBAL_TOC(name) \ 225 .align 2 ; \ 226 .type name,@function; \ 227 .globl name; \ 228name: \ 2290: addis r2,r12,(.TOC.-0b)@ha; \ 230 addi r2,r2,(.TOC.-0b)@l; \ 231 .localentry name,.-name 232#endif 233 234#define DOTSYM(a) a 235 236#else 237 238#define XGLUE(a,b) a##b 239#define GLUE(a,b) XGLUE(a,b) 240 241#define _GLOBAL(name) \ 242 .align 2 ; \ 243 .globl name; \ 244 .globl GLUE(.,name); \ 245 .pushsection ".opd","aw"; \ 246name: \ 247 .quad GLUE(.,name); \ 248 .quad .TOC.@tocbase; \ 249 .quad 0; \ 250 .popsection; \ 251 .type GLUE(.,name),@function; \ 252GLUE(.,name): 253 254#define _GLOBAL_TOC(name) _GLOBAL(name) 255 256#define DOTSYM(a) GLUE(.,a) 257 258#endif 259 260#else /* 32-bit */ 261 262#define _GLOBAL(n) \ 263 .globl n; \ 264n: 265 266#define _GLOBAL_TOC(name) _GLOBAL(name) 267 268#define DOTSYM(a) a 269 270#endif 271 272/* 273 * __kprobes (the C annotation) puts the symbol into the .kprobes.text 274 * section, which gets emitted at the end of regular text. 275 * 276 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to 277 * a blacklist. The former is for core kprobe functions/data, the 278 * latter is for those that incdentially must be excluded from probing 279 * and allows them to be linked at more optimal location within text. 280 */ 281#ifdef CONFIG_KPROBES 282#define _ASM_NOKPROBE_SYMBOL(entry) \ 283 .pushsection "_kprobe_blacklist","aw"; \ 284 PPC_LONG (entry) ; \ 285 .popsection 286#else 287#define _ASM_NOKPROBE_SYMBOL(entry) 288#endif 289 290#define FUNC_START(name) _GLOBAL(name) 291#define FUNC_END(name) 292 293/* 294 * LOAD_REG_IMMEDIATE(rn, expr) 295 * Loads the value of the constant expression 'expr' into register 'rn' 296 * using immediate instructions only. Use this when it's important not 297 * to reference other data (i.e. on ppc64 when the TOC pointer is not 298 * valid) and when 'expr' is a constant or absolute address. 299 * 300 * LOAD_REG_ADDR(rn, name) 301 * Loads the address of label 'name' into register 'rn'. Use this when 302 * you don't particularly need immediate instructions only, but you need 303 * the whole address in one register (e.g. it's a structure address and 304 * you want to access various offsets within it). On ppc32 this is 305 * identical to LOAD_REG_IMMEDIATE. 306 * 307 * LOAD_REG_ADDR_PIC(rn, name) 308 * Loads the address of label 'name' into register 'run'. Use this when 309 * the kernel doesn't run at the linked or relocated address. Please 310 * note that this macro will clobber the lr register. 311 * 312 * LOAD_REG_ADDRBASE(rn, name) 313 * ADDROFF(name) 314 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 315 * register 'rn'. ADDROFF(name) returns the remainder of the address as 316 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 317 * in size, so is suitable for use directly as an offset in load and store 318 * instructions. Use this when loading/storing a single word or less as: 319 * LOAD_REG_ADDRBASE(rX, name) 320 * ld rY,ADDROFF(name)(rX) 321 */ 322 323/* Be careful, this will clobber the lr register. */ 324#define LOAD_REG_ADDR_PIC(reg, name) \ 325 bcl 20,31,$+4; \ 3260: mflr reg; \ 327 addis reg,reg,(name - 0b)@ha; \ 328 addi reg,reg,(name - 0b)@l; 329 330#if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH) 331#define __AS_ATHIGH high 332#else 333#define __AS_ATHIGH h 334#endif 335 336.macro __LOAD_REG_IMMEDIATE_32 r, x 337 .if (\x) >= 0x8000 || (\x) < -0x8000 338 lis \r, (\x)@__AS_ATHIGH 339 .if (\x) & 0xffff != 0 340 ori \r, \r, (\x)@l 341 .endif 342 .else 343 li \r, (\x)@l 344 .endif 345.endm 346 347.macro __LOAD_REG_IMMEDIATE r, x 348 .if (\x) >= 0x80000000 || (\x) < -0x80000000 349 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32 350 sldi \r, \r, 32 351 .if (\x) & 0xffff0000 != 0 352 oris \r, \r, (\x)@__AS_ATHIGH 353 .endif 354 .if (\x) & 0xffff != 0 355 ori \r, \r, (\x)@l 356 .endif 357 .else 358 __LOAD_REG_IMMEDIATE_32 \r, \x 359 .endif 360.endm 361 362#ifdef __powerpc64__ 363 364#ifdef CONFIG_PPC_KERNEL_PCREL 365#define __LOAD_PACA_TOC(reg) \ 366 li reg,-1 367#else 368#define __LOAD_PACA_TOC(reg) \ 369 ld reg,PACATOC(r13) 370#endif 371 372#define LOAD_PACA_TOC() \ 373 __LOAD_PACA_TOC(r2) 374 375#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr 376 377#define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \ 378 lis tmp, (expr)@highest; \ 379 lis reg, (expr)@__AS_ATHIGH; \ 380 ori tmp, tmp, (expr)@higher; \ 381 ori reg, reg, (expr)@l; \ 382 rldimi reg, tmp, 32, 0 383 384#ifdef CONFIG_PPC_KERNEL_PCREL 385#define LOAD_REG_ADDR(reg,name) \ 386 pla reg,name@pcrel 387 388#else 389#define LOAD_REG_ADDR(reg,name) \ 390 addis reg,r2,name@toc@ha; \ 391 addi reg,reg,name@toc@l 392#endif 393 394#ifdef CONFIG_PPC_BOOK3E_64 395/* 396 * This is used in register-constrained interrupt handlers. Not to be used 397 * by BOOK3S. ld complains with "got/toc optimization is not supported" if r2 398 * is not used for the TOC offset, so use @got(tocreg). If the interrupt 399 * handlers saved r2 instead, LOAD_REG_ADDR could be used. 400 */ 401#define LOAD_REG_ADDR_ALTTOC(reg,tocreg,name) \ 402 ld reg,name@got(tocreg) 403#endif 404 405#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 406#define ADDROFF(name) 0 407 408/* offsets for stack frame layout */ 409#define LRSAVE 16 410 411/* 412 * GCC stack frames follow a different pattern on 32 vs 64. This can be used 413 * to make asm frames be consistent with C. 414 */ 415#define PPC_CREATE_STACK_FRAME(size) \ 416 mflr r0; \ 417 std r0,16(r1); \ 418 stdu r1,-(size)(r1) 419 420#else /* 32-bit */ 421 422#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr 423 424#define LOAD_REG_IMMEDIATE_SYM(reg,expr) \ 425 lis reg,(expr)@ha; \ 426 addi reg,reg,(expr)@l; 427 428#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name) 429 430#define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 431#define ADDROFF(name) name@l 432 433/* offsets for stack frame layout */ 434#define LRSAVE 4 435 436#define PPC_CREATE_STACK_FRAME(size) \ 437 stwu r1,-(size)(r1); \ 438 mflr r0; \ 439 stw r0,(size+4)(r1) 440 441#endif 442 443/* various errata or part fixups */ 444#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_E500) 445#define MFTB(dest) \ 44690: mfspr dest, SPRN_TBRL; \ 447BEGIN_FTR_SECTION_NESTED(96); \ 448 cmpwi dest,0; \ 449 beq- 90b; \ 450END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 451#else 452#define MFTB(dest) MFTBL(dest) 453#endif 454 455#ifdef CONFIG_PPC_8xx 456#define MFTBL(dest) mftb dest 457#define MFTBU(dest) mftbu dest 458#else 459#define MFTBL(dest) mfspr dest, SPRN_TBRL 460#define MFTBU(dest) mfspr dest, SPRN_TBRU 461#endif 462 463#ifndef CONFIG_SMP 464#define TLBSYNC 465#else 466#define TLBSYNC tlbsync; sync 467#endif 468 469#ifdef CONFIG_PPC64 470#define MTOCRF(FXM, RS) \ 471 BEGIN_FTR_SECTION_NESTED(848); \ 472 mtcrf (FXM), RS; \ 473 FTR_SECTION_ELSE_NESTED(848); \ 474 mtocrf (FXM), RS; \ 475 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 476#endif 477 478/* 479 * This instruction is not implemented on the PPC 603 or 601; however, on 480 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 481 * All of these instructions exist in the 8xx, they have magical powers, 482 * and they must be used. 483 */ 484 485#if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx) 486#define tlbia \ 487 li r4,1024; \ 488 mtctr r4; \ 489 lis r4,KERNELBASE@h; \ 490 .machine push; \ 491 .machine "power4"; \ 4920: tlbie r4; \ 493 .machine pop; \ 494 addi r4,r4,0x1000; \ 495 bdnz 0b 496#endif 497 498 499#ifdef CONFIG_IBM440EP_ERR42 500#define PPC440EP_ERR42 isync 501#else 502#define PPC440EP_ERR42 503#endif 504 505/* The following stops all load and store data streams associated with stream 506 * ID (ie. streams created explicitly). The embedded and server mnemonics for 507 * dcbt are different so this must only be used for server. 508 */ 509#define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \ 510 lis scratch,0x60000000@h; \ 511 .machine push; \ 512 .machine power4; \ 513 dcbt 0,scratch,0b01010; \ 514 .machine pop; 515 516#define DCBT_SETUP_STREAMS(from, from_parms, to, to_parms, scratch) \ 517 lis scratch,0x8000; /* GO=1 */ \ 518 clrldi scratch,scratch,32; \ 519 .machine push; \ 520 .machine power4; \ 521 /* setup read stream 0 */ \ 522 dcbt 0,from,0b01000; /* addr from */ \ 523 dcbt 0,from_parms,0b01010; /* length and depth from */ \ 524 /* setup write stream 1 */ \ 525 dcbtst 0,to,0b01000; /* addr to */ \ 526 dcbtst 0,to_parms,0b01010; /* length and depth to */ \ 527 eieio; \ 528 dcbt 0,scratch,0b01010; /* all streams GO */ \ 529 .machine pop; 530 531/* 532 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 533 * keep the address intact to be compatible with code shared with 534 * 32-bit classic. 535 * 536 * On the other hand, I find it useful to have them behave as expected 537 * by their name (ie always do the addition) on 64-bit BookE 538 */ 539#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 540#define toreal(rd) 541#define fromreal(rd) 542 543/* 544 * We use addis to ensure compatibility with the "classic" ppc versions of 545 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 546 * converting the address in r0, and so this version has to do that too 547 * (i.e. set register rd to 0 when rs == 0). 548 */ 549#define tophys(rd,rs) \ 550 addis rd,rs,0 551 552#define tovirt(rd,rs) \ 553 addis rd,rs,0 554 555#elif defined(CONFIG_PPC64) 556#define toreal(rd) /* we can access c000... in real mode */ 557#define fromreal(rd) 558 559#define tophys(rd,rs) \ 560 clrldi rd,rs,2 561 562#define tovirt(rd,rs) \ 563 rotldi rd,rs,16; \ 564 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 565 rotldi rd,rd,48 566#else 567#define toreal(rd) tophys(rd,rd) 568#define fromreal(rd) tovirt(rd,rd) 569 570#define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h 571#define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h 572#endif 573 574#ifdef CONFIG_PPC_BOOK3S_64 575#define MTMSRD(r) mtmsrd r 576#define MTMSR_EERI(reg) mtmsrd reg,1 577#else 578#define MTMSRD(r) mtmsr r 579#define MTMSR_EERI(reg) mtmsr reg 580#endif 581 582#endif /* __KERNEL__ */ 583 584/* The boring bits... */ 585 586/* Condition Register Bit Fields */ 587 588#define cr0 0 589#define cr1 1 590#define cr2 2 591#define cr3 3 592#define cr4 4 593#define cr5 5 594#define cr6 6 595#define cr7 7 596 597 598/* 599 * General Purpose Registers (GPRs) 600 * 601 * The lower case r0-r31 should be used in preference to the upper 602 * case R0-R31 as they provide more error checking in the assembler. 603 * Use R0-31 only when really nessesary. 604 */ 605 606#define r0 %r0 607#define r1 %r1 608#define r2 %r2 609#define r3 %r3 610#define r4 %r4 611#define r5 %r5 612#define r6 %r6 613#define r7 %r7 614#define r8 %r8 615#define r9 %r9 616#define r10 %r10 617#define r11 %r11 618#define r12 %r12 619#define r13 %r13 620#define r14 %r14 621#define r15 %r15 622#define r16 %r16 623#define r17 %r17 624#define r18 %r18 625#define r19 %r19 626#define r20 %r20 627#define r21 %r21 628#define r22 %r22 629#define r23 %r23 630#define r24 %r24 631#define r25 %r25 632#define r26 %r26 633#define r27 %r27 634#define r28 %r28 635#define r29 %r29 636#define r30 %r30 637#define r31 %r31 638 639 640/* Floating Point Registers (FPRs) */ 641 642#define fr0 0 643#define fr1 1 644#define fr2 2 645#define fr3 3 646#define fr4 4 647#define fr5 5 648#define fr6 6 649#define fr7 7 650#define fr8 8 651#define fr9 9 652#define fr10 10 653#define fr11 11 654#define fr12 12 655#define fr13 13 656#define fr14 14 657#define fr15 15 658#define fr16 16 659#define fr17 17 660#define fr18 18 661#define fr19 19 662#define fr20 20 663#define fr21 21 664#define fr22 22 665#define fr23 23 666#define fr24 24 667#define fr25 25 668#define fr26 26 669#define fr27 27 670#define fr28 28 671#define fr29 29 672#define fr30 30 673#define fr31 31 674 675/* AltiVec Registers (VPRs) */ 676 677#define v0 0 678#define v1 1 679#define v2 2 680#define v3 3 681#define v4 4 682#define v5 5 683#define v6 6 684#define v7 7 685#define v8 8 686#define v9 9 687#define v10 10 688#define v11 11 689#define v12 12 690#define v13 13 691#define v14 14 692#define v15 15 693#define v16 16 694#define v17 17 695#define v18 18 696#define v19 19 697#define v20 20 698#define v21 21 699#define v22 22 700#define v23 23 701#define v24 24 702#define v25 25 703#define v26 26 704#define v27 27 705#define v28 28 706#define v29 29 707#define v30 30 708#define v31 31 709 710/* VSX Registers (VSRs) */ 711 712#define vs0 0 713#define vs1 1 714#define vs2 2 715#define vs3 3 716#define vs4 4 717#define vs5 5 718#define vs6 6 719#define vs7 7 720#define vs8 8 721#define vs9 9 722#define vs10 10 723#define vs11 11 724#define vs12 12 725#define vs13 13 726#define vs14 14 727#define vs15 15 728#define vs16 16 729#define vs17 17 730#define vs18 18 731#define vs19 19 732#define vs20 20 733#define vs21 21 734#define vs22 22 735#define vs23 23 736#define vs24 24 737#define vs25 25 738#define vs26 26 739#define vs27 27 740#define vs28 28 741#define vs29 29 742#define vs30 30 743#define vs31 31 744#define vs32 32 745#define vs33 33 746#define vs34 34 747#define vs35 35 748#define vs36 36 749#define vs37 37 750#define vs38 38 751#define vs39 39 752#define vs40 40 753#define vs41 41 754#define vs42 42 755#define vs43 43 756#define vs44 44 757#define vs45 45 758#define vs46 46 759#define vs47 47 760#define vs48 48 761#define vs49 49 762#define vs50 50 763#define vs51 51 764#define vs52 52 765#define vs53 53 766#define vs54 54 767#define vs55 55 768#define vs56 56 769#define vs57 57 770#define vs58 58 771#define vs59 59 772#define vs60 60 773#define vs61 61 774#define vs62 62 775#define vs63 63 776 777/* SPE Registers (EVPRs) */ 778 779#define evr0 0 780#define evr1 1 781#define evr2 2 782#define evr3 3 783#define evr4 4 784#define evr5 5 785#define evr6 6 786#define evr7 7 787#define evr8 8 788#define evr9 9 789#define evr10 10 790#define evr11 11 791#define evr12 12 792#define evr13 13 793#define evr14 14 794#define evr15 15 795#define evr16 16 796#define evr17 17 797#define evr18 18 798#define evr19 19 799#define evr20 20 800#define evr21 21 801#define evr22 22 802#define evr23 23 803#define evr24 24 804#define evr25 25 805#define evr26 26 806#define evr27 27 807#define evr28 28 808#define evr29 29 809#define evr30 30 810#define evr31 31 811 812#define RFSCV .long 0x4c0000a4 813 814/* 815 * Create an endian fixup trampoline 816 * 817 * This starts with a "tdi 0,0,0x48" instruction which is 818 * essentially a "trap never", and thus akin to a nop. 819 * 820 * The opcode for this instruction read with the wrong endian 821 * however results in a b . + 8 822 * 823 * So essentially we use that trick to execute the following 824 * trampoline in "reverse endian" if we are running with the 825 * MSR_LE bit set the "wrong" way for whatever endianness the 826 * kernel is built for. 827 */ 828 829#ifdef CONFIG_PPC_BOOK3E_64 830#define FIXUP_ENDIAN 831#else 832/* 833 * This version may be used in HV or non-HV context. 834 * MSR[EE] must be disabled. 835 */ 836#define FIXUP_ENDIAN \ 837 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 838 b 191f; /* Skip trampoline if endian is good */ \ 839 .long 0xa600607d; /* mfmsr r11 */ \ 840 .long 0x01006b69; /* xori r11,r11,1 */ \ 841 .long 0x00004039; /* li r10,0 */ \ 842 .long 0x6401417d; /* mtmsrd r10,1 */ \ 843 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 844 .long 0xa602487d; /* mflr r10 */ \ 845 .long 0x14004a39; /* addi r10,r10,20 */ \ 846 .long 0xa6035a7d; /* mtsrr0 r10 */ \ 847 .long 0xa6037b7d; /* mtsrr1 r11 */ \ 848 .long 0x2400004c; /* rfid */ \ 849191: 850 851/* 852 * This version that may only be used with MSR[HV]=1 853 * - Does not clear MSR[RI], so more robust. 854 * - Slightly smaller and faster. 855 */ 856#define FIXUP_ENDIAN_HV \ 857 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 858 b 191f; /* Skip trampoline if endian is good */ \ 859 .long 0xa600607d; /* mfmsr r11 */ \ 860 .long 0x01006b69; /* xori r11,r11,1 */ \ 861 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 862 .long 0xa602487d; /* mflr r10 */ \ 863 .long 0x14004a39; /* addi r10,r10,20 */ \ 864 .long 0xa64b5a7d; /* mthsrr0 r10 */ \ 865 .long 0xa64b7b7d; /* mthsrr1 r11 */ \ 866 .long 0x2402004c; /* hrfid */ \ 867191: 868 869#endif /* !CONFIG_PPC_BOOK3E_64 */ 870 871#endif /* __ASSEMBLY__ */ 872 873#define SOFT_MASK_TABLE(_start, _end) \ 874 stringify_in_c(.section __soft_mask_table,"a";)\ 875 stringify_in_c(.balign 8;) \ 876 stringify_in_c(.llong (_start);) \ 877 stringify_in_c(.llong (_end);) \ 878 stringify_in_c(.previous) 879 880#define RESTART_TABLE(_start, _end, _target) \ 881 stringify_in_c(.section __restart_table,"a";)\ 882 stringify_in_c(.balign 8;) \ 883 stringify_in_c(.llong (_start);) \ 884 stringify_in_c(.llong (_end);) \ 885 stringify_in_c(.llong (_target);) \ 886 stringify_in_c(.previous) 887 888#ifdef CONFIG_PPC_E500 889#define BTB_FLUSH(reg) \ 890 lis reg,BUCSR_INIT@h; \ 891 ori reg,reg,BUCSR_INIT@l; \ 892 mtspr SPRN_BUCSR,reg; \ 893 isync; 894#else 895#define BTB_FLUSH(reg) 896#endif /* CONFIG_PPC_E500 */ 897 898#if defined(CONFIG_PPC64_ELF_ABI_V1) 899#define STACK_FRAME_PARAMS 48 900#elif defined(CONFIG_PPC64_ELF_ABI_V2) 901#define STACK_FRAME_PARAMS 32 902#elif defined(CONFIG_PPC32) 903#define STACK_FRAME_PARAMS 8 904#endif 905 906#endif /* _ASM_POWERPC_PPC_ASM_H */ 907